* [PATCH v3 1/5] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux
2026-03-04 11:21 [PATCH v3 0/5] arm64: dts: lx2160a: fix pinmux issues, update solidrun boards Josua Mayer
@ 2026-03-04 11:21 ` Josua Mayer
2026-03-04 11:42 ` Josua Mayer
2026-03-04 11:21 ` [PATCH v3 2/5] arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word Josua Mayer
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Josua Mayer @ 2026-03-04 11:21 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Frank Li, linux-arm-kernel, devicetree, linux-kernel, Josua Mayer,
stable
Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
support bus recovery") introduced pinmux nodes for lx2160 i2c
interfaces, allowing runtime change between i2c and gpio functions
implementing bus recovery.
This has caused unintended side-effects on SolidRun boards where the
first application of a pinmux node cleared all bits in a 32-bit word
cleared, corrupting the configuration previously set by bootloader.
The LX2160 SoC is configured at power-on from RCW (Reset
Configuration Word) typically located in the first 4k of boot media.
This blob configures various clock rates and pin functions.
The pinmux for i2c specifically is part of configuration words RCWSR12,
RCWSR13 and RCWSR14 size 32 bit each.
These values are accessible at read-only addresses 0x01e0012c following.
For runtime (re-)configuration the SoC has a dynamic configuration area
where alternative settings can be applied. The counterparts of
RCWSR[12-14] can be overridden at 0x70010012c following.
The commit in question used this area to switch i2c pins between i2c and
gpio function at runtime using the pinctrl-single driver - which reads a
32-bit value, makes particular changes by bitmask and writes back the
new value.
SolidRun have observed that if the dynamic configuration is read first
(before a write), it reads as zero regardless the initial values set by
RCW. After the first write consecutive reads reflect the written value.
Because multiple pins are configured from a single 32-bit value, this
causes unintentional change of all bits (except those for i2c) being set
to zero when the pinctrl driver applies the first configuration.
See below a short list of which functions RCWSR12 alone controls:
LX2162-CF RCWSR12: 0b0000100000000000 0000000000000110
IIC2_PMUX ||| ||| || | ||| |||XXX : I2C/GPIO/CD-WP
IIC3_PMUX ||| ||| || | ||| XXX : I2C/GPIO/CAN/EVT
IIC4_PMUX ||| ||| || | |||XXX||| : I2C/GPIO/CAN/EVT
IIC5_PMUX ||| ||| || | XXX ||| : I2C/GPIO/SDHC-CLK
IIC6_PMUX ||| ||| || |XXX||| ||| : I2C/GPIO/SDHC-CLK
XSPI1_A_DATA74_PMUX ||| ||| XX X ||| ||| : XSPI/GPIO
XSPI1_A_DATA30_PMUX ||| |||XXX|| | ||| ||| : XSPI/GPIO
XSPI1_A_BASE_PMUX ||| XXX || | ||| ||| : XSPI/GPIO
SDHC1_BASE_PMUX |||XXX||| || | ||| ||| : SDHC/GPIO/SPI
SDHC1_DIR_PMUX XXX ||| || | ||| ||| : SDHC/GPIO/SPI
RESERVED XX||| ||| || | ||| ||| :
On LX2162A Clearfog the initial (and intended) value is 0x08000006 -
enabling card-detect on IIC2_PMUX and control GPIOs on SDHC1_DIR_PMUX.
Everything else is intentional zero (enabling I2C & XSPI).
By reading zero from dynamic configuration area, the commit in question
changes IIC2_PMUX to value 0 (I2C function), and SDHC1_DIR_PMUX to 0
(SDHC data direction function) - breaking card-detect and led gpios.
This issue should affect any board based on LX2160 SoC that is using the
same or earlier versions of NXP bootloader as SolidRun have tested, in
particular: LSDK-21.08 and LS-5.15.71-2.2.0.
Whether NXP added some extra initialisation in the bootloader on later
releases was not investigated. However bootloader upgrade should not be
necessary to run a newer Linux kernel.
To work around this issue it is possible to explicitly define ALL pins
controlled by any 32-bit value so that gradually after processing all
pinctrl nodes the correct value is reached on all bits.
This is a large task that should be done carefully on a per-board basis
and not globally through the SoC dtsi.
Therefore reverting the commit in question altogether was considered,
but received pushback in review with the argument that bus recovery was
important.
Instead add pinmux nodes for all fields or rcwsr12 as used by affected
SolidRun LX2160A Clearfog-CX & Honeycomb, and LX2162A Clearfog boards.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Cc: stable@vger.kernel.org
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 7 +++++++
.../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 ++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++++++++++++++++++++++
.../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 2 ++
.../boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 7 +++++++
5 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
index eec2cd6c6d32a..7f6e39e27ce5c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
@@ -162,6 +162,8 @@ rtc@51 {
};
&fspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
status = "okay";
flash@0 {
@@ -177,6 +179,11 @@ flash@0 {
};
};
+&pinmux_i2crv {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_14_12_pins>;
+};
+
&usb0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index af6258b2fe826..580ee9b3026e3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -89,6 +89,8 @@ &emdio2 {
};
&esdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 853b01452813a..be0ccab5a626b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1721,6 +1721,10 @@ i2c1_scl_gpio: i2c1-scl-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
+ esdhc0_cd_wp_pins: iic2-sdhc-pins {
+ pinctrl-single,bits = <0x0 0x6 0x7>;
+ };
+
i2c2_scl: i2c2-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
};
@@ -1753,6 +1757,26 @@ i2c5_scl_gpio: i2c5-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
+ fspi_data74_pins: xspi1-data74-pins {
+ pinctrl-single,bits = <0x0 0 (0x7 << 15)>;
+ };
+
+ fspi_data30_pins: xspi1-data30-pins {
+ pinctrl-single,bits = <0x0 0 (0x7 << 18)>;
+ };
+
+ fspi_dqs_sck_cs10_pins: xspi1-base-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
+ };
+
+ esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
+ };
+
+ gpio0_14_12_pins: sdhc1-dir-gpio-pins {
+ pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
+ };
+
i2c6_scl: i2c6-scl-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index eafef8718a0fe..8920326a06735 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -223,6 +223,8 @@ ethernet_phy8: ethernet-phy@15 {
};
&esdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
index e914291e63a1a..e1344942eaaee 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
@@ -30,6 +30,8 @@ &esdhc1 {
};
&fspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
status = "okay";
flash@0 {
@@ -80,3 +82,8 @@ rtc@6f {
reg = <0x6f>;
};
};
+
+&pinmux_i2crv {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_14_12_pins>;
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 1/5] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux
2026-03-04 11:21 ` [PATCH v3 1/5] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux Josua Mayer
@ 2026-03-04 11:42 ` Josua Mayer
0 siblings, 0 replies; 9+ messages in thread
From: Josua Mayer @ 2026-03-04 11:42 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Am 04.03.26 um 12:21 schrieb Josua Mayer:
> Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
> support bus recovery") introduced pinmux nodes for lx2160 i2c
> interfaces, allowing runtime change between i2c and gpio functions
> implementing bus recovery.
>
> This has caused unintended side-effects on SolidRun boards where the
> first application of a pinmux node cleared all bits in a 32-bit word
> cleared, corrupting the configuration previously set by bootloader.
>
> The LX2160 SoC is configured at power-on from RCW (Reset
> Configuration Word) typically located in the first 4k of boot media.
> This blob configures various clock rates and pin functions.
> The pinmux for i2c specifically is part of configuration words RCWSR12,
> RCWSR13 and RCWSR14 size 32 bit each.
> These values are accessible at read-only addresses 0x01e0012c following.
>
> For runtime (re-)configuration the SoC has a dynamic configuration area
> where alternative settings can be applied. The counterparts of
> RCWSR[12-14] can be overridden at 0x70010012c following.
>
> The commit in question used this area to switch i2c pins between i2c and
> gpio function at runtime using the pinctrl-single driver - which reads a
> 32-bit value, makes particular changes by bitmask and writes back the
> new value.
>
> SolidRun have observed that if the dynamic configuration is read first
> (before a write), it reads as zero regardless the initial values set by
> RCW. After the first write consecutive reads reflect the written value.
>
> Because multiple pins are configured from a single 32-bit value, this
> causes unintentional change of all bits (except those for i2c) being set
> to zero when the pinctrl driver applies the first configuration.
>
> See below a short list of which functions RCWSR12 alone controls:
>
> LX2162-CF RCWSR12: 0b0000100000000000 0000000000000110
> IIC2_PMUX ||| ||| || | ||| |||XXX : I2C/GPIO/CD-WP
> IIC3_PMUX ||| ||| || | ||| XXX : I2C/GPIO/CAN/EVT
> IIC4_PMUX ||| ||| || | |||XXX||| : I2C/GPIO/CAN/EVT
> IIC5_PMUX ||| ||| || | XXX ||| : I2C/GPIO/SDHC-CLK
> IIC6_PMUX ||| ||| || |XXX||| ||| : I2C/GPIO/SDHC-CLK
> XSPI1_A_DATA74_PMUX ||| ||| XX X ||| ||| : XSPI/GPIO
> XSPI1_A_DATA30_PMUX ||| |||XXX|| | ||| ||| : XSPI/GPIO
> XSPI1_A_BASE_PMUX ||| XXX || | ||| ||| : XSPI/GPIO
> SDHC1_BASE_PMUX |||XXX||| || | ||| ||| : SDHC/GPIO/SPI
> SDHC1_DIR_PMUX XXX ||| || | ||| ||| : SDHC/GPIO/SPI
> RESERVED XX||| ||| || | ||| ||| :
>
> On LX2162A Clearfog the initial (and intended) value is 0x08000006 -
> enabling card-detect on IIC2_PMUX and control GPIOs on SDHC1_DIR_PMUX.
> Everything else is intentional zero (enabling I2C & XSPI).
>
> By reading zero from dynamic configuration area, the commit in question
> changes IIC2_PMUX to value 0 (I2C function), and SDHC1_DIR_PMUX to 0
> (SDHC data direction function) - breaking card-detect and led gpios.
>
> This issue should affect any board based on LX2160 SoC that is using the
> same or earlier versions of NXP bootloader as SolidRun have tested, in
> particular: LSDK-21.08 and LS-5.15.71-2.2.0.
>
> Whether NXP added some extra initialisation in the bootloader on later
> releases was not investigated. However bootloader upgrade should not be
> necessary to run a newer Linux kernel.
>
> To work around this issue it is possible to explicitly define ALL pins
> controlled by any 32-bit value so that gradually after processing all
> pinctrl nodes the correct value is reached on all bits.
>
> This is a large task that should be done carefully on a per-board basis
> and not globally through the SoC dtsi.
> Therefore reverting the commit in question altogether was considered,
> but received pushback in review with the argument that bus recovery was
> important.
>
> Instead add pinmux nodes for all fields or rcwsr12 as used by affected
> SolidRun LX2160A Clearfog-CX & Honeycomb, and LX2162A Clearfog boards.
>
> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
> Cc: stable@vger.kernel.org
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> .../arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 7 +++++++
> .../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 ++
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++++++++++++++++++++++
> .../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 2 ++
> .../boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 7 +++++++
> 5 files changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
> index eec2cd6c6d32a..7f6e39e27ce5c 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
> @@ -162,6 +162,8 @@ rtc@51 {
> };
>
> &fspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
> status = "okay";
>
> flash@0 {
> @@ -177,6 +179,11 @@ flash@0 {
> };
> };
>
> +&pinmux_i2crv {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio0_14_12_pins>;
> +};
> +
> &usb0 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
> index af6258b2fe826..580ee9b3026e3 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
> @@ -89,6 +89,8 @@ &emdio2 {
> };
>
> &esdhc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
> sd-uhs-sdr104;
> sd-uhs-sdr50;
> sd-uhs-sdr25;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 853b01452813a..be0ccab5a626b 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -1721,6 +1721,10 @@ i2c1_scl_gpio: i2c1-scl-gpio-pins {
> pinctrl-single,bits = <0x0 0x1 0x7>;
> };
>
> + esdhc0_cd_wp_pins: iic2-sdhc-pins {
> + pinctrl-single,bits = <0x0 0x6 0x7>;
> + };
> +
> i2c2_scl: i2c2-scl-pins {
> pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
> };
> @@ -1753,6 +1757,26 @@ i2c5_scl_gpio: i2c5-scl-gpio-pins {
> pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
> };
>
> + fspi_data74_pins: xspi1-data74-pins {
> + pinctrl-single,bits = <0x0 0 (0x7 << 15)>;
> + };
Here I changed the naming scheme, to follow lx2160 reference manual bitfield names
closely, instead of device-tree bus names.
Should I rename the existing nodes, too, considering this change should go to stable?
I.e. "i2c1-scl-gpio-pins" -> "iic2-gpio-pins".
> +
> + fspi_data30_pins: xspi1-data30-pins {
> + pinctrl-single,bits = <0x0 0 (0x7 << 18)>;
I meant to replace "0" with "0x0" for consistency here ...
> + };
> +
> + fspi_dqs_sck_cs10_pins: xspi1-base-pins {
> + pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
> + };
> +
> + esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
> + pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
> + };
> +
> + gpio0_14_12_pins: sdhc1-dir-gpio-pins {
> + pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
> + };
> +
> i2c6_scl: i2c6-scl-pins {
> pinctrl-single,bits = <0x4 0x2 0x7>;
> };
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
> index eafef8718a0fe..8920326a06735 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
> @@ -223,6 +223,8 @@ ethernet_phy8: ethernet-phy@15 {
> };
>
> &esdhc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
> sd-uhs-sdr104;
> sd-uhs-sdr50;
> sd-uhs-sdr25;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
> index e914291e63a1a..e1344942eaaee 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
> @@ -30,6 +30,8 @@ &esdhc1 {
> };
>
> &fspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
> status = "okay";
>
> flash@0 {
> @@ -80,3 +82,8 @@ rtc@6f {
> reg = <0x6f>;
> };
> };
> +
> +&pinmux_i2crv {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio0_14_12_pins>;
> +};
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 2/5] arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word
2026-03-04 11:21 [PATCH v3 0/5] arm64: dts: lx2160a: fix pinmux issues, update solidrun boards Josua Mayer
2026-03-04 11:21 ` [PATCH v3 1/5] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux Josua Mayer
@ 2026-03-04 11:21 ` Josua Mayer
2026-03-04 11:38 ` Josua Mayer
2026-03-04 11:21 ` [PATCH v3 3/5] arm64: dts: fsl-lx2160a-cex7: add rtc alias Josua Mayer
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Josua Mayer @ 2026-03-04 11:21 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Frank Li, linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
support bus recovery") introduced pinmux nodes for lx2160 i2c
interfaces, allowing runtime change between i2c and gpio functions
implementing bus recovery.
Firstly this can cause unintended side-effects because the dynamic
configuration area where pinmux is modified at runtime reads zero
initially, causing application of the first pinmux node to clear any
other bits previously set during reset configuration.
It is possible for bootloaders to implement a workaround and copy from
the reset values from read-only area to dynamic configuration area,
however bootloader updates should not be required for kernel updates.
Alternatively pinmux in device-tree can be made complete, to cover all
bits of a 32-bit register, not just i2c & gpio functions, e.g. for
RCWSR12 register:
LX2162-CF RCWSR12: 0b0000100000000000 0000000000000110
IIC2_PMUX ||| ||| || | ||| |||XXX : I2C/GPIO/CD-WP
IIC3_PMUX ||| ||| || | ||| XXX : I2C/GPIO/CAN/EVT
IIC4_PMUX ||| ||| || | |||XXX||| : I2C/GPIO/CAN/EVT
IIC5_PMUX ||| ||| || | XXX ||| : I2C/GPIO/SDHC-CLK
IIC6_PMUX ||| ||| || |XXX||| ||| : I2C/GPIO/SDHC-CLK
XSPI1_A_DATA74_PMUX ||| ||| XX X ||| ||| : XSPI/GPIO
XSPI1_A_DATA30_PMUX ||| |||XXX|| | ||| ||| : XSPI/GPIO
XSPI1_A_BASE_PMUX ||| XXX || | ||| ||| : XSPI/GPIO
SDHC1_BASE_PMUX |||XXX||| || | ||| ||| : SDHC/GPIO/SPI
SDHC1_DIR_PMUX XXX ||| || | ||| ||| : SDHC/GPIO/SPI
RESERVED XX||| ||| || | ||| ||| :
Secondly the i2c bus recovery descriptions use explicit "_scl" suffix,
suggesting that only scl pin is configured.
However the pinmux in LX2160 always configures i2c pins in pairs, i.e.
both sda and scl are both switched between i2c and gpio functions. Yet
sda-gpios was not set.
Thirdly i2c6 and i2c7 pinmux nodes are identical, setting the same bits
because both pairs of pins are configured together in lx2160.
Describing them in duplicate nodes is confusing and hides the fact that
changing the mux for one, changes the other too.
Add description for all bits of RCWSR12 register, including i2c, gpio,
flextimer, spi, can and sdhc.
Rename the existing i2c pinmux nodes to be consistent with the newly
added alternate function nodes, and set sda-gpios on each i2c
controller.
Merge the i2c6 and i2c7 into a single node.
Other configuration words, i.e. RCWSR13 & RCWSR14 may be added in the
future for boards setting non-zero values there.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 153 ++++++++++++++++++-------
1 file changed, 114 insertions(+), 39 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index be0ccab5a626b..920198694e2fb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -750,9 +750,10 @@ i2c0: i2c@2000000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c0_scl>;
- pinctrl-1 = <&i2c0_scl_gpio>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-1 = <&gpio0_3_2_pins>;
scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -766,9 +767,10 @@ i2c1: i2c@2010000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c1_scl>;
- pinctrl-1 = <&i2c1_scl_gpio>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-1 = <&gpio0_31_30_pins>;
scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -782,9 +784,10 @@ i2c2: i2c@2020000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c2_scl>;
- pinctrl-1 = <&i2c2_scl_gpio>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&gpio0_29_28_pins>;
scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -798,9 +801,10 @@ i2c3: i2c@2030000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c3_scl>;
- pinctrl-1 = <&i2c3_scl_gpio>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-1 = <&gpio0_27_26_pins>;
scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -814,9 +818,10 @@ i2c4: i2c@2040000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c4_scl>;
- pinctrl-1 = <&i2c4_scl_gpio>;
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&gpio0_25_24_pins>;
scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -830,9 +835,10 @@ i2c5: i2c@2050000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c5_scl>;
- pinctrl-1 = <&i2c5_scl_gpio>;
+ pinctrl-0 = <&i2c5_pins>;
+ pinctrl-1 = <&gpio0_23_22_pins>;
scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -846,9 +852,10 @@ i2c6: i2c@2060000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c6_scl>;
- pinctrl-1 = <&i2c6_scl_gpio>;
+ pinctrl-0 = <&i2c6_i2c7_pins>;
+ pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -862,9 +869,10 @@ i2c7: i2c@2070000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c7_scl>;
- pinctrl-1 = <&i2c7_scl_gpio>;
+ pinctrl-0 = <&i2c6_i2c7_pins>;
+ pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -1713,92 +1721,159 @@ pinmux_i2crv: pinmux@70010012c {
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
- i2c1_scl: i2c1-scl-pins {
- pinctrl-single,bits = <0x0 0 0x7>;
+ /* RCWSR12 */
+ i2c1_pins: iic2-i2c-pins {
+ pinctrl-single,bits = <0x0 0x0 0x7>;
};
- i2c1_scl_gpio: i2c1-scl-gpio-pins {
+ gpio0_31_30_pins: iic2-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
+ ftm0_ch10_pins: iic2-ftm-pins {
+ pinctrl-single,bits = <0x0 0x2 0x7>;
+ };
+
esdhc0_cd_wp_pins: iic2-sdhc-pins {
pinctrl-single,bits = <0x0 0x6 0x7>;
};
- i2c2_scl: i2c2-scl-pins {
+ i2c2_pins: iic3-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
};
- i2c2_scl_gpio: i2c2-scl-gpio-pins {
+ gpio0_29_28_pins: iic3-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
};
- i2c3_scl: i2c3-scl-pins {
+ can0_pins: iic3-can-pins {
+ pinctrl-single,bits = <0x0 (0x2 << 3) (0x7 << 3)>;
+ };
+
+ event65_pins: iic3-event-pins {
+ pinctrl-single,bits = <0x0 (0x6 << 3) (0x7 << 3)>;
+ };
+
+ i2c3_pins: iic4-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
};
- i2c3_scl_gpio: i2c3-scl-gpio-pins {
+ gpio0_27_26_pins: iic4-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
};
- i2c4_scl: i2c4-scl-pins {
+ can1_pins: iic4-can-pins {
+ pinctrl-single,bits = <0x0 (0x2 << 6) (0x7 << 6)>;
+ };
+
+ event87_pins: iic4-event-pins {
+ pinctrl-single,bits = <0x0 (0x6 << 6) (0x7 << 6)>;
+ };
+
+ i2c4_pins: iic5-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
};
- i2c4_scl_gpio: i2c4-scl-gpio-pins {
+ gpio0_25_24_pins: iic5-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
};
- i2c5_scl: i2c5-scl-pins {
+ esdhc0_clksync_pins: iic5-sdhc-clk-pins {
+ pinctrl-single,bits = <0x0 (0x2 << 9) (0x7 << 9)>;
+ };
+
+ dspi2_miso_mosi_pins: iic5-spi3-pins {
+ pinctrl-single,bits = <0x3 (0x2 << 9) (0x7 << 9)>;
+ };
+
+ i2c5_pins: iic6-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
};
- i2c5_scl_gpio: i2c5-scl-gpio-pins {
+ gpio0_23_22_pins: iic6-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
+ esdhc1_clksync_pins: iic6-sdhc-clk-pins {
+ pinctrl-single,bits = <0x0 (0x2 << 12) (0x7 << 12)>;
+ };
+
fspi_data74_pins: xspi1-data74-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 15)>;
};
+ gpio1_31_28_pins: xspi1-data74-gpio-pins {
+ pinctrl-single,bits = <0x0 0x1 (0x7 << 15)>;
+ };
+
fspi_data30_pins: xspi1-data30-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 18)>;
};
+ gpio1_27_24_pins: xspi1-data30-gpio-pins {
+ pinctrl-single,bits = <0x0 0x1 (0x7 << 18)>;
+ };
+
fspi_dqs_sck_cs10_pins: xspi1-base-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
};
+ gpio1_23_20_pins: xspi1-base-gpio-pins {
+ pinctrl-single,bits = <0x0 0x1 (0x7 << 21)>;
+ };
+
esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
};
+ gpio0_21_15_pins: sdhc1-base-gpio-pins {
+ pinctrl-single,bits = <0x0 (0x1 << 24) (0x7 << 24)>;
+ };
+
+ dspi0_pins: sdhc1-base-spi1-pins {
+ pinctrl-single,bits = <0x0 (0x2 << 24) (0x7 << 24)>;
+ };
+
+ esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins {
+ pinctrl-single,bits = <0x0 (0x3 << 24) (0x7 << 24)>;
+ };
+
+ esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins {
+ pinctrl-single,bits = <0x0 (0x4 << 24) (0x7 << 24)>;
+ };
+
+ esdhc0_dir_pins: sdhc1-dir-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 27)>;
+ };
+
gpio0_14_12_pins: sdhc1-dir-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
};
- i2c6_scl: i2c6-scl-pins {
- pinctrl-single,bits = <0x4 0x2 0x7>;
+ dspi2_cs31_pins: sdhc1-dir-spi3-pins {
+ pinctrl-single,bits = <0x0 (0x3 << 27) (0x7 << 27)>;
};
- i2c6_scl_gpio: i2c6-scl-gpio-pins {
- pinctrl-single,bits = <0x4 0x1 0x7>;
+ esdhc0_data75_pins: sdhc1-dir-sdhc-pins {
+ pinctrl-single,bits = <0x0 (0x4 << 27) (0x7 << 27)>;
};
- i2c7_scl: i2c7-scl-pins {
- pinctrl-single,bits = <0x4 0x2 0x7>;
+ /* RCWSR13 */
+ gpio1_18_15_pins: iic8-iic7-gpio-pins {
+ pinctrl-single,bits = <0x4 0x1 0x7>;
};
- i2c7_scl_gpio: i2c7-scl-gpio-pins {
- pinctrl-single,bits = <0x4 0x1 0x7>;
+ i2c6_i2c7_pins: iic8-iic7-i2c-pins {
+ pinctrl-single,bits = <0x4 0x2 0x7>;
};
- i2c0_scl: i2c0-scl-pins {
- pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
+ /* RCWSR14 */
+ i2c0_pins: iic1-i2c-pins {
+ pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
};
- i2c0_scl_gpio: i2c0-scl-gpio-pins {
- pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
+ gpio0_3_2_pins: iic1-gpio-pins {
+ pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>;
};
};
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 2/5] arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word
2026-03-04 11:21 ` [PATCH v3 2/5] arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word Josua Mayer
@ 2026-03-04 11:38 ` Josua Mayer
0 siblings, 0 replies; 9+ messages in thread
From: Josua Mayer @ 2026-03-04 11:38 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Am 04.03.26 um 12:21 schrieb Josua Mayer:
> Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
> support bus recovery") introduced pinmux nodes for lx2160 i2c
> interfaces, allowing runtime change between i2c and gpio functions
> implementing bus recovery.
>
> Firstly this can cause unintended side-effects because the dynamic
> configuration area where pinmux is modified at runtime reads zero
> initially, causing application of the first pinmux node to clear any
> other bits previously set during reset configuration.
>
> It is possible for bootloaders to implement a workaround and copy from
> the reset values from read-only area to dynamic configuration area,
> however bootloader updates should not be required for kernel updates.
>
> Alternatively pinmux in device-tree can be made complete, to cover all
> bits of a 32-bit register, not just i2c & gpio functions, e.g. for
> RCWSR12 register:
>
> LX2162-CF RCWSR12: 0b0000100000000000 0000000000000110
> IIC2_PMUX ||| ||| || | ||| |||XXX : I2C/GPIO/CD-WP
> IIC3_PMUX ||| ||| || | ||| XXX : I2C/GPIO/CAN/EVT
> IIC4_PMUX ||| ||| || | |||XXX||| : I2C/GPIO/CAN/EVT
> IIC5_PMUX ||| ||| || | XXX ||| : I2C/GPIO/SDHC-CLK
> IIC6_PMUX ||| ||| || |XXX||| ||| : I2C/GPIO/SDHC-CLK
> XSPI1_A_DATA74_PMUX ||| ||| XX X ||| ||| : XSPI/GPIO
> XSPI1_A_DATA30_PMUX ||| |||XXX|| | ||| ||| : XSPI/GPIO
> XSPI1_A_BASE_PMUX ||| XXX || | ||| ||| : XSPI/GPIO
> SDHC1_BASE_PMUX |||XXX||| || | ||| ||| : SDHC/GPIO/SPI
> SDHC1_DIR_PMUX XXX ||| || | ||| ||| : SDHC/GPIO/SPI
> RESERVED XX||| ||| || | ||| ||| :
>
> Secondly the i2c bus recovery descriptions use explicit "_scl" suffix,
> suggesting that only scl pin is configured.
>
> However the pinmux in LX2160 always configures i2c pins in pairs, i.e.
> both sda and scl are both switched between i2c and gpio functions. Yet
> sda-gpios was not set.
>
> Thirdly i2c6 and i2c7 pinmux nodes are identical, setting the same bits
> because both pairs of pins are configured together in lx2160.
>
> Describing them in duplicate nodes is confusing and hides the fact that
> changing the mux for one, changes the other too.
>
> Add description for all bits of RCWSR12 register, including i2c, gpio,
> flextimer, spi, can and sdhc.
>
> Rename the existing i2c pinmux nodes to be consistent with the newly
> added alternate function nodes, and set sda-gpios on each i2c
> controller.
>
> Merge the i2c6 and i2c7 into a single node.
I realized that adding new nodes and renaming together makes the diff
quite unreadable.
So I will split this up into two changes for next version.
>
> Other configuration words, i.e. RCWSR13 & RCWSR14 may be added in the
> future for boards setting non-zero values there.
>
> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 153 ++++++++++++++++++-------
> 1 file changed, 114 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index be0ccab5a626b..920198694e2fb 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -750,9 +750,10 @@ i2c0: i2c@2000000 {
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&i2c0_scl>;
> - pinctrl-1 = <&i2c0_scl_gpio>;
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&gpio0_3_2_pins>;
> scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -766,9 +767,10 @@ i2c1: i2c@2010000 {
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&i2c1_scl>;
> - pinctrl-1 = <&i2c1_scl_gpio>;
> + pinctrl-0 = <&i2c1_pins>;
> + pinctrl-1 = <&gpio0_31_30_pins>;
> scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -782,9 +784,10 @@ i2c2: i2c@2020000 {
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&i2c2_scl>;
> - pinctrl-1 = <&i2c2_scl_gpio>;
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&gpio0_29_28_pins>;
> scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -798,9 +801,10 @@ i2c3: i2c@2030000 {
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&i2c3_scl>;
> - pinctrl-1 = <&i2c3_scl_gpio>;
> + pinctrl-0 = <&i2c3_pins>;
> + pinctrl-1 = <&gpio0_27_26_pins>;
> scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -814,9 +818,10 @@ i2c4: i2c@2040000 {
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&i2c4_scl>;
> - pinctrl-1 = <&i2c4_scl_gpio>;
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&gpio0_25_24_pins>;
> scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -830,9 +835,10 @@ i2c5: i2c@2050000 {
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&i2c5_scl>;
> - pinctrl-1 = <&i2c5_scl_gpio>;
> + pinctrl-0 = <&i2c5_pins>;
> + pinctrl-1 = <&gpio0_23_22_pins>;
> scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -846,9 +852,10 @@ i2c6: i2c@2060000 {
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&i2c6_scl>;
> - pinctrl-1 = <&i2c6_scl_gpio>;
> + pinctrl-0 = <&i2c6_i2c7_pins>;
> + pinctrl-1 = <&gpio1_18_15_pins>;
> scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -862,9 +869,10 @@ i2c7: i2c@2070000 {
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&i2c7_scl>;
> - pinctrl-1 = <&i2c7_scl_gpio>;
> + pinctrl-0 = <&i2c6_i2c7_pins>;
> + pinctrl-1 = <&gpio1_18_15_pins>;
> scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> status = "disabled";
> };
>
> @@ -1713,92 +1721,159 @@ pinmux_i2crv: pinmux@70010012c {
> pinctrl-single,register-width = <32>;
> pinctrl-single,function-mask = <0x7>;
>
> - i2c1_scl: i2c1-scl-pins {
> - pinctrl-single,bits = <0x0 0 0x7>;
> + /* RCWSR12 */
> + i2c1_pins: iic2-i2c-pins {
> + pinctrl-single,bits = <0x0 0x0 0x7>;
> };
>
> - i2c1_scl_gpio: i2c1-scl-gpio-pins {
> + gpio0_31_30_pins: iic2-gpio-pins {
> pinctrl-single,bits = <0x0 0x1 0x7>;
> };
>
> + ftm0_ch10_pins: iic2-ftm-pins {
> + pinctrl-single,bits = <0x0 0x2 0x7>;
> + };
> +
> esdhc0_cd_wp_pins: iic2-sdhc-pins {
> pinctrl-single,bits = <0x0 0x6 0x7>;
> };
>
> - i2c2_scl: i2c2-scl-pins {
> + i2c2_pins: iic3-i2c-pins {
> pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
> };
>
> - i2c2_scl_gpio: i2c2-scl-gpio-pins {
> + gpio0_29_28_pins: iic3-gpio-pins {
> pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
> };
>
> - i2c3_scl: i2c3-scl-pins {
> + can0_pins: iic3-can-pins {
> + pinctrl-single,bits = <0x0 (0x2 << 3) (0x7 << 3)>;
> + };
> +
> + event65_pins: iic3-event-pins {
> + pinctrl-single,bits = <0x0 (0x6 << 3) (0x7 << 3)>;
> + };
> +
> + i2c3_pins: iic4-i2c-pins {
> pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
> };
>
> - i2c3_scl_gpio: i2c3-scl-gpio-pins {
> + gpio0_27_26_pins: iic4-gpio-pins {
> pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
> };
>
> - i2c4_scl: i2c4-scl-pins {
> + can1_pins: iic4-can-pins {
> + pinctrl-single,bits = <0x0 (0x2 << 6) (0x7 << 6)>;
> + };
> +
> + event87_pins: iic4-event-pins {
> + pinctrl-single,bits = <0x0 (0x6 << 6) (0x7 << 6)>;
> + };
> +
> + i2c4_pins: iic5-i2c-pins {
> pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
> };
>
> - i2c4_scl_gpio: i2c4-scl-gpio-pins {
> + gpio0_25_24_pins: iic5-gpio-pins {
> pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
> };
>
> - i2c5_scl: i2c5-scl-pins {
> + esdhc0_clksync_pins: iic5-sdhc-clk-pins {
> + pinctrl-single,bits = <0x0 (0x2 << 9) (0x7 << 9)>;
> + };
> +
> + dspi2_miso_mosi_pins: iic5-spi3-pins {
> + pinctrl-single,bits = <0x3 (0x2 << 9) (0x7 << 9)>;
> + };
> +
> + i2c5_pins: iic6-i2c-pins {
> pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
> };
>
> - i2c5_scl_gpio: i2c5-scl-gpio-pins {
> + gpio0_23_22_pins: iic6-gpio-pins {
> pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
> };
>
> + esdhc1_clksync_pins: iic6-sdhc-clk-pins {
> + pinctrl-single,bits = <0x0 (0x2 << 12) (0x7 << 12)>;
> + };
> +
> fspi_data74_pins: xspi1-data74-pins {
> pinctrl-single,bits = <0x0 0 (0x7 << 15)>;
> };
>
> + gpio1_31_28_pins: xspi1-data74-gpio-pins {
> + pinctrl-single,bits = <0x0 0x1 (0x7 << 15)>;
> + };
> +
> fspi_data30_pins: xspi1-data30-pins {
> pinctrl-single,bits = <0x0 0 (0x7 << 18)>;
> };
>
> + gpio1_27_24_pins: xspi1-data30-gpio-pins {
> + pinctrl-single,bits = <0x0 0x1 (0x7 << 18)>;
> + };
> +
> fspi_dqs_sck_cs10_pins: xspi1-base-pins {
> pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
> };
>
> + gpio1_23_20_pins: xspi1-base-gpio-pins {
> + pinctrl-single,bits = <0x0 0x1 (0x7 << 21)>;
> + };
> +
> esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
> pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
> };
>
> + gpio0_21_15_pins: sdhc1-base-gpio-pins {
> + pinctrl-single,bits = <0x0 (0x1 << 24) (0x7 << 24)>;
> + };
> +
> + dspi0_pins: sdhc1-base-spi1-pins {
> + pinctrl-single,bits = <0x0 (0x2 << 24) (0x7 << 24)>;
> + };
> +
> + esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins {
> + pinctrl-single,bits = <0x0 (0x3 << 24) (0x7 << 24)>;
> + };
> +
> + esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins {
> + pinctrl-single,bits = <0x0 (0x4 << 24) (0x7 << 24)>;
> + };
> +
> + esdhc0_dir_pins: sdhc1-dir-pins {
> + pinctrl-single,bits = <0x0 0x0 (0x7 << 27)>;
> + };
> +
> gpio0_14_12_pins: sdhc1-dir-gpio-pins {
> pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
> };
>
> - i2c6_scl: i2c6-scl-pins {
> - pinctrl-single,bits = <0x4 0x2 0x7>;
> + dspi2_cs31_pins: sdhc1-dir-spi3-pins {
> + pinctrl-single,bits = <0x0 (0x3 << 27) (0x7 << 27)>;
> };
>
> - i2c6_scl_gpio: i2c6-scl-gpio-pins {
> - pinctrl-single,bits = <0x4 0x1 0x7>;
> + esdhc0_data75_pins: sdhc1-dir-sdhc-pins {
> + pinctrl-single,bits = <0x0 (0x4 << 27) (0x7 << 27)>;
> };
>
> - i2c7_scl: i2c7-scl-pins {
> - pinctrl-single,bits = <0x4 0x2 0x7>;
> + /* RCWSR13 */
> + gpio1_18_15_pins: iic8-iic7-gpio-pins {
> + pinctrl-single,bits = <0x4 0x1 0x7>;
> };
>
> - i2c7_scl_gpio: i2c7-scl-gpio-pins {
> - pinctrl-single,bits = <0x4 0x1 0x7>;
> + i2c6_i2c7_pins: iic8-iic7-i2c-pins {
> + pinctrl-single,bits = <0x4 0x2 0x7>;
> };
>
> - i2c0_scl: i2c0-scl-pins {
> - pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
> + /* RCWSR14 */
> + i2c0_pins: iic1-i2c-pins {
> + pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
> };
>
> - i2c0_scl_gpio: i2c0-scl-gpio-pins {
> - pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
> + gpio0_3_2_pins: iic1-gpio-pins {
> + pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>;
> };
> };
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 3/5] arm64: dts: fsl-lx2160a-cex7: add rtc alias
2026-03-04 11:21 [PATCH v3 0/5] arm64: dts: lx2160a: fix pinmux issues, update solidrun boards Josua Mayer
2026-03-04 11:21 ` [PATCH v3 1/5] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux Josua Mayer
2026-03-04 11:21 ` [PATCH v3 2/5] arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word Josua Mayer
@ 2026-03-04 11:21 ` Josua Mayer
2026-03-04 11:21 ` [PATCH v3 4/5] arm64: dts: fsl-lx2162a-sr-som: add crypto & rtc aliases, model Josua Mayer
2026-03-04 11:21 ` [PATCH v3 5/5] arm64: dts: lx2162a-clearfog: set sfp connector leds function and source Josua Mayer
4 siblings, 0 replies; 9+ messages in thread
From: Josua Mayer @ 2026-03-04 11:21 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Frank Li, linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
Add aliase for rtc ensuring that on-com rtc is assigned first index.
Note that fsl-lx2160a.dtsi already defines an alias for rtc1 which
implicitly achieved the same result.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
index 7f6e39e27ce5c..90956ffb8ea9a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
@@ -14,6 +14,7 @@ / {
aliases {
crypto = &crypto;
+ rtc0 = &com_rtc;
};
sb_3v3: regulator-sb3v3 {
@@ -154,7 +155,7 @@ &i2c2 {
&i2c4 {
status = "okay";
- rtc@51 {
+ com_rtc: rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
interrupts-extended = <&gpio2 8 IRQ_TYPE_LEVEL_LOW>;
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 4/5] arm64: dts: fsl-lx2162a-sr-som: add crypto & rtc aliases, model
2026-03-04 11:21 [PATCH v3 0/5] arm64: dts: lx2160a: fix pinmux issues, update solidrun boards Josua Mayer
` (2 preceding siblings ...)
2026-03-04 11:21 ` [PATCH v3 3/5] arm64: dts: fsl-lx2160a-cex7: add rtc alias Josua Mayer
@ 2026-03-04 11:21 ` Josua Mayer
2026-03-04 11:21 ` [PATCH v3 5/5] arm64: dts: lx2162a-clearfog: set sfp connector leds function and source Josua Mayer
4 siblings, 0 replies; 9+ messages in thread
From: Josua Mayer @ 2026-03-04 11:21 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Frank Li, linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
Add aliases for crypto accelerator and rtc ensuring that on-com rtc and
the SoC A72 domain crypto accelerator are assigned first index.
Further set model and compatible strings which are informative but
overridden by actual boards.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
index e1344942eaaee..3ad908d52a18b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
@@ -5,6 +5,16 @@
// Copyright 2021 Rabeeh Khoury <rabeeh@solid-run.com>
// Copyright 2023 Josua Mayer <josua@solid-run.com>
+/ {
+ model = "SolidRun LX2162A System on Module";
+ compatible = "solidrun,lx2162a-som", "fsl,lx2160a";
+
+ aliases {
+ crypto = &crypto;
+ rtc0 = &som_rtc;
+ };
+};
+
&crypto {
status = "okay";
};
@@ -77,7 +87,7 @@ variable_eeprom: eeprom@54 {
&i2c5 {
status = "okay";
- rtc@6f {
+ som_rtc: rtc@6f {
compatible = "microchip,mcp7940x";
reg = <0x6f>;
};
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 5/5] arm64: dts: lx2162a-clearfog: set sfp connector leds function and source
2026-03-04 11:21 [PATCH v3 0/5] arm64: dts: lx2160a: fix pinmux issues, update solidrun boards Josua Mayer
` (3 preceding siblings ...)
2026-03-04 11:21 ` [PATCH v3 4/5] arm64: dts: fsl-lx2162a-sr-som: add crypto & rtc aliases, model Josua Mayer
@ 2026-03-04 11:21 ` Josua Mayer
2026-03-04 11:25 ` Josua Mayer
4 siblings, 1 reply; 9+ messages in thread
From: Josua Mayer @ 2026-03-04 11:21 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Frank Li, linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
LX2162A Clearfog has four LEDs attached physically to the 4-port SFP
connector. They are intended to show information relating to network
interface status.
Select "netdev" as default trigger for each LED, and link each one to
the respective dpmac instance as trigger-source.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index 8920326a06735..9d50d3e2761da 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -41,21 +41,29 @@ leds {
led_sfp_at: led-sfp-at {
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
default-state = "off";
+ linux,default-trigger = "netdev";
+ trigger-sources = <&dpmac3>;
};
led_sfp_ab: led-sfp-ab {
gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
default-state = "off";
+ linux,default-trigger = "netdev";
+ trigger-sources = <&dpmac4>;
};
led_sfp_bt: led-sfp-bt {
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
default-state = "off";
+ linux,default-trigger = "netdev";
+ trigger-sources = <&dpmac5>;
};
led_sfp_bb: led-sfp-bb {
gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
default-state = "off";
+ linux,default-trigger = "netdev";
+ trigger-sources = <&dpmac6>;
};
};
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 5/5] arm64: dts: lx2162a-clearfog: set sfp connector leds function and source
2026-03-04 11:21 ` [PATCH v3 5/5] arm64: dts: lx2162a-clearfog: set sfp connector leds function and source Josua Mayer
@ 2026-03-04 11:25 ` Josua Mayer
0 siblings, 0 replies; 9+ messages in thread
From: Josua Mayer @ 2026-03-04 11:25 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Am 04.03.26 um 12:21 schrieb Josua Mayer:
> LX2162A Clearfog has four LEDs attached physically to the 4-port SFP
> connector. They are intended to show information relating to network
> interface status.
>
> Select "netdev" as default trigger for each LED, and link each one to
> the respective dpmac instance as trigger-source.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
> index 8920326a06735..9d50d3e2761da 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
> @@ -41,21 +41,29 @@ leds {
> led_sfp_at: led-sfp-at {
> gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
> default-state = "off";
> + linux,default-trigger = "netdev";
> + trigger-sources = <&dpmac3>;
I wasn't sure about this one, due to how the dpaa2 driver is designed,
the parent to the linux netdev is a dpni object, not a dpmac object.
So I still need udev rules, and the trigger-source is not set automatically.
If this description is correct, then I still prefer to add it.
> };
>
> led_sfp_ab: led-sfp-ab {
> gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
> default-state = "off";
> + linux,default-trigger = "netdev";
> + trigger-sources = <&dpmac4>;
> };
>
> led_sfp_bt: led-sfp-bt {
> gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
> default-state = "off";
> + linux,default-trigger = "netdev";
> + trigger-sources = <&dpmac5>;
> };
>
> led_sfp_bb: led-sfp-bb {
> gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
> default-state = "off";
> + linux,default-trigger = "netdev";
> + trigger-sources = <&dpmac6>;
> };
> };
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread