* [PATCH v4 1/6] mmc: sdhci-cadence: Rename functions/structures to SD4 specific
2023-07-17 12:51 [PATCH v4 0/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
@ 2023-07-17 12:51 ` Piyush Malgujar
2023-07-26 12:41 ` Adrian Hunter
2023-07-17 12:51 ` [PATCH v4 2/6] mmc: sdhci-cadence: Restructure the code Piyush Malgujar
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Piyush Malgujar @ 2023-07-17 12:51 UTC (permalink / raw)
To: linux-mmc, linux-kernel, adrian.hunter, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva, Dhananjay Kangude, Piyush Malgujar
From: Dhananjay Kangude <dkangude@cadence.com>
Renaming the functions and structures specific to SD4 so
that it can be separated from upcoming SD6 related
functionality.
Signed-off-by: Dhananjay Kangude <dkangude@cadence.com>
Co-developed-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
---
drivers/mmc/host/sdhci-cadence.c | 92 ++++++++++++++++----------------
1 file changed, 46 insertions(+), 46 deletions(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index d2f62505468932b069e3411f2a4b7418ffece517..9bb38281bcb244b0be91ef579046c40de7a06e1f 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -16,14 +16,14 @@
#include "sdhci-pltfm.h"
-/* HRS - Host Register Set (specific to Cadence) */
-#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
-#define SDHCI_CDNS_HRS04_ACK BIT(26)
-#define SDHCI_CDNS_HRS04_RD BIT(25)
-#define SDHCI_CDNS_HRS04_WR BIT(24)
-#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
-#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
-#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
+/* SD 4.0 Controller HRS - Host Register Set (specific to Cadence) */
+#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
+#define SDHCI_CDNS_SD4_HRS04_ACK BIT(26)
+#define SDHCI_CDNS_SD4_HRS04_RD BIT(25)
+#define SDHCI_CDNS_SD4_HRS04_WR BIT(24)
+#define SDHCI_CDNS_SD4_HRS04_RDATA GENMASK(23, 16)
+#define SDHCI_CDNS_SD4_HRS04_WDATA GENMASK(15, 8)
+#define SDHCI_CDNS_SD4_HRS04_ADDR GENMASK(5, 0)
#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
@@ -39,7 +39,7 @@
/* SRS - Slot Register Set (SDHCI-compatible) */
#define SDHCI_CDNS_SRS_BASE 0x200
-/* PHY */
+/* PHY registers for SD4 controller */
#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
@@ -60,7 +60,7 @@
*/
#define SDHCI_CDNS_MAX_TUNING_LOOP 40
-struct sdhci_cdns_phy_param {
+struct sdhci_cdns_sd4_phy_param {
u8 addr;
u8 data;
};
@@ -73,10 +73,10 @@ struct sdhci_cdns_priv {
void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
struct reset_control *rst_hw;
unsigned int nr_phy_params;
- struct sdhci_cdns_phy_param phy_params[];
+ struct sdhci_cdns_sd4_phy_param phy_params[];
};
-struct sdhci_cdns_phy_cfg {
+struct sdhci_cdns_sd4_phy_cfg {
const char *property;
u8 addr;
};
@@ -86,7 +86,7 @@ struct sdhci_cdns_drv_data {
const struct sdhci_pltfm_data pltfm_data;
};
-static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
+static const struct sdhci_cdns_sd4_phy_cfg sdhci_cdns_sd4_phy_cfgs[] = {
{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
@@ -106,76 +106,76 @@ static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
writel(val, reg);
}
-static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
- u8 addr, u8 data)
+static int sdhci_cdns_sd4_write_phy_reg(struct sdhci_cdns_priv *priv,
+ u8 addr, u8 data)
{
void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
u32 tmp;
int ret;
- ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
+ ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_SD4_HRS04_ACK),
0, 10);
if (ret)
return ret;
- tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
- FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
+ tmp = FIELD_PREP(SDHCI_CDNS_SD4_HRS04_WDATA, data) |
+ FIELD_PREP(SDHCI_CDNS_SD4_HRS04_ADDR, addr);
priv->priv_writel(priv, tmp, reg);
- tmp |= SDHCI_CDNS_HRS04_WR;
+ tmp |= SDHCI_CDNS_SD4_HRS04_WR;
priv->priv_writel(priv, tmp, reg);
- ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
+ ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_SD4_HRS04_ACK, 0, 10);
if (ret)
return ret;
- tmp &= ~SDHCI_CDNS_HRS04_WR;
+ tmp &= ~SDHCI_CDNS_SD4_HRS04_WR;
priv->priv_writel(priv, tmp, reg);
- ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
+ ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_SD4_HRS04_ACK),
0, 10);
return ret;
}
-static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)
+static unsigned int sdhci_cdns_sd4_phy_param_count(struct device_node *np)
{
unsigned int count = 0;
int i;
- for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++)
- if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property))
+ for (i = 0; i < ARRAY_SIZE(sdhci_cdns_sd4_phy_cfgs); i++)
+ if (of_property_read_bool(np, sdhci_cdns_sd4_phy_cfgs[i].property))
count++;
return count;
}
-static void sdhci_cdns_phy_param_parse(struct device_node *np,
- struct sdhci_cdns_priv *priv)
+static void sdhci_cdns_sd4_phy_param_parse(struct device_node *np,
+ struct sdhci_cdns_priv *priv)
{
- struct sdhci_cdns_phy_param *p = priv->phy_params;
+ struct sdhci_cdns_sd4_phy_param *p = priv->phy_params;
u32 val;
int ret, i;
- for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
- ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
+ for (i = 0; i < ARRAY_SIZE(sdhci_cdns_sd4_phy_cfgs); i++) {
+ ret = of_property_read_u32(np, sdhci_cdns_sd4_phy_cfgs[i].property,
&val);
if (ret)
continue;
- p->addr = sdhci_cdns_phy_cfgs[i].addr;
+ p->addr = sdhci_cdns_sd4_phy_cfgs[i].addr;
p->data = val;
p++;
}
}
-static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
+static int sdhci_cdns_sd4_phy_init(struct sdhci_cdns_priv *priv)
{
int ret, i;
for (i = 0; i < priv->nr_phy_params; i++) {
- ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,
- priv->phy_params[i].data);
+ ret = sdhci_cdns_sd4_write_phy_reg(priv, priv->phy_params[i].addr,
+ priv->phy_params[i].data);
if (ret)
return ret;
}
@@ -218,7 +218,7 @@ static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
}
-static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
+static int sdhci_cdns_sd4_set_tune_val(struct sdhci_host *host, unsigned int val)
{
struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
@@ -271,7 +271,7 @@ static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode)
return 0;
for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
- if (sdhci_cdns_set_tune_val(host, i) ||
+ if (sdhci_cdns_sd4_set_tune_val(host, i) ||
mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
cur_streak = 0;
} else { /* good */
@@ -288,7 +288,7 @@ static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode)
return -EIO;
}
- return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
+ return sdhci_cdns_sd4_set_tune_val(host, end_of_streak - max_streak / 2);
}
static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
@@ -410,7 +410,7 @@ static int elba_drv_init(struct platform_device *pdev)
return 0;
}
-static const struct sdhci_ops sdhci_cdns_ops = {
+static const struct sdhci_ops sdhci_cdns_sd4_ops = {
.set_clock = sdhci_set_clock,
.get_timeout_clock = sdhci_cdns_get_timeout_clock,
.set_bus_width = sdhci_set_bus_width,
@@ -421,7 +421,7 @@ static const struct sdhci_ops sdhci_cdns_ops = {
static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
.pltfm_data = {
- .ops = &sdhci_cdns_ops,
+ .ops = &sdhci_cdns_sd4_ops,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
},
};
@@ -433,9 +433,9 @@ static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = {
},
};
-static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = {
+static const struct sdhci_cdns_drv_data sdhci_cdns_sd4_drv_data = {
.pltfm_data = {
- .ops = &sdhci_cdns_ops,
+ .ops = &sdhci_cdns_sd4_ops,
},
};
@@ -497,9 +497,9 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
data = of_device_get_match_data(dev);
if (!data)
- data = &sdhci_cdns_drv_data;
+ data = &sdhci_cdns_sd4_drv_data;
- nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
+ nr_phy_params = sdhci_cdns_sd4_phy_param_count(dev->of_node);
host = sdhci_pltfm_init(pdev, &data->pltfm_data,
struct_size(priv, phy_params, nr_phy_params));
if (IS_ERR(host)) {
@@ -532,9 +532,9 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
if (ret)
goto free;
- sdhci_cdns_phy_param_parse(dev->of_node, priv);
+ sdhci_cdns_sd4_phy_param_parse(dev->of_node, priv);
- ret = sdhci_cdns_phy_init(priv);
+ ret = sdhci_cdns_sd4_phy_init(priv);
if (ret)
goto free;
@@ -574,7 +574,7 @@ static int sdhci_cdns_resume(struct device *dev)
if (ret)
return ret;
- ret = sdhci_cdns_phy_init(priv);
+ ret = sdhci_cdns_sd4_phy_init(priv);
if (ret)
goto disable_clk;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v4 1/6] mmc: sdhci-cadence: Rename functions/structures to SD4 specific
2023-07-17 12:51 ` [PATCH v4 1/6] mmc: sdhci-cadence: Rename functions/structures to SD4 specific Piyush Malgujar
@ 2023-07-26 12:41 ` Adrian Hunter
0 siblings, 0 replies; 16+ messages in thread
From: Adrian Hunter @ 2023-07-26 12:41 UTC (permalink / raw)
To: Piyush Malgujar, linux-mmc, linux-kernel, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva, Dhananjay Kangude
On 17/07/23 15:51, Piyush Malgujar wrote:
> From: Dhananjay Kangude <dkangude@cadence.com>
>
> Renaming the functions and structures specific to SD4 so
> that it can be separated from upcoming SD6 related
> functionality.
>
> Signed-off-by: Dhananjay Kangude <dkangude@cadence.com>
> Co-developed-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> ---
> drivers/mmc/host/sdhci-cadence.c | 92 ++++++++++++++++----------------
> 1 file changed, 46 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index d2f62505468932b069e3411f2a4b7418ffece517..9bb38281bcb244b0be91ef579046c40de7a06e1f 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -16,14 +16,14 @@
>
> #include "sdhci-pltfm.h"
>
> -/* HRS - Host Register Set (specific to Cadence) */
> -#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
> -#define SDHCI_CDNS_HRS04_ACK BIT(26)> -#define SDHCI_CDNS_HRS04_RD BIT(25)
> -#define SDHCI_CDNS_HRS04_WR BIT(24)
> -#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
> -#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
> -#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
> +/* SD 4.0 Controller HRS - Host Register Set (specific to Cadence) */ where
> +#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
> +#define SDHCI_CDNS_SD4_HRS04_ACK BIT(26)
> +#define SDHCI_CDNS_SD4_HRS04_RD BIT(25)
> +#define SDHCI_CDNS_SD4_HRS04_WR BIT(24)
> +#define SDHCI_CDNS_SD4_HRS04_RDATA GENMASK(23, 16)
> +#define SDHCI_CDNS_SD4_HRS04_WDATA GENMASK(15, 8)
> +#define SDHCI_CDNS_SD4_HRS04_ADDR GENMASK(5, 0)
You have changed the style whereby the register and the fields
had different indentations (compare SDHCI_CDNS_HRS04 and
SDHCI_CDNS_HRS04_ACK). The style doesn't matter much but it
would be nicer not to end up with a mix of styles.
It is also a bit surprising not to continue using the register
name as the prefix for the field name
e.g. why SDHCI_CDNS_SD4_HRS04_ACK instead of SDHCI_CDNS_HRS04_SD4_ACK
>
> #define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
> #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
> @@ -39,7 +39,7 @@
> /* SRS - Slot Register Set (SDHCI-compatible) */
> #define SDHCI_CDNS_SRS_BASE 0x200
>
> -/* PHY */
> +/* PHY registers for SD4 controller */
> #define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
> #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
> #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
> @@ -60,7 +60,7 @@
> */
> #define SDHCI_CDNS_MAX_TUNING_LOOP 40
>
> -struct sdhci_cdns_phy_param {
> +struct sdhci_cdns_sd4_phy_param {
> u8 addr;
> u8 data;
> };
> @@ -73,10 +73,10 @@ struct sdhci_cdns_priv {
> void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
> struct reset_control *rst_hw;
> unsigned int nr_phy_params;
> - struct sdhci_cdns_phy_param phy_params[];
> + struct sdhci_cdns_sd4_phy_param phy_params[];
> };
>
> -struct sdhci_cdns_phy_cfg {
> +struct sdhci_cdns_sd4_phy_cfg {
> const char *property;
> u8 addr;
> };
> @@ -86,7 +86,7 @@ struct sdhci_cdns_drv_data {
> const struct sdhci_pltfm_data pltfm_data;
> };
>
> -static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
> +static const struct sdhci_cdns_sd4_phy_cfg sdhci_cdns_sd4_phy_cfgs[] = {
> { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
> { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
> { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
> @@ -106,76 +106,76 @@ static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
> writel(val, reg);
> }
>
> -static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
> - u8 addr, u8 data)
> +static int sdhci_cdns_sd4_write_phy_reg(struct sdhci_cdns_priv *priv,
> + u8 addr, u8 data)
> {
> void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
> u32 tmp;
> int ret;
>
> - ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
> + ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_SD4_HRS04_ACK),
> 0, 10);
> if (ret)
> return ret;
>
> - tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
> - FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
> + tmp = FIELD_PREP(SDHCI_CDNS_SD4_HRS04_WDATA, data) |
> + FIELD_PREP(SDHCI_CDNS_SD4_HRS04_ADDR, addr);
> priv->priv_writel(priv, tmp, reg);
>
> - tmp |= SDHCI_CDNS_HRS04_WR;
> + tmp |= SDHCI_CDNS_SD4_HRS04_WR;
> priv->priv_writel(priv, tmp, reg);
>
> - ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
> + ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_SD4_HRS04_ACK, 0, 10);
> if (ret)
> return ret;
>
> - tmp &= ~SDHCI_CDNS_HRS04_WR;
> + tmp &= ~SDHCI_CDNS_SD4_HRS04_WR;
> priv->priv_writel(priv, tmp, reg);
>
> - ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
> + ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_SD4_HRS04_ACK),
> 0, 10);
>
> return ret;
> }
>
> -static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)
> +static unsigned int sdhci_cdns_sd4_phy_param_count(struct device_node *np)
> {
> unsigned int count = 0;
> int i;
>
> - for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++)
> - if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property))
> + for (i = 0; i < ARRAY_SIZE(sdhci_cdns_sd4_phy_cfgs); i++)
> + if (of_property_read_bool(np, sdhci_cdns_sd4_phy_cfgs[i].property))
> count++;
>
> return count;
> }
>
> -static void sdhci_cdns_phy_param_parse(struct device_node *np,
> - struct sdhci_cdns_priv *priv)
> +static void sdhci_cdns_sd4_phy_param_parse(struct device_node *np,
> + struct sdhci_cdns_priv *priv)
> {
> - struct sdhci_cdns_phy_param *p = priv->phy_params;
> + struct sdhci_cdns_sd4_phy_param *p = priv->phy_params;
> u32 val;
> int ret, i;
>
> - for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
> - ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
> + for (i = 0; i < ARRAY_SIZE(sdhci_cdns_sd4_phy_cfgs); i++) {
> + ret = of_property_read_u32(np, sdhci_cdns_sd4_phy_cfgs[i].property,
> &val);
> if (ret)
> continue;
>
> - p->addr = sdhci_cdns_phy_cfgs[i].addr;
> + p->addr = sdhci_cdns_sd4_phy_cfgs[i].addr;
> p->data = val;
> p++;
> }
> }
>
> -static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
> +static int sdhci_cdns_sd4_phy_init(struct sdhci_cdns_priv *priv)
> {
> int ret, i;
>
> for (i = 0; i < priv->nr_phy_params; i++) {
> - ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,
> - priv->phy_params[i].data);
> + ret = sdhci_cdns_sd4_write_phy_reg(priv, priv->phy_params[i].addr,
> + priv->phy_params[i].data);
> if (ret)
> return ret;
> }
> @@ -218,7 +218,7 @@ static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
> return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
> }
>
> -static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
> +static int sdhci_cdns_sd4_set_tune_val(struct sdhci_host *host, unsigned int val)
> {
> struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
> @@ -271,7 +271,7 @@ static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode)
> return 0;
>
> for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
> - if (sdhci_cdns_set_tune_val(host, i) ||
> + if (sdhci_cdns_sd4_set_tune_val(host, i) ||
> mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
> cur_streak = 0;
> } else { /* good */
> @@ -288,7 +288,7 @@ static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode)
> return -EIO;
> }
>
> - return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
> + return sdhci_cdns_sd4_set_tune_val(host, end_of_streak - max_streak / 2);
> }
>
> static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
> @@ -410,7 +410,7 @@ static int elba_drv_init(struct platform_device *pdev)
> return 0;
> }
>
> -static const struct sdhci_ops sdhci_cdns_ops = {
> +static const struct sdhci_ops sdhci_cdns_sd4_ops = {
> .set_clock = sdhci_set_clock,
> .get_timeout_clock = sdhci_cdns_get_timeout_clock,
> .set_bus_width = sdhci_set_bus_width,
> @@ -421,7 +421,7 @@ static const struct sdhci_ops sdhci_cdns_ops = {
>
> static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
> .pltfm_data = {
> - .ops = &sdhci_cdns_ops,
> + .ops = &sdhci_cdns_sd4_ops,
> .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> },
> };
> @@ -433,9 +433,9 @@ static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = {
> },
> };
>
> -static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = {
> +static const struct sdhci_cdns_drv_data sdhci_cdns_sd4_drv_data = {
> .pltfm_data = {
> - .ops = &sdhci_cdns_ops,
> + .ops = &sdhci_cdns_sd4_ops,
> },
> };
>
> @@ -497,9 +497,9 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
>
> data = of_device_get_match_data(dev);
> if (!data)
> - data = &sdhci_cdns_drv_data;
> + data = &sdhci_cdns_sd4_drv_data;
>
> - nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
> + nr_phy_params = sdhci_cdns_sd4_phy_param_count(dev->of_node);
> host = sdhci_pltfm_init(pdev, &data->pltfm_data,
> struct_size(priv, phy_params, nr_phy_params));
> if (IS_ERR(host)) {
> @@ -532,9 +532,9 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> if (ret)
> goto free;
>
> - sdhci_cdns_phy_param_parse(dev->of_node, priv);
> + sdhci_cdns_sd4_phy_param_parse(dev->of_node, priv);
>
> - ret = sdhci_cdns_phy_init(priv);
> + ret = sdhci_cdns_sd4_phy_init(priv);
> if (ret)
> goto free;
>
> @@ -574,7 +574,7 @@ static int sdhci_cdns_resume(struct device *dev)
> if (ret)
> return ret;
>
> - ret = sdhci_cdns_phy_init(priv);
> + ret = sdhci_cdns_sd4_phy_init(priv);
> if (ret)
> goto disable_clk;
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 2/6] mmc: sdhci-cadence: Restructure the code
2023-07-17 12:51 [PATCH v4 0/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
2023-07-17 12:51 ` [PATCH v4 1/6] mmc: sdhci-cadence: Rename functions/structures to SD4 specific Piyush Malgujar
@ 2023-07-17 12:51 ` Piyush Malgujar
2023-07-26 12:41 ` Adrian Hunter
2023-07-17 12:51 ` [PATCH v4 3/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Piyush Malgujar @ 2023-07-17 12:51 UTC (permalink / raw)
To: linux-mmc, linux-kernel, adrian.hunter, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva, Dhananjay Kangude, Piyush Malgujar
From: Dhananjay Kangude <dkangude@cadence.com>
Restructured the code, added controller version specific init for
SD4 operations with no change to existing functionality.
Signed-off-by: Dhananjay Kangude <dkangude@cadence.com>
Co-developed-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
---
drivers/mmc/host/sdhci-cadence.c | 76 ++++++++++++++++++++++++--------
1 file changed, 58 insertions(+), 18 deletions(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 9bb38281bcb244b0be91ef579046c40de7a06e1f..98fe752bcf27a71607623f3cb1c36f1a16d688a4 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -60,11 +60,17 @@
*/
#define SDHCI_CDNS_MAX_TUNING_LOOP 40
+struct sdhci_cdns_priv;
+
struct sdhci_cdns_sd4_phy_param {
u8 addr;
u8 data;
};
+struct sdhci_cdns_sd4_phy {
+ unsigned int nr_phy_params;
+ struct sdhci_cdns_sd4_phy_param phy_params[];
+};
struct sdhci_cdns_priv {
void __iomem *hrs_addr;
void __iomem *ctl_addr; /* write control */
@@ -72,8 +78,8 @@ struct sdhci_cdns_priv {
bool enhanced_strobe;
void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
struct reset_control *rst_hw;
- unsigned int nr_phy_params;
- struct sdhci_cdns_sd4_phy_param phy_params[];
+ const struct sdhci_cdns_drv_data *cdns_data;
+ void *phy;
};
struct sdhci_cdns_sd4_phy_cfg {
@@ -83,6 +89,8 @@ struct sdhci_cdns_sd4_phy_cfg {
struct sdhci_cdns_drv_data {
int (*init)(struct platform_device *pdev);
+ int (*phy_init)(struct sdhci_cdns_priv *priv);
+ int (*phy_probe)(struct platform_device *pdev, struct sdhci_cdns_priv *priv);
const struct sdhci_pltfm_data pltfm_data;
};
@@ -151,9 +159,9 @@ static unsigned int sdhci_cdns_sd4_phy_param_count(struct device_node *np)
}
static void sdhci_cdns_sd4_phy_param_parse(struct device_node *np,
- struct sdhci_cdns_priv *priv)
+ struct sdhci_cdns_sd4_phy *phy)
{
- struct sdhci_cdns_sd4_phy_param *p = priv->phy_params;
+ struct sdhci_cdns_sd4_phy_param *p = phy->phy_params;
u32 val;
int ret, i;
@@ -172,10 +180,11 @@ static void sdhci_cdns_sd4_phy_param_parse(struct device_node *np,
static int sdhci_cdns_sd4_phy_init(struct sdhci_cdns_priv *priv)
{
int ret, i;
+ struct sdhci_cdns_sd4_phy *phy = priv->phy;
- for (i = 0; i < priv->nr_phy_params; i++) {
- ret = sdhci_cdns_sd4_write_phy_reg(priv, priv->phy_params[i].addr,
- priv->phy_params[i].data);
+ for (i = 0; i < phy->nr_phy_params; i++) {
+ ret = sdhci_cdns_sd4_write_phy_reg(priv, phy->phy_params[i].addr,
+ phy->phy_params[i].data);
if (ret)
return ret;
}
@@ -218,6 +227,27 @@ static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
}
+static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,
+ struct sdhci_cdns_priv *priv)
+{
+ unsigned int nr_phy_params;
+ struct sdhci_cdns_sd4_phy *phy;
+ struct device *dev = &pdev->dev;
+
+ nr_phy_params = sdhci_cdns_sd4_phy_param_count(dev->of_node);
+ phy = devm_kzalloc(dev, struct_size(phy, phy_params, nr_phy_params),
+ GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ phy->nr_phy_params = nr_phy_params;
+
+ sdhci_cdns_sd4_phy_param_parse(dev->of_node, phy);
+ priv->phy = phy;
+
+ return 0;
+}
+
static int sdhci_cdns_sd4_set_tune_val(struct sdhci_host *host, unsigned int val)
{
struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
@@ -420,6 +450,8 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
};
static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
+ .phy_init = sdhci_cdns_sd4_phy_init,
+ .phy_probe = sdhci_cdns_sd4_phy_probe,
.pltfm_data = {
.ops = &sdhci_cdns_sd4_ops,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
@@ -428,12 +460,16 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = {
.init = elba_drv_init,
+ .phy_init = sdhci_cdns_sd4_phy_init,
+ .phy_probe = sdhci_cdns_sd4_phy_probe,
.pltfm_data = {
.ops = &sdhci_elba_ops,
},
};
static const struct sdhci_cdns_drv_data sdhci_cdns_sd4_drv_data = {
+ .phy_init = sdhci_cdns_sd4_phy_init,
+ .phy_probe = sdhci_cdns_sd4_phy_probe,
.pltfm_data = {
.ops = &sdhci_cdns_sd4_ops,
},
@@ -482,7 +518,6 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_cdns_priv *priv;
struct clk *clk;
- unsigned int nr_phy_params;
int ret;
struct device *dev = &pdev->dev;
static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
@@ -496,12 +531,12 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
return ret;
data = of_device_get_match_data(dev);
- if (!data)
- data = &sdhci_cdns_sd4_drv_data;
+ if (!data) {
+ ret = -EINVAL;
+ goto disable_clk;
+ }
- nr_phy_params = sdhci_cdns_sd4_phy_param_count(dev->of_node);
- host = sdhci_pltfm_init(pdev, &data->pltfm_data,
- struct_size(priv, phy_params, nr_phy_params));
+ host = sdhci_pltfm_init(pdev, &data->pltfm_data, sizeof(*priv));
if (IS_ERR(host)) {
ret = PTR_ERR(host);
goto disable_clk;
@@ -511,10 +546,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
pltfm_host->clk = clk;
priv = sdhci_pltfm_priv(pltfm_host);
- priv->nr_phy_params = nr_phy_params;
priv->hrs_addr = host->ioaddr;
priv->enhanced_strobe = false;
priv->priv_writel = cdns_writel;
+ priv->cdns_data = data;
host->ioaddr += SDHCI_CDNS_SRS_BASE;
host->mmc_host_ops.hs400_enhanced_strobe =
sdhci_cdns_hs400_enhanced_strobe;
@@ -532,9 +567,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
if (ret)
goto free;
- sdhci_cdns_sd4_phy_param_parse(dev->of_node, priv);
+ ret = data->phy_probe(pdev, priv);
+ if (ret)
+ goto free;
- ret = sdhci_cdns_sd4_phy_init(priv);
+ ret = priv->cdns_data->phy_init(priv);
if (ret)
goto free;
@@ -574,7 +611,7 @@ static int sdhci_cdns_resume(struct device *dev)
if (ret)
return ret;
- ret = sdhci_cdns_sd4_phy_init(priv);
+ ret = priv->cdns_data->phy_init(priv);
if (ret)
goto disable_clk;
@@ -604,7 +641,10 @@ static const struct of_device_id sdhci_cdns_match[] = {
.compatible = "amd,pensando-elba-sd4hc",
.data = &sdhci_elba_drv_data,
},
- { .compatible = "cdns,sd4hc" },
+ {
+ .compatible = "cdns,sd4hc",
+ .data = &sdhci_cdns_sd4_drv_data,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v4 2/6] mmc: sdhci-cadence: Restructure the code
2023-07-17 12:51 ` [PATCH v4 2/6] mmc: sdhci-cadence: Restructure the code Piyush Malgujar
@ 2023-07-26 12:41 ` Adrian Hunter
0 siblings, 0 replies; 16+ messages in thread
From: Adrian Hunter @ 2023-07-26 12:41 UTC (permalink / raw)
To: Piyush Malgujar, linux-mmc, linux-kernel, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva, Dhananjay Kangude, Brad Larson
On 17/07/23 15:51, Piyush Malgujar wrote:
> From: Dhananjay Kangude <dkangude@cadence.com>
>
> Restructured the code, added controller version specific init for
> SD4 operations with no change to existing functionality.
>
> Signed-off-by: Dhananjay Kangude <dkangude@cadence.com>
> Co-developed-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> ---
> drivers/mmc/host/sdhci-cadence.c | 76 ++++++++++++++++++++++++--------
> 1 file changed, 58 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index 9bb38281bcb244b0be91ef579046c40de7a06e1f..98fe752bcf27a71607623f3cb1c36f1a16d688a4 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -60,11 +60,17 @@
> */
> #define SDHCI_CDNS_MAX_TUNING_LOOP 40
>
> +struct sdhci_cdns_priv;
Unnecessary forward declaration.
> +
> struct sdhci_cdns_sd4_phy_param {
> u8 addr;
> u8 data;
> };
>
> +struct sdhci_cdns_sd4_phy {
> + unsigned int nr_phy_params;
> + struct sdhci_cdns_sd4_phy_param phy_params[];
> +};
> struct sdhci_cdns_priv {
> void __iomem *hrs_addr;
> void __iomem *ctl_addr; /* write control */
> @@ -72,8 +78,8 @@ struct sdhci_cdns_priv {
> bool enhanced_strobe;
> void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
> struct reset_control *rst_hw;
> - unsigned int nr_phy_params;
> - struct sdhci_cdns_sd4_phy_param phy_params[];
> + const struct sdhci_cdns_drv_data *cdns_data;
> + void *phy;
> };
>
> struct sdhci_cdns_sd4_phy_cfg {
> @@ -83,6 +89,8 @@ struct sdhci_cdns_sd4_phy_cfg {
>
> struct sdhci_cdns_drv_data {
> int (*init)(struct platform_device *pdev);
> + int (*phy_init)(struct sdhci_cdns_priv *priv);
> + int (*phy_probe)(struct platform_device *pdev, struct sdhci_cdns_priv *priv);
> const struct sdhci_pltfm_data pltfm_data;
> };
>
> @@ -151,9 +159,9 @@ static unsigned int sdhci_cdns_sd4_phy_param_count(struct device_node *np)
> }
>
> static void sdhci_cdns_sd4_phy_param_parse(struct device_node *np,
> - struct sdhci_cdns_priv *priv)
> + struct sdhci_cdns_sd4_phy *phy)
> {
> - struct sdhci_cdns_sd4_phy_param *p = priv->phy_params;
> + struct sdhci_cdns_sd4_phy_param *p = phy->phy_params;
> u32 val;
> int ret, i;
>
> @@ -172,10 +180,11 @@ static void sdhci_cdns_sd4_phy_param_parse(struct device_node *np,
> static int sdhci_cdns_sd4_phy_init(struct sdhci_cdns_priv *priv)
> {
> int ret, i;
> + struct sdhci_cdns_sd4_phy *phy = priv->phy;
>
> - for (i = 0; i < priv->nr_phy_params; i++) {
> - ret = sdhci_cdns_sd4_write_phy_reg(priv, priv->phy_params[i].addr,
> - priv->phy_params[i].data);
> + for (i = 0; i < phy->nr_phy_params; i++) {
> + ret = sdhci_cdns_sd4_write_phy_reg(priv, phy->phy_params[i].addr,
> + phy->phy_params[i].data);
> if (ret)
> return ret;
> }
> @@ -218,6 +227,27 @@ static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
> return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
> }
>
> +static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,
> + struct sdhci_cdns_priv *priv)
> +{
> + unsigned int nr_phy_params;
> + struct sdhci_cdns_sd4_phy *phy;
> + struct device *dev = &pdev->dev;
> +
> + nr_phy_params = sdhci_cdns_sd4_phy_param_count(dev->of_node);
> + phy = devm_kzalloc(dev, struct_size(phy, phy_params, nr_phy_params),
> + GFP_KERNEL);
> + if (!phy)
> + return -ENOMEM;
> +
> + phy->nr_phy_params = nr_phy_params;
> +
> + sdhci_cdns_sd4_phy_param_parse(dev->of_node, phy);
> + priv->phy = phy;
> +
> + return 0;
> +}
> +
> static int sdhci_cdns_sd4_set_tune_val(struct sdhci_host *host, unsigned int val)
> {
> struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> @@ -420,6 +450,8 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
> };
>
> static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
> + .phy_init = sdhci_cdns_sd4_phy_init,
> + .phy_probe = sdhci_cdns_sd4_phy_probe,
> .pltfm_data = {
> .ops = &sdhci_cdns_sd4_ops,
> .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> @@ -428,12 +460,16 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
>
> static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = {
> .init = elba_drv_init,
> + .phy_init = sdhci_cdns_sd4_phy_init,
> + .phy_probe = sdhci_cdns_sd4_phy_probe,
> .pltfm_data = {
> .ops = &sdhci_elba_ops,
> },
> };
>
> static const struct sdhci_cdns_drv_data sdhci_cdns_sd4_drv_data = {
> + .phy_init = sdhci_cdns_sd4_phy_init,
> + .phy_probe = sdhci_cdns_sd4_phy_probe,
> .pltfm_data = {
> .ops = &sdhci_cdns_sd4_ops,
> },
> @@ -482,7 +518,6 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> struct sdhci_pltfm_host *pltfm_host;
> struct sdhci_cdns_priv *priv;
> struct clk *clk;
> - unsigned int nr_phy_params;
> int ret;
> struct device *dev = &pdev->dev;
> static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
> @@ -496,12 +531,12 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> return ret;
>
> data = of_device_get_match_data(dev);
> - if (!data)
> - data = &sdhci_cdns_sd4_drv_data;
Why change this?
> + if (!data) {
> + ret = -EINVAL;
> + goto disable_clk;
> + }
>
> - nr_phy_params = sdhci_cdns_sd4_phy_param_count(dev->of_node);
> - host = sdhci_pltfm_init(pdev, &data->pltfm_data,
> - struct_size(priv, phy_params, nr_phy_params));
> + host = sdhci_pltfm_init(pdev, &data->pltfm_data, sizeof(*priv));
> if (IS_ERR(host)) {
> ret = PTR_ERR(host);
> goto disable_clk;
> @@ -511,10 +546,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> pltfm_host->clk = clk;
>
> priv = sdhci_pltfm_priv(pltfm_host);
> - priv->nr_phy_params = nr_phy_params;
> priv->hrs_addr = host->ioaddr;
> priv->enhanced_strobe = false;
> priv->priv_writel = cdns_writel;
> + priv->cdns_data = data;
> host->ioaddr += SDHCI_CDNS_SRS_BASE;
> host->mmc_host_ops.hs400_enhanced_strobe =
> sdhci_cdns_hs400_enhanced_strobe;
> @@ -532,9 +567,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> if (ret)
> goto free;
>
> - sdhci_cdns_sd4_phy_param_parse(dev->of_node, priv);
> + ret = data->phy_probe(pdev, priv);
> + if (ret)
> + goto free;
>
> - ret = sdhci_cdns_sd4_phy_init(priv);
> + ret = priv->cdns_data->phy_init(priv);
data->phy_init() would be consistent with data->phy_probe()
instead of priv->cdns_data->phy_init()
> if (ret)
> goto free;
>
> @@ -574,7 +611,7 @@ static int sdhci_cdns_resume(struct device *dev)
> if (ret)
> return ret;
>
> - ret = sdhci_cdns_sd4_phy_init(priv);
> + ret = priv->cdns_data->phy_init(priv);
> if (ret)
> goto disable_clk;
>
> @@ -604,7 +641,10 @@ static const struct of_device_id sdhci_cdns_match[] = {
> .compatible = "amd,pensando-elba-sd4hc",
> .data = &sdhci_elba_drv_data,
> },
> - { .compatible = "cdns,sd4hc" },
> + {
> + .compatible = "cdns,sd4hc",
> + .data = &sdhci_cdns_sd4_drv_data,
Why change this?
> + },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 3/6] mmc: sdhci-cadence: SD6 controller support
2023-07-17 12:51 [PATCH v4 0/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
2023-07-17 12:51 ` [PATCH v4 1/6] mmc: sdhci-cadence: Rename functions/structures to SD4 specific Piyush Malgujar
2023-07-17 12:51 ` [PATCH v4 2/6] mmc: sdhci-cadence: Restructure the code Piyush Malgujar
@ 2023-07-17 12:51 ` Piyush Malgujar
2023-07-17 20:04 ` Krzysztof Kozlowski
2023-07-26 12:41 ` Adrian Hunter
2023-07-17 12:51 ` [PATCH v4 4/6] mmc: sdhci-cadence: enable MMC_SDHCI_IO_ACCESSORS support Piyush Malgujar
` (2 subsequent siblings)
5 siblings, 2 replies; 16+ messages in thread
From: Piyush Malgujar @ 2023-07-17 12:51 UTC (permalink / raw)
To: linux-mmc, linux-kernel, adrian.hunter, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva, Dhananjay Kangude, Piyush Malgujar
From: Dhananjay Kangude <dkangude@cadence.com>
Add support for SD6 controller for Marvell CN10k SoCs and related ops
along with support for HS400 and HS400ES emmc modes.
Updated HS200 tuning values and support to read tune configuration
from FDT and support to configure and read host side drive strength,
slew from device tree.
Signed-off-by: Dhananjay Kangude <dkangude@cadence.com>
Co-developed-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
---
drivers/mmc/host/sdhci-cadence.c | 1256 +++++++++++++++++++++++++++++-
1 file changed, 1253 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 98fe752bcf27a71607623f3cb1c36f1a16d688a4..8bcf585185053b0afaff2625d62316cec1824fa3 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -16,8 +16,20 @@
#include "sdhci-pltfm.h"
+#define SDMCLK_MAX_FREQ 200000000
+
+#define DEFAULT_CMD_DELAY 16
+#define SDHCI_CDNS_TUNE_START 16
+#define SDHCI_CDNS_TUNE_STEP 6
+#define SDHCI_CDNS_TUNE_ITERATIONS 40
+
+#define SDHCI_CDNS_HRS00 0x00
+#define SDHCI_CDNS_HRS00_SWR BIT(0)
+
+#define SDHCI_CDNS_HRS02 0x08 /* PHY access port */
+#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
+
/* SD 4.0 Controller HRS - Host Register Set (specific to Cadence) */
-#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
#define SDHCI_CDNS_SD4_HRS04_ACK BIT(26)
#define SDHCI_CDNS_SD4_HRS04_RD BIT(25)
#define SDHCI_CDNS_SD4_HRS04_WR BIT(24)
@@ -30,12 +42,89 @@
#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
#define SDHCI_CDNS_HRS06_MODE_SD 0x0
+#define SDHCI_CDNS_HRS06_MODE_LEGACY 0x1
#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
+/* SD 6.0 Controller HRS - Host Register Set (Specific to Cadence) */
+#define SDHCI_CDNS_SD6_HRS04_ADDR GENMASK(15, 0)
+
+#define SDHCI_CDNS_HRS05 0x14
+
+#define SDHCI_CDNS_HRS07 0x1C
+#define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16)
+#define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0)
+
+#define SDHCI_CDNS_HRS09 0x24
+#define SDHCI_CDNS_HRS09_RDDATA_EN BIT(16)
+#define SDHCI_CDNS_HRS09_RDCMD_EN BIT(15)
+#define SDHCI_CDNS_HRS09_EXTENDED_WR_MODE BIT(3)
+#define SDHCI_CDNS_HRS09_EXTENDED_RD_MODE BIT(2)
+#define SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE BIT(1)
+#define SDHCI_CDNS_HRS09_PHY_SW_RESET BIT(0)
+
+#define SDHCI_CDNS_HRS10 0x28
+#define SDHCI_CDNS_HRS10_HCSDCLKADJ GENMASK(19, 16)
+
+#define SDHCI_CDNS_HRS11 0x2c
+/*Reset related*/
+#define SDHCI_CDNS_SRS11_SW_RESET_ALL BIT(24)
+#define SDHCI_CDNS_SRS11_SW_RESET_CMD BIT(25)
+#define SDHCI_CDNS_SRS11_SW_RESET_DAT BIT(26)
+
+#define SDHCI_CDNS_HRS16 0x40
+#define SDHCI_CDNS_HRS16_WRDATA1_SDCLK_DLY GENMASK(31, 28)
+#define SDHCI_CDNS_HRS16_WRDATA0_SDCLK_DLY GENMASK(27, 24)
+#define SDHCI_CDNS_HRS16_WRCMD1_SDCLK_DLY GENMASK(23, 20)
+#define SDHCI_CDNS_HRS16_WRCMD0_SDCLK_DLY GENMASK(19, 16)
+#define SDHCI_CDNS_HRS16_WRDATA1_DLY GENMASK(15, 12)
+#define SDHCI_CDNS_HRS16_WRDATA0_DLY GENMASK(11, 8)
+#define SDHCI_CDNS_HRS16_WRCMD1_DLY GENMASK(7, 4)
+#define SDHCI_CDNS_HRS16_WRCMD0_DLY GENMASK(3, 0)
+
+/* PHY registers for SD6 controller */
+#define SDHCI_CDNS_SD6_PHY_DQ_TIMING 0x2000
+#define SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_ALWAYS_ON BIT(31)
+#define SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_END GENMASK(29, 27)
+#define SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_START GENMASK(26, 24)
+#define SDHCI_CDNS_SD6_PHY_DQ_TIMING_DATA_SELECT_OE_END GENMASK(2, 0)
+
+#define SDHCI_CDNS_SD6_PHY_DQS_TIMING 0x2004
+#define SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_EXT_LPBK_DQS BIT(22)
+#define SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_LPBK_DQS BIT(21)
+#define SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS BIT(20)
+#define SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS_CMD BIT(19)
+
+#define SDHCI_CDNS_SD6_PHY_GATE_LPBK 0x2008
+#define SDHCI_CDNS_SD6_PHY_GATE_LPBK_SYNC_METHOD BIT(31)
+#define SDHCI_CDNS_SD6_PHY_GATE_LPBK_SW_HALF_CYCLE_SHIFT BIT(28)
+#define SDHCI_CDNS_SD6_PHY_GATE_LPBK_RD_DEL_SEL GENMASK(24, 19)
+#define SDHCI_CDNS_SD6_PHY_GATE_LPBK_GATE_CFG_ALWAYS_ON BIT(6)
+
+#define SDHCI_CDNS_SD6_PHY_DLL_MASTER 0x200C
+#define SDHCI_CDNS_SD6_PHY_DLL_MASTER_BYPASS_MODE BIT(23)
+#define SDHCI_CDNS_SD6_PHY_DLL_MASTER_PHASE_DETECT_SEL GENMASK(22, 20)
+#define SDHCI_CDNS_SD6_PHY_DLL_MASTER_DLL_LOCK_NUM GENMASK(18, 16)
+#define SDHCI_CDNS_SD6_PHY_DLL_MASTER_DLL_START_POINT GENMASK(7, 0)
+
+#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE 0x2010
+#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_CMD_DELAY GENMASK(31, 24)
+#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WRDQS_DELAY GENMASK(23, 16)
+#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WR_DELAY GENMASK(15, 8)
+#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_DELAY GENMASK(7, 0)
+
+#define SDHCI_CDNS_SD6_PHY_CTRL 0x2080
+#define SDHCI_CDNS_SD6_PHY_CTRL_PHONY_DQS_TIMING GENMASK(9, 4)
+
+#define SDHCI_CDNS_SD6_PHY_GPIO_CTRL0 0x2088
+#define SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_DRV GENMASK(6, 5)
+#define SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_DRV_OVR_EN BIT(4)
+#define SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_SLEW GENMASK(2, 1)
+#define SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_SLEW_OVR_EN BIT(0)
+
/* SRS - Slot Register Set (SDHCI-compatible) */
#define SDHCI_CDNS_SRS_BASE 0x200
@@ -60,6 +149,10 @@
*/
#define SDHCI_CDNS_MAX_TUNING_LOOP 40
+static int tune_val_start = SDHCI_CDNS_TUNE_START;
+static int tune_val_step = SDHCI_CDNS_TUNE_STEP;
+static int max_tune_iter = SDHCI_CDNS_TUNE_ITERATIONS;
+
struct sdhci_cdns_priv;
struct sdhci_cdns_sd4_phy_param {
@@ -108,6 +201,558 @@ static const struct sdhci_cdns_sd4_phy_cfg sdhci_cdns_sd4_phy_cfgs[] = {
{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
};
+enum sdhci_cdns_sd6_phy_lock_mode {
+ SDHCI_CDNS_SD6_PHY_LOCK_MODE_FULL_CLK = 0,
+ SDHCI_CDNS_SD6_PHY_LOCK_MODE_HALF_CLK = 2,
+ SDHCI_CDNS_SD6_PHY_LOCK_MODE_SATURATION = 3,
+};
+
+struct sdhci_cdns_sd6_phy_timings {
+ u32 t_cmd_output_min;
+ u32 t_cmd_output_max;
+ u32 t_dat_output_min;
+ u32 t_dat_output_max;
+ u32 t_cmd_input_min;
+ u32 t_cmd_input_max;
+ u32 t_dat_input_min;
+ u32 t_dat_input_max;
+ u32 t_sdclk_min;
+ u32 t_sdclk_max;
+};
+
+struct sdhci_cdns_sd6_phy_delays {
+ u32 phy_sdclk_delay;
+ u32 phy_cmd_o_delay;
+ u32 phy_dat_o_delay;
+ u32 iocell_input_delay;
+ u32 iocell_output_delay;
+ u32 delay_element_org;
+ u32 delay_element;
+};
+
+struct sdhci_cdns_sd6_phy_settings {
+ /* SDHCI_CDNS_SD6_PHY_DLL_SLAVE */
+ u32 cp_read_dqs_cmd_delay;
+ u32 cp_read_dqs_delay;
+ u32 cp_clk_wr_delay;
+ u32 cp_clk_wrdqs_delay;
+
+ /* SDHCI_CDNS_SD6_PHY_DLL_MASTER */
+ u32 cp_dll_bypass_mode;
+ u32 cp_dll_start_point;
+
+ /* SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 */
+ u32 cp_dll_locked_mode;
+
+ /* SDHCI_CDNS_SD6_PHY_GATE_LPBK */
+ u32 cp_gate_cfg_always_on;
+ u32 cp_sync_method;
+ u32 cp_rd_del_sel;
+ u32 cp_sw_half_cycle_shift;
+ u32 cp_underrun_suppress;
+
+ /* SDHCI_CDNS_SD6_PHY_DQ_TIMING */
+ u32 cp_io_mask_always_on;
+ u32 cp_io_mask_end;
+ u32 cp_io_mask_start;
+ u32 cp_data_select_oe_end;
+
+ /* SDHCI_CDNS_SD6_PHY_DQS_TIMING */
+ u32 cp_use_ext_lpbk_dqs;
+ u32 cp_use_lpbk_dqs;
+ u8 cp_use_phony_dqs;
+ u8 cp_use_phony_dqs_cmd;
+
+ /* HRS 09 */
+ u8 sdhc_extended_rd_mode;
+ u8 sdhc_extended_wr_mode;
+ u32 sdhc_rdcmd_en;
+ u32 sdhc_rddata_en;
+
+ /* HRS10 */
+ u32 sdhc_hcsdclkadj;
+
+ /* HRS 07 */
+ u32 sdhc_idelay_val;
+ u32 sdhc_rw_compensate;
+
+ /* SRS 11 */
+ u32 sdhc_sdcfsh;
+ u32 sdhc_sdcfsl;
+
+ /* HRS 16 */
+ u32 sdhc_wrcmd0_dly;
+ u32 sdhc_wrcmd0_sdclk_dly;
+ u32 sdhc_wrcmd1_dly;
+ u32 sdhc_wrcmd1_sdclk_dly;
+ u32 sdhc_wrdata0_dly;
+ u32 sdhc_wrdata0_sdclk_dly;
+ u32 sdhc_wrdata1_dly;
+ u32 sdhc_wrdata1_sdclk_dly;
+
+ u32 hs200_tune_val;
+ u32 drive;
+ u32 slew;
+};
+
+struct sdhci_cdns_sd6_phy_intermediate_results {
+ u32 t_sdmclk_calc;
+ u32 dll_max_value;
+};
+
+struct sdhci_cdns_sd6_phy {
+ struct sdhci_cdns_sd6_phy_timings t;
+ struct sdhci_cdns_sd6_phy_delays d;
+ u32 t_sdmclk;
+ struct sdhci_cdns_sd6_phy_settings settings;
+ struct sdhci_cdns_sd6_phy_intermediate_results vars;
+ bool ddr;
+ bool tune_cmd;
+ bool tune_dat;
+ bool strobe_cmd;
+ bool strobe_dat;
+ int mode;
+ int t_sdclk;
+};
+
+static void init_hs(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 2000, .t_cmd_output_max = t_sdclk - 6000,
+ .t_dat_output_min = 2000, .t_dat_output_max = t_sdclk - 6000,
+ .t_cmd_input_min = 14000, .t_cmd_input_max = t_sdclk + 2500,
+ .t_dat_input_min = 14000, .t_dat_input_max = t_sdclk + 2500,
+ .t_sdclk_min = 1000000 / 50, .t_sdclk_max = 1000000 / 0.4
+ };
+}
+
+static void init_uhs_sdr12(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 3000,
+ .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 3000,
+ .t_cmd_input_min = 14000, .t_cmd_input_max = t_sdclk + 1500,
+ .t_dat_input_min = 14000, .t_dat_input_max = t_sdclk + 1500,
+ .t_sdclk_min = 1000000 / 25, .t_sdclk_max = 1000000 / 0.4
+ };
+}
+
+static void init_uhs_sdr25(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 3000,
+ .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 3000,
+ .t_cmd_input_min = 14000, .t_cmd_input_max = t_sdclk + 1500,
+ .t_dat_input_min = 14000, .t_dat_input_max = t_sdclk + 1500,
+ .t_sdclk_min = 1000000 / 50, .t_sdclk_max = 1000000 / 0.4
+ };
+}
+
+static void init_uhs_sdr50(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 3000,
+ .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 3000,
+ .t_cmd_input_min = 7500, .t_cmd_input_max = t_sdclk + 1500,
+ .t_dat_input_min = 7500, .t_dat_input_max = t_sdclk + 1500,
+ .t_sdclk_min = 1000000 / 100, .t_sdclk_max = 1000000 / 0.4
+ };
+}
+
+static void init_uhs_sdr104(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 1400,
+ .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 1400,
+ .t_cmd_input_min = 1000, .t_cmd_input_max = t_sdclk + 1000,
+ .t_dat_input_min = 1000, .t_dat_input_max = t_sdclk + 1000,
+ .t_sdclk_min = 1000000 / 200, .t_sdclk_max = 1000000 / 100
+ };
+}
+
+static void init_uhs_ddr50(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 3000,
+ .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 3000,
+ .t_cmd_input_min = 13700, .t_cmd_input_max = t_sdclk + 1500,
+ .t_dat_input_min = 7000, .t_dat_input_max = t_sdclk + 1500,
+ .t_sdclk_min = 1000000 / 50, .t_sdclk_max = 1000000 / 0.4
+ };
+}
+
+static void init_emmc_legacy(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 3000, .t_cmd_output_max = t_sdclk - 3000,
+ .t_dat_output_min = 3000, .t_dat_output_max = t_sdclk - 3000,
+ .t_cmd_input_min = 11700, .t_cmd_input_max = t_sdclk + 8300,
+ .t_dat_input_min = 11700, .t_dat_input_max = t_sdclk + 8300,
+ .t_sdclk_min = 1000000 / 25, .t_sdclk_max = 1000000 / 0.4
+ };
+}
+
+static void init_emmc_sdr(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 3000, .t_cmd_output_max = t_sdclk - 3000,
+ .t_dat_output_min = 3000, .t_dat_output_max = t_sdclk - 3000,
+ .t_cmd_input_min = 13700, .t_cmd_input_max = t_sdclk + 2500,
+ .t_dat_input_min = 13700, .t_dat_input_max = t_sdclk + 2500,
+ .t_sdclk_min = 1000000 / 50, .t_sdclk_max = 1000000 / 0.4
+ };
+}
+
+static void init_emmc_ddr(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 3000, .t_cmd_output_max = t_sdclk - 3000,
+ .t_dat_output_min = 2500, .t_dat_output_max = t_sdclk - 2500,
+ .t_cmd_input_min = 13700, .t_cmd_input_max = t_sdclk + 2500,
+ .t_dat_input_min = 7000, .t_dat_input_max = t_sdclk + 1500,
+ .t_sdclk_min = 1000000 / 50, .t_sdclk_max = 1000000 / 0.4
+ };
+}
+
+static void init_emmc_hs200(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 1400,
+ .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 1400,
+ .t_cmd_input_min = 1000, .t_cmd_input_max = t_sdclk + 1000,
+ .t_dat_input_min = 1000, .t_dat_input_max = t_sdclk + 1000,
+ .t_sdclk_min = 1000000 / 200, .t_sdclk_max = 1000000 / 100
+ };
+}
+
+/* HS400 and HS400ES */
+static void init_emmc_hs400(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
+{
+ *t = (struct sdhci_cdns_sd6_phy_timings){
+ .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 1400,
+ .t_dat_output_min = 400, .t_dat_output_max = t_sdclk - 400,
+ .t_cmd_input_min = 1000, .t_cmd_input_max = t_sdclk + 1000,
+ .t_dat_input_min = 1000, .t_dat_input_max = t_sdclk + 1000,
+ .t_sdclk_min = 1000000 / 200, .t_sdclk_max = 1000000 / 100
+ };
+}
+
+static void (*init_timings[])(struct sdhci_cdns_sd6_phy_timings*, int) = {
+ &init_hs, &init_emmc_legacy, &init_emmc_sdr,
+ &init_emmc_ddr, &init_emmc_hs200, &init_emmc_hs400,
+ &init_uhs_sdr12, &init_uhs_sdr25, &init_uhs_sdr50,
+ &init_uhs_sdr104, &init_uhs_ddr50
+};
+
+static u32 read_dqs_cmd_delay, clk_wrdqs_delay, clk_wr_delay, read_dqs_delay;
+
+static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host, unsigned int timing);
+
+static int sdhci_cdns_sd6_phy_lock_dll(struct sdhci_cdns_sd6_phy *phy)
+{
+ u32 delay_element = phy->d.delay_element_org;
+ u32 delay_elements_in_sdmclk;
+ enum sdhci_cdns_sd6_phy_lock_mode mode;
+
+ delay_elements_in_sdmclk = DIV_ROUND_UP(phy->t_sdmclk, delay_element);
+ if (delay_elements_in_sdmclk > 256) {
+ delay_element *= 2;
+ delay_elements_in_sdmclk = DIV_ROUND_UP(phy->t_sdmclk,
+ delay_element);
+
+ if (delay_elements_in_sdmclk > 256)
+ return -1;
+
+ mode = SDHCI_CDNS_SD6_PHY_LOCK_MODE_HALF_CLK;
+ phy->vars.dll_max_value = 127;
+ } else {
+ mode = SDHCI_CDNS_SD6_PHY_LOCK_MODE_FULL_CLK;
+ phy->vars.dll_max_value = 255;
+ }
+
+ phy->vars.t_sdmclk_calc = delay_element * delay_elements_in_sdmclk;
+ phy->d.delay_element = delay_element;
+ phy->settings.cp_dll_locked_mode = mode;
+ phy->settings.cp_dll_bypass_mode = 0;
+
+ return 0;
+}
+
+static void sdhci_cdns_sd6_phy_dll_bypass(struct sdhci_cdns_sd6_phy *phy)
+{
+ phy->vars.dll_max_value = 256;
+ phy->settings.cp_dll_bypass_mode = 1;
+ phy->settings.cp_dll_locked_mode =
+ SDHCI_CDNS_SD6_PHY_LOCK_MODE_SATURATION;
+}
+
+static void sdhci_cdns_sd6_phy_configure_dll(struct sdhci_cdns_sd6_phy *phy)
+{
+ if (phy->settings.sdhc_extended_wr_mode == 0) {
+ if (sdhci_cdns_sd6_phy_lock_dll(phy) == 0)
+ return;
+ }
+ sdhci_cdns_sd6_phy_dll_bypass(phy);
+}
+
+static void sdhci_cdns_sd6_phy_calc_out(struct sdhci_cdns_sd6_phy *phy,
+ bool cmd_not_dat)
+{
+ u32 wr0_dly = 0, wr1_dly = 0, output_min, output_max, phy_o_delay,
+ clk_wr_delay = 0, wr0_sdclk_dly = 0, wr1_sdclk_dly = 0;
+ bool data_ddr = phy->ddr && !cmd_not_dat;
+ int t;
+
+ if (cmd_not_dat) {
+ output_min = phy->t.t_cmd_output_min;
+ output_max = phy->t.t_cmd_output_max;
+ phy_o_delay = phy->d.phy_cmd_o_delay;
+ } else {
+ output_min = phy->t.t_dat_output_min;
+ output_max = phy->t.t_dat_output_max;
+ phy_o_delay = phy->d.phy_dat_o_delay;
+ }
+
+ if (data_ddr) {
+ wr0_sdclk_dly = 1;
+ wr1_sdclk_dly = 1;
+ }
+
+ t = phy_o_delay - phy->d.phy_sdclk_delay - output_min;
+ if (t < 0 && phy->settings.sdhc_extended_wr_mode == 1) {
+ u32 n_half_cycle = DIV_ROUND_UP(-t * 2, phy->t_sdmclk);
+
+ wr0_dly = (n_half_cycle + 1) / 2;
+ if (data_ddr)
+ wr1_dly = (n_half_cycle + 1) / 2;
+ else
+ wr1_dly = (n_half_cycle + 1) % 2 + wr0_dly - 1;
+ }
+
+ if (phy->settings.sdhc_extended_wr_mode == 0) {
+ u32 out_hold, out_setup, out_hold_margin;
+ u32 n;
+
+ if (!data_ddr)
+ wr0_dly = 1;
+
+ out_setup = output_max;
+ out_hold = output_min;
+ out_hold_margin = DIV_ROUND_UP(out_setup - out_hold, 4);
+ out_hold += out_hold_margin;
+
+ if (phy->settings.cp_dll_bypass_mode == 0)
+ n = DIV_ROUND_UP(256 * out_hold, phy->vars.t_sdmclk_calc);
+ else
+ n = DIV_ROUND_UP(out_hold, phy->d.delay_element) - 1;
+
+ if (n <= phy->vars.dll_max_value)
+ clk_wr_delay = n;
+ else
+ clk_wr_delay = 255;
+ } else {
+ /* sdhc_extended_wr_mode = 1 - PHY IO cell work in SDR mode */
+ clk_wr_delay = 0;
+ }
+
+ if (cmd_not_dat) {
+ phy->settings.sdhc_wrcmd0_dly = wr0_dly;
+ phy->settings.sdhc_wrcmd1_dly = wr1_dly;
+ phy->settings.cp_clk_wrdqs_delay = clk_wr_delay;
+ phy->settings.sdhc_wrcmd0_sdclk_dly = wr0_sdclk_dly;
+ phy->settings.sdhc_wrcmd1_sdclk_dly = wr1_sdclk_dly;
+ } else {
+ phy->settings.sdhc_wrdata0_dly = wr0_dly;
+ phy->settings.sdhc_wrdata1_dly = wr1_dly;
+ phy->settings.cp_clk_wr_delay = clk_wr_delay;
+ phy->settings.sdhc_wrdata0_sdclk_dly = wr0_sdclk_dly;
+ phy->settings.sdhc_wrdata1_sdclk_dly = wr1_sdclk_dly;
+ }
+}
+
+static void sdhci_cdns_sd6_phy_calc_cmd_out(struct sdhci_cdns_sd6_phy *phy)
+{
+ sdhci_cdns_sd6_phy_calc_out(phy, true);
+}
+
+static void sdhci_cdns_sd6_phy_calc_cmd_in(struct sdhci_cdns_sd6_phy *phy)
+{
+ phy->settings.cp_io_mask_end =
+ ((phy->d.iocell_output_delay + phy->d.iocell_input_delay) * 2)
+ / phy->t_sdmclk;
+
+ if (phy->settings.cp_io_mask_end >= 8)
+ phy->settings.cp_io_mask_end = 7;
+
+ if (phy->strobe_cmd && phy->settings.cp_io_mask_end > 0)
+ phy->settings.cp_io_mask_end--;
+
+ if (phy->strobe_cmd) {
+ phy->settings.cp_use_phony_dqs_cmd = 0;
+ phy->settings.cp_read_dqs_cmd_delay = 64;
+ } else {
+ phy->settings.cp_use_phony_dqs_cmd = 1;
+ phy->settings.cp_read_dqs_cmd_delay = 0;
+ }
+
+ if ((phy->mode == MMC_TIMING_MMC_HS400 && !phy->strobe_cmd) ||
+ phy->mode == MMC_TIMING_MMC_HS200)
+ phy->settings.cp_read_dqs_cmd_delay =
+ phy->settings.hs200_tune_val;
+}
+
+static void sdhci_cdns_sd6_phy_calc_dat_in(struct sdhci_cdns_sd6_phy *phy)
+{
+ u32 hcsdclkadj = 0;
+
+ if (phy->strobe_dat) {
+ phy->settings.cp_use_phony_dqs = 0;
+ phy->settings.cp_read_dqs_delay = 64;
+ } else {
+ phy->settings.cp_use_phony_dqs = 1;
+ phy->settings.cp_read_dqs_delay = 0;
+ }
+
+ if (phy->mode == MMC_TIMING_MMC_HS200)
+ phy->settings.cp_read_dqs_delay =
+ phy->settings.hs200_tune_val;
+
+ if (phy->strobe_dat) {
+ /* dqs loopback input via IO cell */
+ hcsdclkadj += phy->d.iocell_input_delay;
+ /* dfi_dqs_in: mem_dqs -> clean_dqs_mod; delay of hic_dll_dqs_nand2 */
+ hcsdclkadj += phy->d.delay_element / 2;
+ /* delay line */
+ hcsdclkadj += phy->t_sdclk / 2;
+ /* PHY FIFO write pointer */
+ hcsdclkadj += phy->t_sdclk / 2 + phy->d.delay_element;
+ /* 1st synchronizer */
+ hcsdclkadj += DIV_ROUND_UP(hcsdclkadj, phy->t_sdmclk)
+ * phy->t_sdmclk - hcsdclkadj;
+ /*
+ * 2nd synchronizer + PHY FIFO read pointer + PHY rddata
+ * + PHY rddata registered, + FIFO 1st ciu_en
+ */
+ hcsdclkadj += 5 * phy->t_sdmclk;
+ /* FIFO 2st ciu_en */
+ hcsdclkadj += phy->t_sdclk;
+
+ hcsdclkadj /= phy->t_sdclk;
+ } else {
+ u32 n;
+
+ /* rebar PHY delay */
+ hcsdclkadj += 2 * phy->t_sdmclk;
+ /* rebar output via IO cell */
+ hcsdclkadj += phy->d.iocell_output_delay;
+ /* dqs loopback input via IO cell */
+ hcsdclkadj += phy->d.iocell_input_delay;
+ /* dfi_dqs_in: mem_dqs -> clean_dqs_mod delay of hic_dll_dqs_nand2 */
+ hcsdclkadj += phy->d.delay_element / 2;
+ /* dll: one delay element between SIGI_0 and SIGO_0 */
+ hcsdclkadj += phy->d.delay_element;
+ /* dfi_dqs_in: mem_dqs_delayed -> clk_dqs delay of hic_dll_dqs_nand2 */
+ hcsdclkadj += phy->d.delay_element / 2;
+ /* deskew DLL: clk_dqs -> clk_dqN: one delay element */
+ hcsdclkadj += phy->d.delay_element;
+
+ if (phy->t_sdclk == phy->t_sdmclk)
+ n = (hcsdclkadj - 2 * phy->t_sdmclk) / phy->t_sdclk;
+ else
+ n = hcsdclkadj / phy->t_sdclk;
+
+ /* phase shift within one t_sdclk clock cycle caused by rebar - lbk dqs delay */
+ hcsdclkadj = hcsdclkadj % phy->t_sdclk;
+ /* PHY FIFO write pointer */
+ hcsdclkadj += phy->t_sdclk / 2;
+ /* 1st synchronizer */
+ hcsdclkadj += DIV_ROUND_UP(hcsdclkadj, phy->t_sdmclk)
+ * phy->t_sdmclk - hcsdclkadj;
+ /*
+ * 2nd synchronizer + PHY FIFO read pointer + PHY rddata
+ * + PHY rddata registered
+ */
+ hcsdclkadj += 4 * phy->t_sdmclk;
+
+ if ((phy->t_sdclk / phy->t_sdmclk) > 1) {
+ u32 tmp1, tmp2;
+
+ tmp1 = hcsdclkadj;
+ tmp2 = (hcsdclkadj / phy->t_sdclk) * phy->t_sdclk
+ + phy->t_sdclk - phy->t_sdmclk;
+ if (tmp1 == tmp2)
+ tmp2 += phy->t_sdclk;
+
+ /* FIFO aligns to clock cycle before ciu_en */
+ hcsdclkadj += tmp2 - tmp1;
+ }
+
+ /* FIFO 1st ciu_en */
+ hcsdclkadj += phy->t_sdmclk;
+ /* FIFO 2nd ciu_en */
+ hcsdclkadj += phy->t_sdclk;
+
+ hcsdclkadj /= phy->t_sdclk;
+
+ hcsdclkadj += n;
+
+ if ((phy->t_sdclk / phy->t_sdmclk) >= 2) {
+ if (phy->mode == MMC_TIMING_UHS_DDR50 ||
+ phy->mode == MMC_TIMING_MMC_DDR52)
+ hcsdclkadj -= 2;
+ else
+ hcsdclkadj -= 1;
+ } else if ((phy->t_sdclk / phy->t_sdmclk) == 1) {
+ hcsdclkadj += 2;
+ }
+
+ if (phy->tune_dat)
+ hcsdclkadj -= 1;
+ }
+
+ if (hcsdclkadj > 15)
+ hcsdclkadj = 15;
+
+ phy->settings.sdhc_hcsdclkadj = hcsdclkadj;
+}
+
+static void sdhci_cdns_sd6_phy_calc_dat_out(struct sdhci_cdns_sd6_phy *phy)
+{
+ sdhci_cdns_sd6_phy_calc_out(phy, false);
+}
+
+static void sdhci_cdns_sd6_phy_calc_io(struct sdhci_cdns_sd6_phy *phy)
+{
+ u32 rw_compensate;
+
+ rw_compensate = (phy->d.iocell_input_delay + phy->d.iocell_output_delay)
+ / phy->t_sdmclk + phy->settings.sdhc_wrdata0_dly + 5 + 3;
+
+ phy->settings.sdhc_idelay_val = (2 * phy->d.iocell_input_delay)
+ / phy->t_sdmclk;
+
+ phy->settings.cp_io_mask_start = 0;
+ if (phy->t_sdclk == phy->t_sdmclk && rw_compensate > 10)
+ phy->settings.cp_io_mask_start = 2 * (rw_compensate - 10);
+
+ if (phy->mode == MMC_TIMING_UHS_SDR104)
+ phy->settings.cp_io_mask_start++;
+
+ if (phy->t_sdclk == phy->t_sdmclk && phy->mode == MMC_TIMING_UHS_SDR50)
+ phy->settings.cp_io_mask_start++;
+
+ phy->settings.sdhc_rw_compensate = rw_compensate;
+}
+
+static void sdhci_cdns_sd6_phy_calc_settings(struct sdhci_cdns_sd6_phy *phy)
+{
+ sdhci_cdns_sd6_phy_calc_cmd_out(phy);
+ sdhci_cdns_sd6_phy_calc_cmd_in(phy);
+ sdhci_cdns_sd6_phy_calc_dat_out(phy);
+ sdhci_cdns_sd6_phy_calc_dat_in(phy);
+ sdhci_cdns_sd6_phy_calc_io(phy);
+}
+
static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
void __iomem *reg)
{
@@ -188,7 +833,276 @@ static int sdhci_cdns_sd4_phy_init(struct sdhci_cdns_priv *priv)
if (ret)
return ret;
}
+ return 0;
+}
+static u32 sdhci_cdns_sd6_read_phy_reg(struct sdhci_cdns_priv *priv,
+ u32 addr)
+{
+ writel(FIELD_PREP(SDHCI_CDNS_SD6_HRS04_ADDR, addr),
+ priv->hrs_addr + SDHCI_CDNS_HRS04);
+ return readl(priv->hrs_addr + SDHCI_CDNS_HRS05);
+}
+
+static void sdhci_cdns_sd6_write_phy_reg(struct sdhci_cdns_priv *priv,
+ u32 addr, u32 data)
+{
+ writel(FIELD_PREP(SDHCI_CDNS_SD6_HRS04_ADDR, addr),
+ priv->hrs_addr + SDHCI_CDNS_HRS04);
+ writel(data, priv->hrs_addr + SDHCI_CDNS_HRS05);
+}
+
+static int sdhci_cdns_sd6_dll_reset(struct sdhci_cdns_priv *priv, bool reset)
+{
+ u32 reg;
+ int ret = 0;
+
+ reg = readl(priv->hrs_addr + SDHCI_CDNS_HRS09);
+ if (reset)
+ reg &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET;
+ else
+ reg |= SDHCI_CDNS_HRS09_PHY_SW_RESET;
+
+ writel(reg, priv->hrs_addr + SDHCI_CDNS_HRS09);
+
+ if (!reset)
+ ret = readl_poll_timeout(priv->hrs_addr + SDHCI_CDNS_HRS09,
+ reg,
+ (reg &
+ SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE),
+ 0, 0);
+
+ return ret;
+}
+
+static void sdhci_cdns_sd6_calc_phy(struct sdhci_cdns_sd6_phy *phy)
+{
+ if (phy->mode == MMC_TIMING_MMC_HS) {
+ phy->settings.cp_clk_wr_delay = 0;
+ phy->settings.cp_clk_wrdqs_delay = 0;
+ phy->settings.cp_data_select_oe_end = 1;
+ phy->settings.cp_dll_bypass_mode = 1;
+ phy->settings.cp_dll_locked_mode = 3;
+ phy->settings.cp_dll_start_point = 4;
+ phy->settings.cp_gate_cfg_always_on = 1;
+ phy->settings.cp_io_mask_always_on = 0;
+ phy->settings.cp_io_mask_end = 0;
+ phy->settings.cp_io_mask_start = 0;
+ phy->settings.cp_rd_del_sel = 52;
+ phy->settings.cp_read_dqs_cmd_delay = 0;
+ phy->settings.cp_read_dqs_delay = 0;
+ phy->settings.cp_sw_half_cycle_shift = 0;
+ phy->settings.cp_sync_method = 1;
+ phy->settings.cp_underrun_suppress = 1;
+ phy->settings.cp_use_ext_lpbk_dqs = 1;
+ phy->settings.cp_use_lpbk_dqs = 1;
+ phy->settings.cp_use_phony_dqs = 1;
+ phy->settings.cp_use_phony_dqs_cmd = 1;
+ phy->settings.sdhc_extended_rd_mode = 1;
+ phy->settings.sdhc_extended_wr_mode = 1;
+ phy->settings.sdhc_hcsdclkadj = 2;
+ phy->settings.sdhc_idelay_val = 0;
+ phy->settings.sdhc_rdcmd_en = 1;
+ phy->settings.sdhc_rddata_en = 1;
+ phy->settings.sdhc_rw_compensate = 9;
+ phy->settings.sdhc_sdcfsh = 0;
+ phy->settings.sdhc_sdcfsl = 4;
+ phy->settings.sdhc_wrcmd0_dly = 1;
+ phy->settings.sdhc_wrcmd0_sdclk_dly = 0;
+ phy->settings.sdhc_wrcmd1_dly = 0;
+ phy->settings.sdhc_wrcmd1_sdclk_dly = 0;
+ phy->settings.sdhc_wrdata0_dly = 1;
+ phy->settings.sdhc_wrdata0_sdclk_dly = 0;
+ phy->settings.sdhc_wrdata1_dly = 0;
+ phy->settings.sdhc_wrdata1_sdclk_dly = 0;
+ }
+}
+
+static
+int sdhci_cdns_sd6_get_delay_params(struct device *dev,
+ struct sdhci_cdns_priv *priv)
+{
+ struct sdhci_cdns_sd6_phy *phy = priv->phy;
+ int ret;
+
+ of_property_read_u32(dev->of_node, "marvell,iocell-input-delay-ps",
+ &phy->d.iocell_input_delay);
+ of_property_read_u32(dev->of_node, "marvell,iocell-output-delay-ps",
+ &phy->d.iocell_output_delay);
+ of_property_read_u32(dev->of_node, "marvell,delay-element-ps",
+ &phy->d.delay_element);
+ ret = of_property_read_u32(dev->of_node, "marvell,read-dqs-cmd-delay-ps",
+ &phy->settings.cp_read_dqs_cmd_delay);
+ if (ret)
+ phy->settings.cp_read_dqs_cmd_delay = DEFAULT_CMD_DELAY;
+
+ ret = of_property_read_u32(dev->of_node, "marvell,tune-val-start-ps",
+ &tune_val_start);
+ if (ret)
+ tune_val_start = SDHCI_CDNS_TUNE_START;
+
+ ret = of_property_read_u32(dev->of_node, "marvell,tune-val-step-ps",
+ &tune_val_step);
+ if (ret)
+ tune_val_step = SDHCI_CDNS_TUNE_STEP;
+
+ read_dqs_cmd_delay = phy->settings.cp_read_dqs_cmd_delay;
+ clk_wrdqs_delay = phy->settings.cp_clk_wrdqs_delay;
+ clk_wr_delay = phy->settings.cp_clk_wr_delay;
+ read_dqs_delay = phy->settings.cp_read_dqs_delay;
+ return 0;
+}
+
+static int sdhci_cdns_sd6_phy_init(struct sdhci_cdns_priv *priv)
+{
+ int ret;
+ u32 reg;
+ struct sdhci_cdns_sd6_phy *phy = priv->phy;
+
+ sdhci_cdns_sd6_dll_reset(priv, true);
+
+ reg = sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DQS_TIMING);
+ reg &= ~SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_EXT_LPBK_DQS;
+ reg &= ~SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_LPBK_DQS;
+ reg &= ~SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS;
+ reg &= ~SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS_CMD;
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_EXT_LPBK_DQS,
+ phy->settings.cp_use_ext_lpbk_dqs);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_LPBK_DQS,
+ phy->settings.cp_use_lpbk_dqs);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS,
+ phy->settings.cp_use_phony_dqs);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS_CMD,
+ phy->settings.cp_use_phony_dqs_cmd);
+ sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DQS_TIMING, reg);
+
+ reg = sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_GATE_LPBK);
+ reg &= ~SDHCI_CDNS_SD6_PHY_GATE_LPBK_SYNC_METHOD;
+ reg &= ~SDHCI_CDNS_SD6_PHY_GATE_LPBK_SW_HALF_CYCLE_SHIFT;
+ reg &= ~SDHCI_CDNS_SD6_PHY_GATE_LPBK_RD_DEL_SEL;
+ reg &= ~SDHCI_CDNS_SD6_PHY_GATE_LPBK_GATE_CFG_ALWAYS_ON;
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GATE_LPBK_SYNC_METHOD,
+ phy->settings.cp_sync_method);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GATE_LPBK_SW_HALF_CYCLE_SHIFT,
+ phy->settings.cp_sw_half_cycle_shift);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GATE_LPBK_RD_DEL_SEL,
+ phy->settings.cp_rd_del_sel);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GATE_LPBK_GATE_CFG_ALWAYS_ON,
+ phy->settings.cp_gate_cfg_always_on);
+ sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_GATE_LPBK, reg);
+
+ reg = 0x0;
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_MASTER_BYPASS_MODE,
+ phy->settings.cp_dll_bypass_mode);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_MASTER_PHASE_DETECT_SEL, 2);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_MASTER_DLL_LOCK_NUM, 0);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_MASTER_DLL_START_POINT,
+ phy->settings.cp_dll_start_point);
+ sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DLL_MASTER, reg);
+
+ reg = 0x0;
+ reg = FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_CMD_DELAY,
+ phy->settings.cp_read_dqs_cmd_delay);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WRDQS_DELAY,
+ phy->settings.cp_clk_wrdqs_delay);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WR_DELAY,
+ phy->settings.cp_clk_wr_delay);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_DELAY,
+ phy->settings.cp_read_dqs_delay);
+ sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DLL_SLAVE, reg);
+
+ reg = sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL);
+ reg &= ~SDHCI_CDNS_SD6_PHY_CTRL_PHONY_DQS_TIMING;
+ sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL, reg);
+
+ reg = sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_GPIO_CTRL0);
+ reg &= ~0x77;
+ reg |= SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_DRV_OVR_EN |
+ SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_SLEW_OVR_EN;
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_DRV,
+ phy->settings.drive);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_SLEW,
+ phy->settings.slew);
+ sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_GPIO_CTRL0, reg);
+
+ ret = sdhci_cdns_sd6_dll_reset(priv, false);
+ if (ret)
+ return ret;
+
+ reg = sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DQ_TIMING);
+ reg &= ~SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_ALWAYS_ON;
+ reg &= ~SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_END;
+ reg &= ~SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_START;
+ reg &= ~SDHCI_CDNS_SD6_PHY_DQ_TIMING_DATA_SELECT_OE_END;
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_ALWAYS_ON,
+ phy->settings.cp_io_mask_always_on);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_END,
+ phy->settings.cp_io_mask_end);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_START,
+ phy->settings.cp_io_mask_start);
+ reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQ_TIMING_DATA_SELECT_OE_END,
+ phy->settings.cp_data_select_oe_end);
+ sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DQ_TIMING, reg);
+
+ reg = readl(priv->hrs_addr + SDHCI_CDNS_HRS09);
+ if (phy->settings.sdhc_extended_wr_mode)
+ reg |= SDHCI_CDNS_HRS09_EXTENDED_WR_MODE;
+ else
+ reg &= ~SDHCI_CDNS_HRS09_EXTENDED_WR_MODE;
+
+ if (phy->settings.sdhc_extended_rd_mode)
+ reg |= SDHCI_CDNS_HRS09_EXTENDED_RD_MODE;
+ else
+ reg &= ~SDHCI_CDNS_HRS09_EXTENDED_RD_MODE;
+
+ if (phy->settings.sdhc_rddata_en)
+ reg |= SDHCI_CDNS_HRS09_RDDATA_EN;
+ else
+ reg &= ~SDHCI_CDNS_HRS09_RDDATA_EN;
+
+ if (phy->settings.sdhc_rdcmd_en)
+ reg |= SDHCI_CDNS_HRS09_RDCMD_EN;
+ else
+ reg &= ~SDHCI_CDNS_HRS09_RDCMD_EN;
+
+ writel(reg, priv->hrs_addr + SDHCI_CDNS_HRS09);
+
+ writel(0x30004, priv->hrs_addr + SDHCI_CDNS_HRS02);
+
+ reg = 0x0;
+ reg = FIELD_PREP(SDHCI_CDNS_HRS10_HCSDCLKADJ, phy->settings.sdhc_hcsdclkadj);
+ writel(reg, priv->hrs_addr + SDHCI_CDNS_HRS10);
+
+ if (phy->mode != MMC_TIMING_MMC_HS && phy->mode != MMC_TIMING_MMC_DDR52) {
+ reg = 0x0;
+ reg = FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA1_SDCLK_DLY,
+ phy->settings.sdhc_wrdata1_sdclk_dly);
+ reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA0_SDCLK_DLY,
+ phy->settings.sdhc_wrdata0_sdclk_dly);
+ reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD1_SDCLK_DLY,
+ phy->settings.sdhc_wrcmd1_sdclk_dly);
+ reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD0_SDCLK_DLY,
+ phy->settings.sdhc_wrcmd0_sdclk_dly);
+ reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA1_DLY,
+ phy->settings.sdhc_wrdata1_dly);
+ reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA0_DLY,
+ phy->settings.sdhc_wrdata0_dly);
+ reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD1_DLY,
+ phy->settings.sdhc_wrcmd1_dly);
+ reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD0_DLY,
+ phy->settings.sdhc_wrcmd0_dly);
+ } else {
+ reg = 0x202;
+ }
+
+ writel(reg, priv->hrs_addr + SDHCI_CDNS_HRS16);
+
+ reg = 0x0;
+ reg = FIELD_PREP(SDHCI_CDNS_HRS07_RW_COMPENSATE,
+ phy->settings.sdhc_rw_compensate);
+ reg |= FIELD_PREP(SDHCI_CDNS_HRS07_IDELAY_VAL,
+ phy->settings.sdhc_idelay_val);
+ writel(reg, priv->hrs_addr + SDHCI_CDNS_HRS07);
return 0;
}
@@ -199,6 +1113,19 @@ static void *sdhci_cdns_priv(struct sdhci_host *host)
return sdhci_pltfm_priv(pltfm_host);
}
+static int sdhci_cdns_sd6_set_tune_val(struct sdhci_host *host,
+ unsigned int val)
+{
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ struct sdhci_cdns_sd6_phy *phy = priv->phy;
+
+ phy->settings.hs200_tune_val = val;
+ phy->settings.cp_read_dqs_cmd_delay = val;
+ phy->settings.cp_read_dqs_delay = val;
+
+ return sdhci_cdns_sd6_phy_init(priv);
+}
+
static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
{
/*
@@ -208,6 +1135,11 @@ static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
return host->max_clk;
}
+static unsigned int sdhci_cdns_get_max_clock(struct sdhci_host *host)
+{
+ return SDMCLK_MAX_FREQ;
+}
+
static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
{
u32 tmp;
@@ -227,6 +1159,118 @@ static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
}
+static int sdhci_cdns_sd6_phy_update_timings(struct sdhci_host *host)
+{
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ struct sdhci_cdns_sd6_phy *phy = priv->phy;
+ int t_sdmclk = phy->t_sdmclk;
+ int mode;
+
+ mode = sdhci_cdns_sd6_get_mode(host, host->mmc->ios.timing);
+ /* initialize input */
+ init_timings[mode](&phy->t, phy->t_sdclk);
+
+ phy->mode = host->mmc->ios.timing;
+ phy->strobe_dat = false;
+
+ switch (phy->mode) {
+ case MMC_TIMING_UHS_SDR104:
+ phy->tune_cmd = true;
+ phy->tune_dat = true;
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ phy->ddr = true;
+ break;
+ case MMC_TIMING_MMC_DDR52:
+ phy->ddr = true;
+ break;
+ case MMC_TIMING_MMC_HS200:
+ phy->tune_dat = true;
+ phy->tune_cmd = true;
+ break;
+ case MMC_TIMING_MMC_HS400:
+ phy->tune_cmd = true;
+ phy->ddr = true;
+ phy->strobe_dat = true;
+ break;
+ }
+
+ if (priv->enhanced_strobe)
+ phy->strobe_cmd = true;
+
+ phy->d.phy_sdclk_delay = 2 * t_sdmclk;
+ phy->d.phy_cmd_o_delay = 2 * t_sdmclk + t_sdmclk / 2;
+ phy->d.phy_dat_o_delay = 2 * t_sdmclk + t_sdmclk / 2;
+
+ if (phy->t_sdclk == phy->t_sdmclk) {
+ phy->settings.sdhc_extended_wr_mode = 0;
+ phy->settings.sdhc_extended_rd_mode = 0;
+ } else {
+ phy->settings.sdhc_extended_wr_mode = 1;
+ phy->settings.sdhc_extended_rd_mode = 1;
+ }
+
+ phy->settings.cp_gate_cfg_always_on = 1;
+
+ sdhci_cdns_sd6_phy_configure_dll(phy);
+
+ sdhci_cdns_sd6_phy_calc_settings(phy);
+
+ return 0;
+}
+
+static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host,
+ unsigned int timing)
+{
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ u32 mode;
+
+ switch (timing) {
+ case MMC_TIMING_MMC_HS:
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
+ break;
+ case MMC_TIMING_MMC_DDR52:
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
+ break;
+ case MMC_TIMING_MMC_HS200:
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
+ break;
+ case MMC_TIMING_MMC_HS400:
+ if (priv->enhanced_strobe)
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
+ else
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
+ break;
+ case MMC_TIMING_SD_HS:
+ mode = SDHCI_CDNS_HRS06_MODE_SD;
+ break;
+ default:
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
+ break;
+ }
+
+ return mode;
+}
+
+static void sdhci_cdns_sd6_set_clock(struct sdhci_host *host,
+ unsigned int clock)
+{
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ struct sdhci_cdns_sd6_phy *phy = priv->phy;
+
+ phy->t_sdclk = DIV_ROUND_DOWN_ULL(1e12, clock);
+
+ pr_debug("%s %d %d\n", __func__, phy->mode, clock);
+
+ if (sdhci_cdns_sd6_phy_update_timings(host))
+ pr_debug("%s: update timings failed\n", __func__);
+
+ if (sdhci_cdns_sd6_phy_init(priv))
+ pr_debug("%s: phy init failed\n", __func__);
+
+ sdhci_set_clock(host, clock);
+}
+
static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,
struct sdhci_cdns_priv *priv)
{
@@ -248,6 +1292,106 @@ static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,
return 0;
}
+static int sdhci_cdns_sd6_phy_probe(struct platform_device *pdev,
+ struct sdhci_cdns_priv *priv)
+{
+ struct device *dev = &pdev->dev;
+ struct sdhci_cdns_sd6_phy *phy;
+ u32 val;
+ struct clk *clk;
+ int ret;
+ const char *mode_name;
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ clk = devm_clk_get(dev, "sdmclk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "sdmclk get error\n");
+ return PTR_ERR(clk);
+ }
+
+ val = clk_get_rate(clk);
+ phy->t_sdmclk = DIV_ROUND_DOWN_ULL(1e12, val);
+
+ ret = of_property_read_u32(dev->of_node, "cdns,host_slew",
+ &phy->settings.slew);
+ if (ret)
+ phy->settings.slew = 3;
+
+ ret = of_property_read_u32(dev->of_node, "cdns,host_drive",
+ &phy->settings.drive);
+ if (ret)
+ phy->settings.drive = 2;
+
+ ret = of_property_read_u32(dev->of_node, "cdns,iocell-input-delay",
+ &phy->d.iocell_input_delay);
+ if (ret)
+ phy->d.iocell_input_delay = 2500;
+
+ ret = of_property_read_u32(dev->of_node, "cdns,iocell-output-delay",
+ &phy->d.iocell_output_delay);
+ if (ret)
+ phy->d.iocell_output_delay = 2500;
+
+ ret = of_property_read_u32(dev->of_node, "cdns,delay-element",
+ &phy->d.delay_element);
+ if (ret)
+ phy->d.delay_element = 24;
+
+ ret = of_property_read_string_index(dev->of_node, "cdns,mode", 0,
+ &mode_name);
+ if (!ret) {
+ if (!strcmp("emmc_sdr", mode_name))
+ phy->mode = MMC_TIMING_MMC_HS;
+ else if (!strcmp("emmc_ddr", mode_name))
+ phy->mode = MMC_TIMING_MMC_DDR52;
+ else if (!strcmp("emmc_hs200", mode_name))
+ phy->mode = MMC_TIMING_MMC_HS200;
+ else if (!strcmp("emmc_hs400", mode_name))
+ phy->mode = MMC_TIMING_MMC_HS400;
+ else if (!strcmp("sd_hs", mode_name))
+ phy->mode = MMC_TIMING_SD_HS;
+ else
+ phy->mode = MMC_TIMING_MMC_HS;
+ } else {
+ phy->mode = MMC_TIMING_MMC_HS;
+ }
+
+ phy->d.delay_element_org = phy->d.delay_element;
+ phy->d.iocell_input_delay = 650;
+ phy->d.iocell_output_delay = 1800;
+
+ switch (phy->mode) {
+ case MMC_TIMING_MMC_HS:
+ phy->t_sdclk = 10000;
+ break;
+ case MMC_TIMING_MMC_DDR52:
+ phy->t_sdclk = 10000;
+ break;
+ case MMC_TIMING_MMC_HS200:
+ phy->t_sdclk = 5000;
+ break;
+ case MMC_TIMING_MMC_HS400:
+ phy->t_sdclk = 5000;
+ break;
+ case MMC_TIMING_SD_HS:
+ phy->t_sdclk = 100000;
+ break;
+ default:
+ phy->t_sdclk = 10000;
+ break;
+ }
+
+ priv->phy = phy;
+
+ sdhci_cdns_sd6_get_delay_params(dev, priv);
+
+ sdhci_cdns_sd6_calc_phy(phy);
+ return 0;
+}
+
static int sdhci_cdns_sd4_set_tune_val(struct sdhci_host *host, unsigned int val)
{
struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
@@ -281,6 +1425,57 @@ static int sdhci_cdns_sd4_set_tune_val(struct sdhci_host *host, unsigned int val
return 0;
}
+/*
+ * In SD mode, software must not use the hardware tuning and instead perform
+ * an almost identical procedure to eMMC.
+ */
+static int sdhci_cdns_sd6_execute_tuning(struct sdhci_host *host, u32 opcode)
+{
+ int cur_streak = 0;
+ int max_streak = 0;
+ int end_of_streak = 0;
+ int i, midpoint, iter = 0;
+
+ /*
+ * Do not execute tuning for UHS_SDR50 or UHS_DDR50.
+ * The delay is set by probe, based on the DT properties.
+ */
+ if (host->timing != MMC_TIMING_MMC_HS200 &&
+ host->timing != MMC_TIMING_UHS_SDR104)
+ return 0;
+
+ for (i = tune_val_start; iter < max_tune_iter; iter++, i += tune_val_step) {
+ if (sdhci_cdns_sd6_set_tune_val(host, i) ||
+ mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
+ cur_streak = 0;
+ } else { /* good */
+ cur_streak++;
+ if (cur_streak > max_streak) {
+ max_streak = cur_streak;
+ end_of_streak = i;
+ pr_debug("%s (%d-%d = %d)", __func__,
+ end_of_streak - ((cur_streak - 1) * tune_val_step),
+ end_of_streak, cur_streak);
+ } else {
+ pr_debug("%s (%d-%d)", __func__,
+ i - ((cur_streak - 1) * tune_val_step), i);
+ }
+ }
+ }
+
+ if (!max_streak) {
+ dev_err(mmc_dev(host->mmc), "no tuning point found\n");
+ return -EIO;
+ }
+
+ pr_debug("max_streak: %d-%d", end_of_streak - ((max_streak - 1) * tune_val_step),
+ end_of_streak);
+
+ midpoint = end_of_streak - (((max_streak - 1) * tune_val_step) / 2);
+
+ return sdhci_cdns_sd6_set_tune_val(host, midpoint);
+}
+
/*
* In SD mode, software must not use the hardware tuning and instead perform
* an almost identical procedure to eMMC.
@@ -343,9 +1538,12 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
else
mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
break;
- default:
+ case MMC_TIMING_SD_HS:
mode = SDHCI_CDNS_HRS06_MODE_SD;
break;
+ default:
+ mode = SDHCI_CDNS_HRS06_MODE_LEGACY;
+ break;
}
sdhci_cdns_set_emmc_mode(priv, mode);
@@ -440,6 +1638,24 @@ static int elba_drv_init(struct platform_device *pdev)
return 0;
}
+static void sdhci_cdns_sd6_set_uhs_signaling(struct sdhci_host *host,
+ unsigned int timing)
+{
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ struct sdhci_cdns_sd6_phy *phy = priv->phy;
+
+ sdhci_cdns_set_uhs_signaling(host, timing);
+
+ if ((phy->mode == -1) || (phy->t_sdclk == -1))
+ return;
+
+ if (sdhci_cdns_sd6_phy_update_timings(host))
+ pr_debug("%s: update timings failed\n", __func__);
+
+ if (sdhci_cdns_sd6_phy_init(priv))
+ pr_debug("%s: phy init failed\n", __func__);
+}
+
static const struct sdhci_ops sdhci_cdns_sd4_ops = {
.set_clock = sdhci_set_clock,
.get_timeout_clock = sdhci_cdns_get_timeout_clock,
@@ -449,6 +1665,16 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
};
+static const struct sdhci_ops sdhci_cdns_sd6_ops = {
+ .get_max_clock = sdhci_cdns_get_max_clock,
+ .set_clock = sdhci_cdns_sd6_set_clock,
+ .get_timeout_clock = sdhci_cdns_get_timeout_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .reset = sdhci_reset,
+ .platform_execute_tuning = sdhci_cdns_sd6_execute_tuning,
+ .set_uhs_signaling = sdhci_cdns_sd6_set_uhs_signaling,
+};
+
static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
.phy_init = sdhci_cdns_sd4_phy_init,
.phy_probe = sdhci_cdns_sd4_phy_probe,
@@ -475,6 +1701,14 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_sd4_drv_data = {
},
};
+static const struct sdhci_cdns_drv_data sdhci_cdns_sd6_drv_data = {
+ .phy_init = sdhci_cdns_sd6_phy_init,
+ .phy_probe = sdhci_cdns_sd6_phy_probe,
+ .pltfm_data = {
+ .ops = &sdhci_cdns_sd6_ops,
+ },
+};
+
static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
struct mmc_ios *ios)
{
@@ -518,8 +1752,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_cdns_priv *priv;
struct clk *clk;
+ bool sd6_ctrl;
int ret;
struct device *dev = &pdev->dev;
+ sd6_ctrl = of_device_is_compatible(dev->of_node, "marvell,cdns-sd6hc");
+
static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
clk = devm_clk_get(dev, NULL);
@@ -545,6 +1782,12 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
pltfm_host = sdhci_priv(host);
pltfm_host->clk = clk;
+ if (sd6_ctrl) {
+ host->clk_mul = 0;
+ host->max_clk = SDMCLK_MAX_FREQ;
+ host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
+ host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
+ }
priv = sdhci_pltfm_priv(pltfm_host);
priv->hrs_addr = host->ioaddr;
priv->enhanced_strobe = false;
@@ -559,7 +1802,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
goto free;
}
sdhci_enable_v4_mode(host);
- __sdhci_read_caps(host, &version, NULL, NULL);
+ if (sd6_ctrl)
+ __sdhci_read_caps(host, NULL, NULL, NULL);
+ else
+ __sdhci_read_caps(host, &version, NULL, NULL);
sdhci_get_of_property(pdev);
@@ -645,6 +1891,10 @@ static const struct of_device_id sdhci_cdns_match[] = {
.compatible = "cdns,sd4hc",
.data = &sdhci_cdns_sd4_drv_data,
},
+ {
+ .compatible = "marvell,cdns-sd6hc",
+ .data = &sdhci_cdns_sd6_drv_data,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v4 3/6] mmc: sdhci-cadence: SD6 controller support
2023-07-17 12:51 ` [PATCH v4 3/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
@ 2023-07-17 20:04 ` Krzysztof Kozlowski
2023-07-26 12:41 ` Adrian Hunter
1 sibling, 0 replies; 16+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-17 20:04 UTC (permalink / raw)
To: Piyush Malgujar, linux-mmc, linux-kernel, adrian.hunter,
ulf.hansson, p.zabel, robh+dt, krzysztof.kozlowski+dt, conor+dt,
yamada.masahiro, devicetree
Cc: jannadurai, cchavva, Dhananjay Kangude
On 17/07/2023 14:51, Piyush Malgujar wrote:
> From: Dhananjay Kangude <dkangude@cadence.com>
>
> Add support for SD6 controller for Marvell CN10k SoCs and related ops
> along with support for HS400 and HS400ES emmc modes.
> Updated HS200 tuning values and support to read tune configuration
> from FDT and support to configure and read host side drive strength,
> slew from device tree.
>
...
> static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
> struct mmc_ios *ios)
> {
> @@ -518,8 +1752,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> struct sdhci_pltfm_host *pltfm_host;
> struct sdhci_cdns_priv *priv;
> struct clk *clk;
> + bool sd6_ctrl;
> int ret;
> struct device *dev = &pdev->dev;
> + sd6_ctrl = of_device_is_compatible(dev->of_node, "marvell,cdns-sd6hc");
Don't sprinkle compatibles in probe. You have match data for quirks and
flags.
> +
> static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v4 3/6] mmc: sdhci-cadence: SD6 controller support
2023-07-17 12:51 ` [PATCH v4 3/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
2023-07-17 20:04 ` Krzysztof Kozlowski
@ 2023-07-26 12:41 ` Adrian Hunter
1 sibling, 0 replies; 16+ messages in thread
From: Adrian Hunter @ 2023-07-26 12:41 UTC (permalink / raw)
To: Piyush Malgujar, linux-mmc, linux-kernel, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva, Dhananjay Kangude
On 17/07/23 15:51, Piyush Malgujar wrote:
> From: Dhananjay Kangude <dkangude@cadence.com>
>
> Add support for SD6 controller for Marvell CN10k SoCs and related ops
> along with support for HS400 and HS400ES emmc modes.
> Updated HS200 tuning values and support to read tune configuration
> from FDT and support to configure and read host side drive strength,
> slew from device tree.
>
> Signed-off-by: Dhananjay Kangude <dkangude@cadence.com>
> Co-developed-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> ---
> drivers/mmc/host/sdhci-cadence.c | 1256 +++++++++++++++++++++++++++++-
> 1 file changed, 1253 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index 98fe752bcf27a71607623f3cb1c36f1a16d688a4..8bcf585185053b0afaff2625d62316cec1824fa3 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -16,8 +16,20 @@
>
> #include "sdhci-pltfm.h"
>
> +#define SDMCLK_MAX_FREQ 200000000
> +
> +#define DEFAULT_CMD_DELAY 16
> +#define SDHCI_CDNS_TUNE_START 16
> +#define SDHCI_CDNS_TUNE_STEP 6
> +#define SDHCI_CDNS_TUNE_ITERATIONS 40
> +
> +#define SDHCI_CDNS_HRS00 0x00
> +#define SDHCI_CDNS_HRS00_SWR BIT(0)
> +
> +#define SDHCI_CDNS_HRS02 0x08 /* PHY access port */
> +#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
> +
> /* SD 4.0 Controller HRS - Host Register Set (specific to Cadence) */
> -#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
> #define SDHCI_CDNS_SD4_HRS04_ACK BIT(26)
> #define SDHCI_CDNS_SD4_HRS04_RD BIT(25)
> #define SDHCI_CDNS_SD4_HRS04_WR BIT(24)
> @@ -30,12 +42,89 @@
> #define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
> #define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
> #define SDHCI_CDNS_HRS06_MODE_SD 0x0
> +#define SDHCI_CDNS_HRS06_MODE_LEGACY 0x1
The other field names have an extra 2 spaces before them, but
not this one. One way or the other, please be consistent.
> #define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
> #define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
> #define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
> #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
> #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
>
> +/* SD 6.0 Controller HRS - Host Register Set (Specific to Cadence) */
> +#define SDHCI_CDNS_SD6_HRS04_ADDR GENMASK(15, 0)
> +
> +#define SDHCI_CDNS_HRS05 0x14
> +
> +#define SDHCI_CDNS_HRS07 0x1C
> +#define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16)
> +#define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0)
There is a tab used above that expands to only 1 space (kernel expects
tabs at 8 column intervals), which might as well have been a space,
except the original style was to put 2 extra spaces before field names.
One way or the other, please be consistent.
> +
> +#define SDHCI_CDNS_HRS09 0x24
> +#define SDHCI_CDNS_HRS09_RDDATA_EN BIT(16)
> +#define SDHCI_CDNS_HRS09_RDCMD_EN BIT(15)
> +#define SDHCI_CDNS_HRS09_EXTENDED_WR_MODE BIT(3)
> +#define SDHCI_CDNS_HRS09_EXTENDED_RD_MODE BIT(2)
> +#define SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE BIT(1)
> +#define SDHCI_CDNS_HRS09_PHY_SW_RESET BIT(0)
> +
> +#define SDHCI_CDNS_HRS10 0x28
> +#define SDHCI_CDNS_HRS10_HCSDCLKADJ GENMASK(19, 16)
> +
> +#define SDHCI_CDNS_HRS11 0x2c
> +/*Reset related*/
> +#define SDHCI_CDNS_SRS11_SW_RESET_ALL BIT(24)
> +#define SDHCI_CDNS_SRS11_SW_RESET_CMD BIT(25)
> +#define SDHCI_CDNS_SRS11_SW_RESET_DAT BIT(26)
> +
> +#define SDHCI_CDNS_HRS16 0x40
> +#define SDHCI_CDNS_HRS16_WRDATA1_SDCLK_DLY GENMASK(31, 28)
> +#define SDHCI_CDNS_HRS16_WRDATA0_SDCLK_DLY GENMASK(27, 24)
> +#define SDHCI_CDNS_HRS16_WRCMD1_SDCLK_DLY GENMASK(23, 20)
> +#define SDHCI_CDNS_HRS16_WRCMD0_SDCLK_DLY GENMASK(19, 16)
> +#define SDHCI_CDNS_HRS16_WRDATA1_DLY GENMASK(15, 12)
> +#define SDHCI_CDNS_HRS16_WRDATA0_DLY GENMASK(11, 8)
> +#define SDHCI_CDNS_HRS16_WRCMD1_DLY GENMASK(7, 4)
> +#define SDHCI_CDNS_HRS16_WRCMD0_DLY GENMASK(3, 0)
> +
> +/* PHY registers for SD6 controller */
> +#define SDHCI_CDNS_SD6_PHY_DQ_TIMING 0x2000
> +#define SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_ALWAYS_ON BIT(31)
> +#define SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_END GENMASK(29, 27)
> +#define SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_START GENMASK(26, 24)
> +#define SDHCI_CDNS_SD6_PHY_DQ_TIMING_DATA_SELECT_OE_END GENMASK(2, 0)
> +
> +#define SDHCI_CDNS_SD6_PHY_DQS_TIMING 0x2004
> +#define SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_EXT_LPBK_DQS BIT(22)
> +#define SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_LPBK_DQS BIT(21)
> +#define SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS BIT(20)
> +#define SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS_CMD BIT(19)
> +
> +#define SDHCI_CDNS_SD6_PHY_GATE_LPBK 0x2008
> +#define SDHCI_CDNS_SD6_PHY_GATE_LPBK_SYNC_METHOD BIT(31)
> +#define SDHCI_CDNS_SD6_PHY_GATE_LPBK_SW_HALF_CYCLE_SHIFT BIT(28)
> +#define SDHCI_CDNS_SD6_PHY_GATE_LPBK_RD_DEL_SEL GENMASK(24, 19)
> +#define SDHCI_CDNS_SD6_PHY_GATE_LPBK_GATE_CFG_ALWAYS_ON BIT(6)
> +
> +#define SDHCI_CDNS_SD6_PHY_DLL_MASTER 0x200C
> +#define SDHCI_CDNS_SD6_PHY_DLL_MASTER_BYPASS_MODE BIT(23)
> +#define SDHCI_CDNS_SD6_PHY_DLL_MASTER_PHASE_DETECT_SEL GENMASK(22, 20)
> +#define SDHCI_CDNS_SD6_PHY_DLL_MASTER_DLL_LOCK_NUM GENMASK(18, 16)
> +#define SDHCI_CDNS_SD6_PHY_DLL_MASTER_DLL_START_POINT GENMASK(7, 0)
> +
> +#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE 0x2010
> +#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_CMD_DELAY GENMASK(31, 24)
> +#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WRDQS_DELAY GENMASK(23, 16)
> +#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WR_DELAY GENMASK(15, 8)
> +#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_DELAY GENMASK(7, 0)
> +
> +#define SDHCI_CDNS_SD6_PHY_CTRL 0x2080
> +#define SDHCI_CDNS_SD6_PHY_CTRL_PHONY_DQS_TIMING GENMASK(9, 4)
> +
> +#define SDHCI_CDNS_SD6_PHY_GPIO_CTRL0 0x2088
> +#define SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_DRV GENMASK(6, 5)
> +#define SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_DRV_OVR_EN BIT(4)
> +#define SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_SLEW GENMASK(2, 1)
> +#define SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_SLEW_OVR_EN BIT(0)
> +
> /* SRS - Slot Register Set (SDHCI-compatible) */
> #define SDHCI_CDNS_SRS_BASE 0x200
>
> @@ -60,6 +149,10 @@
> */
> #define SDHCI_CDNS_MAX_TUNING_LOOP 40
>
> +static int tune_val_start = SDHCI_CDNS_TUNE_START;
> +static int tune_val_step = SDHCI_CDNS_TUNE_STEP;
These 2 need to be in one of the structs, not global.
> +static int max_tune_iter = SDHCI_CDNS_TUNE_ITERATIONS;
This never changes so might as well just use SDHCI_CDNS_TUNE_ITERATIONS
instead.
> +
> struct sdhci_cdns_priv;
>
> struct sdhci_cdns_sd4_phy_param {
> @@ -108,6 +201,558 @@ static const struct sdhci_cdns_sd4_phy_cfg sdhci_cdns_sd4_phy_cfgs[] = {
> { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
> };
>
> +enum sdhci_cdns_sd6_phy_lock_mode {
> + SDHCI_CDNS_SD6_PHY_LOCK_MODE_FULL_CLK = 0,
> + SDHCI_CDNS_SD6_PHY_LOCK_MODE_HALF_CLK = 2,
> + SDHCI_CDNS_SD6_PHY_LOCK_MODE_SATURATION = 3,
> +};
> +
> +struct sdhci_cdns_sd6_phy_timings {
> + u32 t_cmd_output_min;
> + u32 t_cmd_output_max;
> + u32 t_dat_output_min;
> + u32 t_dat_output_max;
> + u32 t_cmd_input_min;
> + u32 t_cmd_input_max;
> + u32 t_dat_input_min;
> + u32 t_dat_input_max;
> + u32 t_sdclk_min;
> + u32 t_sdclk_max;
> +};
> +
> +struct sdhci_cdns_sd6_phy_delays {
> + u32 phy_sdclk_delay;
> + u32 phy_cmd_o_delay;
> + u32 phy_dat_o_delay;
> + u32 iocell_input_delay;
> + u32 iocell_output_delay;
> + u32 delay_element_org;
> + u32 delay_element;
> +};
> +
> +struct sdhci_cdns_sd6_phy_settings {
> + /* SDHCI_CDNS_SD6_PHY_DLL_SLAVE */
> + u32 cp_read_dqs_cmd_delay;
> + u32 cp_read_dqs_delay;
> + u32 cp_clk_wr_delay;
> + u32 cp_clk_wrdqs_delay;
> +
> + /* SDHCI_CDNS_SD6_PHY_DLL_MASTER */
> + u32 cp_dll_bypass_mode;
> + u32 cp_dll_start_point;
> +
> + /* SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 */
> + u32 cp_dll_locked_mode;
> +
> + /* SDHCI_CDNS_SD6_PHY_GATE_LPBK */
> + u32 cp_gate_cfg_always_on;
> + u32 cp_sync_method;
> + u32 cp_rd_del_sel;
> + u32 cp_sw_half_cycle_shift;
> + u32 cp_underrun_suppress;
cp_underrun_suppress is not used. Please leave out anything
that is not used.
> +
> + /* SDHCI_CDNS_SD6_PHY_DQ_TIMING */
> + u32 cp_io_mask_always_on;
> + u32 cp_io_mask_end;
> + u32 cp_io_mask_start;
> + u32 cp_data_select_oe_end;
> +
> + /* SDHCI_CDNS_SD6_PHY_DQS_TIMING */
> + u32 cp_use_ext_lpbk_dqs;
> + u32 cp_use_lpbk_dqs;
> + u8 cp_use_phony_dqs;
> + u8 cp_use_phony_dqs_cmd;
> +
> + /* HRS 09 */
> + u8 sdhc_extended_rd_mode;
> + u8 sdhc_extended_wr_mode;
> + u32 sdhc_rdcmd_en;
> + u32 sdhc_rddata_en;
> +
> + /* HRS10 */
> + u32 sdhc_hcsdclkadj;
> +
> + /* HRS 07 */
> + u32 sdhc_idelay_val;
> + u32 sdhc_rw_compensate;
> +
> + /* SRS 11 */
> + u32 sdhc_sdcfsh;
> + u32 sdhc_sdcfsl;
> +
> + /* HRS 16 */
> + u32 sdhc_wrcmd0_dly;
> + u32 sdhc_wrcmd0_sdclk_dly;
> + u32 sdhc_wrcmd1_dly;
> + u32 sdhc_wrcmd1_sdclk_dly;
> + u32 sdhc_wrdata0_dly;
> + u32 sdhc_wrdata0_sdclk_dly;
> + u32 sdhc_wrdata1_dly;
> + u32 sdhc_wrdata1_sdclk_dly;
> +
> + u32 hs200_tune_val;
> + u32 drive;
> + u32 slew;
> +};
> +
> +struct sdhci_cdns_sd6_phy_intermediate_results {
> + u32 t_sdmclk_calc;
> + u32 dll_max_value;
> +};
> +
> +struct sdhci_cdns_sd6_phy {
> + struct sdhci_cdns_sd6_phy_timings t;
> + struct sdhci_cdns_sd6_phy_delays d;
Kernel style is not to have nested structures i.e.
just put all the members of struct sdhci_cdns_sd6_phy_delays
in struct sdhci_cdns_sd6_phy.
> + u32 t_sdmclk;
> + struct sdhci_cdns_sd6_phy_settings settings;
Kernel style is not to have nested structures i.e.
just put all the members of struct sdhci_cdns_sd6_phy_settings
in struct sdhci_cdns_sd6_phy.
> + struct sdhci_cdns_sd6_phy_intermediate_results vars;
Kernel style is not to have nested structures i.e.
just put all the members of struct sdhci_cdns_sd6_phy_intermediate_results
in struct sdhci_cdns_sd6_phy.
> + bool ddr;
> + bool tune_cmd;
> + bool tune_dat;
> + bool strobe_cmd;
> + bool strobe_dat;
> + int mode;
> + int t_sdclk;
> +};
> +
> +static void init_hs(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 2000, .t_cmd_output_max = t_sdclk - 6000,
> + .t_dat_output_min = 2000, .t_dat_output_max = t_sdclk - 6000,
> + .t_cmd_input_min = 14000, .t_cmd_input_max = t_sdclk + 2500,
> + .t_dat_input_min = 14000, .t_dat_input_max = t_sdclk + 2500,
> + .t_sdclk_min = 1000000 / 50, .t_sdclk_max = 1000000 / 0.4
> + };
> +}
> +
> +static void init_uhs_sdr12(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 3000,
> + .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 3000,
> + .t_cmd_input_min = 14000, .t_cmd_input_max = t_sdclk + 1500,
> + .t_dat_input_min = 14000, .t_dat_input_max = t_sdclk + 1500,
> + .t_sdclk_min = 1000000 / 25, .t_sdclk_max = 1000000 / 0.4
> + };
> +}
> +
> +static void init_uhs_sdr25(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 3000,
> + .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 3000,
> + .t_cmd_input_min = 14000, .t_cmd_input_max = t_sdclk + 1500,
> + .t_dat_input_min = 14000, .t_dat_input_max = t_sdclk + 1500,
> + .t_sdclk_min = 1000000 / 50, .t_sdclk_max = 1000000 / 0.4
> + };
> +}
> +
> +static void init_uhs_sdr50(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 3000,
> + .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 3000,
> + .t_cmd_input_min = 7500, .t_cmd_input_max = t_sdclk + 1500,
> + .t_dat_input_min = 7500, .t_dat_input_max = t_sdclk + 1500,
> + .t_sdclk_min = 1000000 / 100, .t_sdclk_max = 1000000 / 0.4
> + };
> +}
> +
> +static void init_uhs_sdr104(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 1400,
> + .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 1400,
> + .t_cmd_input_min = 1000, .t_cmd_input_max = t_sdclk + 1000,
> + .t_dat_input_min = 1000, .t_dat_input_max = t_sdclk + 1000,
> + .t_sdclk_min = 1000000 / 200, .t_sdclk_max = 1000000 / 100
> + };
> +}
> +
> +static void init_uhs_ddr50(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 3000,
> + .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 3000,
> + .t_cmd_input_min = 13700, .t_cmd_input_max = t_sdclk + 1500,
> + .t_dat_input_min = 7000, .t_dat_input_max = t_sdclk + 1500,
> + .t_sdclk_min = 1000000 / 50, .t_sdclk_max = 1000000 / 0.4
> + };
> +}
> +
> +static void init_emmc_legacy(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 3000, .t_cmd_output_max = t_sdclk - 3000,
> + .t_dat_output_min = 3000, .t_dat_output_max = t_sdclk - 3000,
> + .t_cmd_input_min = 11700, .t_cmd_input_max = t_sdclk + 8300,
> + .t_dat_input_min = 11700, .t_dat_input_max = t_sdclk + 8300,
> + .t_sdclk_min = 1000000 / 25, .t_sdclk_max = 1000000 / 0.4
> + };
> +}
> +
> +static void init_emmc_sdr(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 3000, .t_cmd_output_max = t_sdclk - 3000,
> + .t_dat_output_min = 3000, .t_dat_output_max = t_sdclk - 3000,
> + .t_cmd_input_min = 13700, .t_cmd_input_max = t_sdclk + 2500,
> + .t_dat_input_min = 13700, .t_dat_input_max = t_sdclk + 2500,
> + .t_sdclk_min = 1000000 / 50, .t_sdclk_max = 1000000 / 0.4
> + };
> +}
> +
> +static void init_emmc_ddr(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 3000, .t_cmd_output_max = t_sdclk - 3000,
> + .t_dat_output_min = 2500, .t_dat_output_max = t_sdclk - 2500,
> + .t_cmd_input_min = 13700, .t_cmd_input_max = t_sdclk + 2500,
> + .t_dat_input_min = 7000, .t_dat_input_max = t_sdclk + 1500,
> + .t_sdclk_min = 1000000 / 50, .t_sdclk_max = 1000000 / 0.4
> + };
> +}
> +
> +static void init_emmc_hs200(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 1400,
> + .t_dat_output_min = 800, .t_dat_output_max = t_sdclk - 1400,
> + .t_cmd_input_min = 1000, .t_cmd_input_max = t_sdclk + 1000,
> + .t_dat_input_min = 1000, .t_dat_input_max = t_sdclk + 1000,
> + .t_sdclk_min = 1000000 / 200, .t_sdclk_max = 1000000 / 100
> + };
> +}
> +
> +/* HS400 and HS400ES */
> +static void init_emmc_hs400(struct sdhci_cdns_sd6_phy_timings *t, int t_sdclk)
> +{
> + *t = (struct sdhci_cdns_sd6_phy_timings){
> + .t_cmd_output_min = 800, .t_cmd_output_max = t_sdclk - 1400,
> + .t_dat_output_min = 400, .t_dat_output_max = t_sdclk - 400,
> + .t_cmd_input_min = 1000, .t_cmd_input_max = t_sdclk + 1000,
> + .t_dat_input_min = 1000, .t_dat_input_max = t_sdclk + 1000,
> + .t_sdclk_min = 1000000 / 200, .t_sdclk_max = 1000000 / 100
> + };
> +}
> +
> +static void (*init_timings[])(struct sdhci_cdns_sd6_phy_timings*, int) = {
> + &init_hs, &init_emmc_legacy, &init_emmc_sdr,
> + &init_emmc_ddr, &init_emmc_hs200, &init_emmc_hs400,
> + &init_uhs_sdr12, &init_uhs_sdr25, &init_uhs_sdr50,
> + &init_uhs_sdr104, &init_uhs_ddr50
> +};
Calling a function (sdhci_cdns_sd6_get_mode()) which uses a switch
statement to get the index to this array of function pointers to
call that function, begs the question: why not just call them
from the switch statement in the first place?
> +
> +static u32 read_dqs_cmd_delay, clk_wrdqs_delay, clk_wr_delay, read_dqs_delay;
These need to be in one of the structs, not global.
> +
> +static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host, unsigned int timing);
Avoid unnecessary forward declarations. Instead move the functions
as needed.
> +
> +static int sdhci_cdns_sd6_phy_lock_dll(struct sdhci_cdns_sd6_phy *phy)
> +{
> + u32 delay_element = phy->d.delay_element_org;
> + u32 delay_elements_in_sdmclk;
> + enum sdhci_cdns_sd6_phy_lock_mode mode;
> +
> + delay_elements_in_sdmclk = DIV_ROUND_UP(phy->t_sdmclk, delay_element);
> + if (delay_elements_in_sdmclk > 256) {
> + delay_element *= 2;
> + delay_elements_in_sdmclk = DIV_ROUND_UP(phy->t_sdmclk,
> + delay_element);
> +
> + if (delay_elements_in_sdmclk > 256)
> + return -1;
> +
> + mode = SDHCI_CDNS_SD6_PHY_LOCK_MODE_HALF_CLK;
> + phy->vars.dll_max_value = 127;
> + } else {
> + mode = SDHCI_CDNS_SD6_PHY_LOCK_MODE_FULL_CLK;
> + phy->vars.dll_max_value = 255;
> + }
> +
> + phy->vars.t_sdmclk_calc = delay_element * delay_elements_in_sdmclk;
> + phy->d.delay_element = delay_element;
> + phy->settings.cp_dll_locked_mode = mode;
> + phy->settings.cp_dll_bypass_mode = 0;
> +
> + return 0;
> +}
> +
> +static void sdhci_cdns_sd6_phy_dll_bypass(struct sdhci_cdns_sd6_phy *phy)
> +{
> + phy->vars.dll_max_value = 256;
> + phy->settings.cp_dll_bypass_mode = 1;
> + phy->settings.cp_dll_locked_mode =
> + SDHCI_CDNS_SD6_PHY_LOCK_MODE_SATURATION;
> +}
> +
> +static void sdhci_cdns_sd6_phy_configure_dll(struct sdhci_cdns_sd6_phy *phy)
> +{
> + if (phy->settings.sdhc_extended_wr_mode == 0) {
> + if (sdhci_cdns_sd6_phy_lock_dll(phy) == 0)
> + return;
> + }
> + sdhci_cdns_sd6_phy_dll_bypass(phy);
> +}
> +
> +static void sdhci_cdns_sd6_phy_calc_out(struct sdhci_cdns_sd6_phy *phy,
> + bool cmd_not_dat)
> +{
> + u32 wr0_dly = 0, wr1_dly = 0, output_min, output_max, phy_o_delay,
> + clk_wr_delay = 0, wr0_sdclk_dly = 0, wr1_sdclk_dly = 0;
> + bool data_ddr = phy->ddr && !cmd_not_dat;
> + int t;
> +
> + if (cmd_not_dat) {
> + output_min = phy->t.t_cmd_output_min;
> + output_max = phy->t.t_cmd_output_max;
> + phy_o_delay = phy->d.phy_cmd_o_delay;
> + } else {
> + output_min = phy->t.t_dat_output_min;
> + output_max = phy->t.t_dat_output_max;
> + phy_o_delay = phy->d.phy_dat_o_delay;
> + }
> +
> + if (data_ddr) {
> + wr0_sdclk_dly = 1;
> + wr1_sdclk_dly = 1;
> + }
> +
> + t = phy_o_delay - phy->d.phy_sdclk_delay - output_min;
> + if (t < 0 && phy->settings.sdhc_extended_wr_mode == 1) {
> + u32 n_half_cycle = DIV_ROUND_UP(-t * 2, phy->t_sdmclk);
> +
> + wr0_dly = (n_half_cycle + 1) / 2;
> + if (data_ddr)
> + wr1_dly = (n_half_cycle + 1) / 2;
> + else
> + wr1_dly = (n_half_cycle + 1) % 2 + wr0_dly - 1;
> + }
> +
> + if (phy->settings.sdhc_extended_wr_mode == 0) {
> + u32 out_hold, out_setup, out_hold_margin;
> + u32 n;
> +
> + if (!data_ddr)
> + wr0_dly = 1;
> +
> + out_setup = output_max;
> + out_hold = output_min;
> + out_hold_margin = DIV_ROUND_UP(out_setup - out_hold, 4);
> + out_hold += out_hold_margin;
> +
> + if (phy->settings.cp_dll_bypass_mode == 0)
> + n = DIV_ROUND_UP(256 * out_hold, phy->vars.t_sdmclk_calc);
> + else
> + n = DIV_ROUND_UP(out_hold, phy->d.delay_element) - 1;
> +
> + if (n <= phy->vars.dll_max_value)
> + clk_wr_delay = n;
> + else
> + clk_wr_delay = 255;
> + } else {
> + /* sdhc_extended_wr_mode = 1 - PHY IO cell work in SDR mode */
> + clk_wr_delay = 0;
> + }
> +
> + if (cmd_not_dat) {
> + phy->settings.sdhc_wrcmd0_dly = wr0_dly;
> + phy->settings.sdhc_wrcmd1_dly = wr1_dly;
> + phy->settings.cp_clk_wrdqs_delay = clk_wr_delay;
> + phy->settings.sdhc_wrcmd0_sdclk_dly = wr0_sdclk_dly;
> + phy->settings.sdhc_wrcmd1_sdclk_dly = wr1_sdclk_dly;
> + } else {
> + phy->settings.sdhc_wrdata0_dly = wr0_dly;
> + phy->settings.sdhc_wrdata1_dly = wr1_dly;
> + phy->settings.cp_clk_wr_delay = clk_wr_delay;
> + phy->settings.sdhc_wrdata0_sdclk_dly = wr0_sdclk_dly;
> + phy->settings.sdhc_wrdata1_sdclk_dly = wr1_sdclk_dly;
> + }
> +}
> +
> +static void sdhci_cdns_sd6_phy_calc_cmd_out(struct sdhci_cdns_sd6_phy *phy)
> +{
> + sdhci_cdns_sd6_phy_calc_out(phy, true);
> +}
> +
> +static void sdhci_cdns_sd6_phy_calc_cmd_in(struct sdhci_cdns_sd6_phy *phy)
> +{
> + phy->settings.cp_io_mask_end =
> + ((phy->d.iocell_output_delay + phy->d.iocell_input_delay) * 2)
> + / phy->t_sdmclk;
> +
> + if (phy->settings.cp_io_mask_end >= 8)
> + phy->settings.cp_io_mask_end = 7;
> +
> + if (phy->strobe_cmd && phy->settings.cp_io_mask_end > 0)
> + phy->settings.cp_io_mask_end--;
> +
> + if (phy->strobe_cmd) {
> + phy->settings.cp_use_phony_dqs_cmd = 0;
> + phy->settings.cp_read_dqs_cmd_delay = 64;
> + } else {
> + phy->settings.cp_use_phony_dqs_cmd = 1;
> + phy->settings.cp_read_dqs_cmd_delay = 0;
> + }
> +
> + if ((phy->mode == MMC_TIMING_MMC_HS400 && !phy->strobe_cmd) ||
> + phy->mode == MMC_TIMING_MMC_HS200)
> + phy->settings.cp_read_dqs_cmd_delay =
> + phy->settings.hs200_tune_val;
> +}
> +
> +static void sdhci_cdns_sd6_phy_calc_dat_in(struct sdhci_cdns_sd6_phy *phy)
> +{
> + u32 hcsdclkadj = 0;
> +
> + if (phy->strobe_dat) {
> + phy->settings.cp_use_phony_dqs = 0;
> + phy->settings.cp_read_dqs_delay = 64;
> + } else {
> + phy->settings.cp_use_phony_dqs = 1;
> + phy->settings.cp_read_dqs_delay = 0;
> + }
> +
> + if (phy->mode == MMC_TIMING_MMC_HS200)
> + phy->settings.cp_read_dqs_delay =
> + phy->settings.hs200_tune_val;
> +
> + if (phy->strobe_dat) {
> + /* dqs loopback input via IO cell */
> + hcsdclkadj += phy->d.iocell_input_delay;
> + /* dfi_dqs_in: mem_dqs -> clean_dqs_mod; delay of hic_dll_dqs_nand2 */
> + hcsdclkadj += phy->d.delay_element / 2;
> + /* delay line */
> + hcsdclkadj += phy->t_sdclk / 2;
> + /* PHY FIFO write pointer */
> + hcsdclkadj += phy->t_sdclk / 2 + phy->d.delay_element;
> + /* 1st synchronizer */
> + hcsdclkadj += DIV_ROUND_UP(hcsdclkadj, phy->t_sdmclk)
> + * phy->t_sdmclk - hcsdclkadj;
> + /*
> + * 2nd synchronizer + PHY FIFO read pointer + PHY rddata
> + * + PHY rddata registered, + FIFO 1st ciu_en
> + */
> + hcsdclkadj += 5 * phy->t_sdmclk;
> + /* FIFO 2st ciu_en */
> + hcsdclkadj += phy->t_sdclk;
> +
> + hcsdclkadj /= phy->t_sdclk;
> + } else {
> + u32 n;
> +
> + /* rebar PHY delay */
> + hcsdclkadj += 2 * phy->t_sdmclk;
> + /* rebar output via IO cell */
> + hcsdclkadj += phy->d.iocell_output_delay;
> + /* dqs loopback input via IO cell */
> + hcsdclkadj += phy->d.iocell_input_delay;
> + /* dfi_dqs_in: mem_dqs -> clean_dqs_mod delay of hic_dll_dqs_nand2 */
> + hcsdclkadj += phy->d.delay_element / 2;
> + /* dll: one delay element between SIGI_0 and SIGO_0 */
> + hcsdclkadj += phy->d.delay_element;
> + /* dfi_dqs_in: mem_dqs_delayed -> clk_dqs delay of hic_dll_dqs_nand2 */
> + hcsdclkadj += phy->d.delay_element / 2;
> + /* deskew DLL: clk_dqs -> clk_dqN: one delay element */
> + hcsdclkadj += phy->d.delay_element;
> +
> + if (phy->t_sdclk == phy->t_sdmclk)
> + n = (hcsdclkadj - 2 * phy->t_sdmclk) / phy->t_sdclk;
> + else
> + n = hcsdclkadj / phy->t_sdclk;
> +
> + /* phase shift within one t_sdclk clock cycle caused by rebar - lbk dqs delay */
> + hcsdclkadj = hcsdclkadj % phy->t_sdclk;
> + /* PHY FIFO write pointer */
> + hcsdclkadj += phy->t_sdclk / 2;
> + /* 1st synchronizer */
> + hcsdclkadj += DIV_ROUND_UP(hcsdclkadj, phy->t_sdmclk)
> + * phy->t_sdmclk - hcsdclkadj;
> + /*
> + * 2nd synchronizer + PHY FIFO read pointer + PHY rddata
> + * + PHY rddata registered
> + */
> + hcsdclkadj += 4 * phy->t_sdmclk;
> +
> + if ((phy->t_sdclk / phy->t_sdmclk) > 1) {
> + u32 tmp1, tmp2;
> +
> + tmp1 = hcsdclkadj;
> + tmp2 = (hcsdclkadj / phy->t_sdclk) * phy->t_sdclk
> + + phy->t_sdclk - phy->t_sdmclk;
> + if (tmp1 == tmp2)
> + tmp2 += phy->t_sdclk;
> +
> + /* FIFO aligns to clock cycle before ciu_en */
> + hcsdclkadj += tmp2 - tmp1;
> + }
> +
> + /* FIFO 1st ciu_en */
> + hcsdclkadj += phy->t_sdmclk;
> + /* FIFO 2nd ciu_en */
> + hcsdclkadj += phy->t_sdclk;
> +
> + hcsdclkadj /= phy->t_sdclk;
> +
> + hcsdclkadj += n;
> +
> + if ((phy->t_sdclk / phy->t_sdmclk) >= 2) {
> + if (phy->mode == MMC_TIMING_UHS_DDR50 ||
> + phy->mode == MMC_TIMING_MMC_DDR52)
> + hcsdclkadj -= 2;
> + else
> + hcsdclkadj -= 1;
> + } else if ((phy->t_sdclk / phy->t_sdmclk) == 1) {
> + hcsdclkadj += 2;
> + }
> +
> + if (phy->tune_dat)
> + hcsdclkadj -= 1;
> + }
> +
> + if (hcsdclkadj > 15)
> + hcsdclkadj = 15;
> +
> + phy->settings.sdhc_hcsdclkadj = hcsdclkadj;
> +}
> +
> +static void sdhci_cdns_sd6_phy_calc_dat_out(struct sdhci_cdns_sd6_phy *phy)
> +{
> + sdhci_cdns_sd6_phy_calc_out(phy, false);
> +}
> +
> +static void sdhci_cdns_sd6_phy_calc_io(struct sdhci_cdns_sd6_phy *phy)
> +{
> + u32 rw_compensate;
> +
> + rw_compensate = (phy->d.iocell_input_delay + phy->d.iocell_output_delay)
> + / phy->t_sdmclk + phy->settings.sdhc_wrdata0_dly + 5 + 3;
> +
> + phy->settings.sdhc_idelay_val = (2 * phy->d.iocell_input_delay)
> + / phy->t_sdmclk;
> +
> + phy->settings.cp_io_mask_start = 0;
> + if (phy->t_sdclk == phy->t_sdmclk && rw_compensate > 10)
> + phy->settings.cp_io_mask_start = 2 * (rw_compensate - 10);
> +
> + if (phy->mode == MMC_TIMING_UHS_SDR104)
> + phy->settings.cp_io_mask_start++;
> +
> + if (phy->t_sdclk == phy->t_sdmclk && phy->mode == MMC_TIMING_UHS_SDR50)
> + phy->settings.cp_io_mask_start++;
> +
> + phy->settings.sdhc_rw_compensate = rw_compensate;
> +}
> +
> +static void sdhci_cdns_sd6_phy_calc_settings(struct sdhci_cdns_sd6_phy *phy)
> +{
> + sdhci_cdns_sd6_phy_calc_cmd_out(phy);
> + sdhci_cdns_sd6_phy_calc_cmd_in(phy);
> + sdhci_cdns_sd6_phy_calc_dat_out(phy);
> + sdhci_cdns_sd6_phy_calc_dat_in(phy);
> + sdhci_cdns_sd6_phy_calc_io(phy);
> +}
> +
> static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
> void __iomem *reg)
> {
> @@ -188,7 +833,276 @@ static int sdhci_cdns_sd4_phy_init(struct sdhci_cdns_priv *priv)
> if (ret)
> return ret;
> }
A blank line was removed here and makes the diff look weird.
> + return 0;
> +}
>
> +static u32 sdhci_cdns_sd6_read_phy_reg(struct sdhci_cdns_priv *priv,
> + u32 addr)
> +{
> + writel(FIELD_PREP(SDHCI_CDNS_SD6_HRS04_ADDR, addr),
> + priv->hrs_addr + SDHCI_CDNS_HRS04);
> + return readl(priv->hrs_addr + SDHCI_CDNS_HRS05);
> +}
> +
> +static void sdhci_cdns_sd6_write_phy_reg(struct sdhci_cdns_priv *priv,
> + u32 addr, u32 data)
> +{
> + writel(FIELD_PREP(SDHCI_CDNS_SD6_HRS04_ADDR, addr),
> + priv->hrs_addr + SDHCI_CDNS_HRS04);
> + writel(data, priv->hrs_addr + SDHCI_CDNS_HRS05);
> +}
> +
> +static int sdhci_cdns_sd6_dll_reset(struct sdhci_cdns_priv *priv, bool reset)
> +{
> + u32 reg;
> + int ret = 0;
> +
> + reg = readl(priv->hrs_addr + SDHCI_CDNS_HRS09);
> + if (reset)
> + reg &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET;
> + else
> + reg |= SDHCI_CDNS_HRS09_PHY_SW_RESET;
> +
> + writel(reg, priv->hrs_addr + SDHCI_CDNS_HRS09);
> +
> + if (!reset)
> + ret = readl_poll_timeout(priv->hrs_addr + SDHCI_CDNS_HRS09,
> + reg,
> + (reg &
> + SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE),
> + 0, 0);
> +
> + return ret;
> +}
> +
> +static void sdhci_cdns_sd6_calc_phy(struct sdhci_cdns_sd6_phy *phy)
> +{
> + if (phy->mode == MMC_TIMING_MMC_HS) {
> + phy->settings.cp_clk_wr_delay = 0;
> + phy->settings.cp_clk_wrdqs_delay = 0;
> + phy->settings.cp_data_select_oe_end = 1;
> + phy->settings.cp_dll_bypass_mode = 1;
> + phy->settings.cp_dll_locked_mode = 3;
> + phy->settings.cp_dll_start_point = 4;
> + phy->settings.cp_gate_cfg_always_on = 1;
> + phy->settings.cp_io_mask_always_on = 0;
> + phy->settings.cp_io_mask_end = 0;
> + phy->settings.cp_io_mask_start = 0;
> + phy->settings.cp_rd_del_sel = 52;
> + phy->settings.cp_read_dqs_cmd_delay = 0;
> + phy->settings.cp_read_dqs_delay = 0;
> + phy->settings.cp_sw_half_cycle_shift = 0;
> + phy->settings.cp_sync_method = 1;
> + phy->settings.cp_underrun_suppress = 1;
> + phy->settings.cp_use_ext_lpbk_dqs = 1;
> + phy->settings.cp_use_lpbk_dqs = 1;
> + phy->settings.cp_use_phony_dqs = 1;
> + phy->settings.cp_use_phony_dqs_cmd = 1;
> + phy->settings.sdhc_extended_rd_mode = 1;
> + phy->settings.sdhc_extended_wr_mode = 1;
> + phy->settings.sdhc_hcsdclkadj = 2;
> + phy->settings.sdhc_idelay_val = 0;
> + phy->settings.sdhc_rdcmd_en = 1;
> + phy->settings.sdhc_rddata_en = 1;
> + phy->settings.sdhc_rw_compensate = 9;
> + phy->settings.sdhc_sdcfsh = 0;
> + phy->settings.sdhc_sdcfsl = 4;
> + phy->settings.sdhc_wrcmd0_dly = 1;
> + phy->settings.sdhc_wrcmd0_sdclk_dly = 0;
> + phy->settings.sdhc_wrcmd1_dly = 0;
> + phy->settings.sdhc_wrcmd1_sdclk_dly = 0;
> + phy->settings.sdhc_wrdata0_dly = 1;
> + phy->settings.sdhc_wrdata0_sdclk_dly = 0;
> + phy->settings.sdhc_wrdata1_dly = 0;
> + phy->settings.sdhc_wrdata1_sdclk_dly = 0;
> + }
> +}
> +
> +static
> +int sdhci_cdns_sd6_get_delay_params(struct device *dev,
> + struct sdhci_cdns_priv *priv)
> +{
> + struct sdhci_cdns_sd6_phy *phy = priv->phy;
> + int ret;
> +
> + of_property_read_u32(dev->of_node, "marvell,iocell-input-delay-ps",
> + &phy->d.iocell_input_delay);
> + of_property_read_u32(dev->of_node, "marvell,iocell-output-delay-ps",
> + &phy->d.iocell_output_delay);
> + of_property_read_u32(dev->of_node, "marvell,delay-element-ps",
> + &phy->d.delay_element);
> + ret = of_property_read_u32(dev->of_node, "marvell,read-dqs-cmd-delay-ps",
> + &phy->settings.cp_read_dqs_cmd_delay);
> + if (ret)
> + phy->settings.cp_read_dqs_cmd_delay = DEFAULT_CMD_DELAY;
> +
> + ret = of_property_read_u32(dev->of_node, "marvell,tune-val-start-ps",
> + &tune_val_start);
> + if (ret)
> + tune_val_start = SDHCI_CDNS_TUNE_START;
> +
> + ret = of_property_read_u32(dev->of_node, "marvell,tune-val-step-ps",
> + &tune_val_step);
> + if (ret)
> + tune_val_step = SDHCI_CDNS_TUNE_STEP;
> +
> + read_dqs_cmd_delay = phy->settings.cp_read_dqs_cmd_delay;
> + clk_wrdqs_delay = phy->settings.cp_clk_wrdqs_delay;
> + clk_wr_delay = phy->settings.cp_clk_wr_delay;
> + read_dqs_delay = phy->settings.cp_read_dqs_delay;
> + return 0;
> +}
> +
> +static int sdhci_cdns_sd6_phy_init(struct sdhci_cdns_priv *priv)
> +{
> + int ret;
> + u32 reg;
> + struct sdhci_cdns_sd6_phy *phy = priv->phy;
> +
> + sdhci_cdns_sd6_dll_reset(priv, true);
> +
> + reg = sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DQS_TIMING);
> + reg &= ~SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_EXT_LPBK_DQS;
> + reg &= ~SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_LPBK_DQS;
> + reg &= ~SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS;
> + reg &= ~SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS_CMD;
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_EXT_LPBK_DQS,
> + phy->settings.cp_use_ext_lpbk_dqs);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_LPBK_DQS,
> + phy->settings.cp_use_lpbk_dqs);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS,
> + phy->settings.cp_use_phony_dqs);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQS_TIMING_USE_PHONY_DQS_CMD,
> + phy->settings.cp_use_phony_dqs_cmd);
> + sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DQS_TIMING, reg);
> +
> + reg = sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_GATE_LPBK);
> + reg &= ~SDHCI_CDNS_SD6_PHY_GATE_LPBK_SYNC_METHOD;
> + reg &= ~SDHCI_CDNS_SD6_PHY_GATE_LPBK_SW_HALF_CYCLE_SHIFT;
> + reg &= ~SDHCI_CDNS_SD6_PHY_GATE_LPBK_RD_DEL_SEL;
> + reg &= ~SDHCI_CDNS_SD6_PHY_GATE_LPBK_GATE_CFG_ALWAYS_ON;
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GATE_LPBK_SYNC_METHOD,
> + phy->settings.cp_sync_method);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GATE_LPBK_SW_HALF_CYCLE_SHIFT,
> + phy->settings.cp_sw_half_cycle_shift);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GATE_LPBK_RD_DEL_SEL,
> + phy->settings.cp_rd_del_sel);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GATE_LPBK_GATE_CFG_ALWAYS_ON,
> + phy->settings.cp_gate_cfg_always_on);
> + sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_GATE_LPBK, reg);
> +
> + reg = 0x0;
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_MASTER_BYPASS_MODE,
> + phy->settings.cp_dll_bypass_mode);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_MASTER_PHASE_DETECT_SEL, 2);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_MASTER_DLL_LOCK_NUM, 0);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_MASTER_DLL_START_POINT,
> + phy->settings.cp_dll_start_point);
> + sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DLL_MASTER, reg);
> +
> + reg = 0x0;
> + reg = FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_CMD_DELAY,
> + phy->settings.cp_read_dqs_cmd_delay);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WRDQS_DELAY,
> + phy->settings.cp_clk_wrdqs_delay);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WR_DELAY,
> + phy->settings.cp_clk_wr_delay);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_DELAY,
> + phy->settings.cp_read_dqs_delay);
> + sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DLL_SLAVE, reg);
> +
> + reg = sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL);
> + reg &= ~SDHCI_CDNS_SD6_PHY_CTRL_PHONY_DQS_TIMING;
> + sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL, reg);
> +
> + reg = sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_GPIO_CTRL0);
> + reg &= ~0x77;
> + reg |= SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_DRV_OVR_EN |
> + SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_SLEW_OVR_EN;
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_DRV,
> + phy->settings.drive);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_GPIO_CTRL0_SLEW,
> + phy->settings.slew);
> + sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_GPIO_CTRL0, reg);
> +
> + ret = sdhci_cdns_sd6_dll_reset(priv, false);
> + if (ret)
> + return ret;
> +
> + reg = sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DQ_TIMING);
> + reg &= ~SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_ALWAYS_ON;
> + reg &= ~SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_END;
> + reg &= ~SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_START;
> + reg &= ~SDHCI_CDNS_SD6_PHY_DQ_TIMING_DATA_SELECT_OE_END;
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_ALWAYS_ON,
> + phy->settings.cp_io_mask_always_on);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_END,
> + phy->settings.cp_io_mask_end);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQ_TIMING_IO_MASK_START,
> + phy->settings.cp_io_mask_start);
> + reg |= FIELD_PREP(SDHCI_CDNS_SD6_PHY_DQ_TIMING_DATA_SELECT_OE_END,
> + phy->settings.cp_data_select_oe_end);
> + sdhci_cdns_sd6_write_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DQ_TIMING, reg);
> +
> + reg = readl(priv->hrs_addr + SDHCI_CDNS_HRS09);
> + if (phy->settings.sdhc_extended_wr_mode)
> + reg |= SDHCI_CDNS_HRS09_EXTENDED_WR_MODE;
> + else
> + reg &= ~SDHCI_CDNS_HRS09_EXTENDED_WR_MODE;
> +
> + if (phy->settings.sdhc_extended_rd_mode)
> + reg |= SDHCI_CDNS_HRS09_EXTENDED_RD_MODE;
> + else
> + reg &= ~SDHCI_CDNS_HRS09_EXTENDED_RD_MODE;
> +
> + if (phy->settings.sdhc_rddata_en)
> + reg |= SDHCI_CDNS_HRS09_RDDATA_EN;
> + else
> + reg &= ~SDHCI_CDNS_HRS09_RDDATA_EN;
> +
> + if (phy->settings.sdhc_rdcmd_en)
> + reg |= SDHCI_CDNS_HRS09_RDCMD_EN;
> + else
> + reg &= ~SDHCI_CDNS_HRS09_RDCMD_EN;
> +
> + writel(reg, priv->hrs_addr + SDHCI_CDNS_HRS09);
> +
> + writel(0x30004, priv->hrs_addr + SDHCI_CDNS_HRS02);
> +
> + reg = 0x0;
> + reg = FIELD_PREP(SDHCI_CDNS_HRS10_HCSDCLKADJ, phy->settings.sdhc_hcsdclkadj);
> + writel(reg, priv->hrs_addr + SDHCI_CDNS_HRS10);
> +
> + if (phy->mode != MMC_TIMING_MMC_HS && phy->mode != MMC_TIMING_MMC_DDR52) {
> + reg = 0x0;
> + reg = FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA1_SDCLK_DLY,
> + phy->settings.sdhc_wrdata1_sdclk_dly);
> + reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA0_SDCLK_DLY,
> + phy->settings.sdhc_wrdata0_sdclk_dly);
> + reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD1_SDCLK_DLY,
> + phy->settings.sdhc_wrcmd1_sdclk_dly);
> + reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD0_SDCLK_DLY,
> + phy->settings.sdhc_wrcmd0_sdclk_dly);
> + reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA1_DLY,
> + phy->settings.sdhc_wrdata1_dly);
> + reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA0_DLY,
> + phy->settings.sdhc_wrdata0_dly);
> + reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD1_DLY,
> + phy->settings.sdhc_wrcmd1_dly);
> + reg |= FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD0_DLY,
> + phy->settings.sdhc_wrcmd0_dly);
> + } else {
> + reg = 0x202;
> + }
> +
> + writel(reg, priv->hrs_addr + SDHCI_CDNS_HRS16);
> +
> + reg = 0x0;
> + reg = FIELD_PREP(SDHCI_CDNS_HRS07_RW_COMPENSATE,
> + phy->settings.sdhc_rw_compensate);
> + reg |= FIELD_PREP(SDHCI_CDNS_HRS07_IDELAY_VAL,
> + phy->settings.sdhc_idelay_val);
> + writel(reg, priv->hrs_addr + SDHCI_CDNS_HRS07);
> return 0;
> }
>
> @@ -199,6 +1113,19 @@ static void *sdhci_cdns_priv(struct sdhci_host *host)
> return sdhci_pltfm_priv(pltfm_host);
> }
>
> +static int sdhci_cdns_sd6_set_tune_val(struct sdhci_host *host,
> + unsigned int val)
> +{
> + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> + struct sdhci_cdns_sd6_phy *phy = priv->phy;
> +
> + phy->settings.hs200_tune_val = val;
> + phy->settings.cp_read_dqs_cmd_delay = val;
> + phy->settings.cp_read_dqs_delay = val;
> +
> + return sdhci_cdns_sd6_phy_init(priv);
> +}
> +
> static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
> {
> /*
> @@ -208,6 +1135,11 @@ static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
> return host->max_clk;
> }
>
> +static unsigned int sdhci_cdns_get_max_clock(struct sdhci_host *host)
> +{
> + return SDMCLK_MAX_FREQ;
> +}
> +
> static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
> {
> u32 tmp;
> @@ -227,6 +1159,118 @@ static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
> return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
> }
>
> +static int sdhci_cdns_sd6_phy_update_timings(struct sdhci_host *host)
> +{
> + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> + struct sdhci_cdns_sd6_phy *phy = priv->phy;
> + int t_sdmclk = phy->t_sdmclk;
> + int mode;
> +
> + mode = sdhci_cdns_sd6_get_mode(host, host->mmc->ios.timing);
> + /* initialize input */
> + init_timings[mode](&phy->t, phy->t_sdclk);
> +
> + phy->mode = host->mmc->ios.timing;
> + phy->strobe_dat = false;
> +
> + switch (phy->mode) {
> + case MMC_TIMING_UHS_SDR104:
> + phy->tune_cmd = true;
> + phy->tune_dat = true;
> + break;
> + case MMC_TIMING_UHS_DDR50:
> + phy->ddr = true;
> + break;
> + case MMC_TIMING_MMC_DDR52:
> + phy->ddr = true;
> + break;
> + case MMC_TIMING_MMC_HS200:
> + phy->tune_dat = true;
> + phy->tune_cmd = true;
> + break;
> + case MMC_TIMING_MMC_HS400:
> + phy->tune_cmd = true;
> + phy->ddr = true;
> + phy->strobe_dat = true;
> + break;
> + }
> +
> + if (priv->enhanced_strobe)
> + phy->strobe_cmd = true;
> +
> + phy->d.phy_sdclk_delay = 2 * t_sdmclk;
> + phy->d.phy_cmd_o_delay = 2 * t_sdmclk + t_sdmclk / 2;
> + phy->d.phy_dat_o_delay = 2 * t_sdmclk + t_sdmclk / 2;
> +
> + if (phy->t_sdclk == phy->t_sdmclk) {
> + phy->settings.sdhc_extended_wr_mode = 0;
> + phy->settings.sdhc_extended_rd_mode = 0;
> + } else {
> + phy->settings.sdhc_extended_wr_mode = 1;
> + phy->settings.sdhc_extended_rd_mode = 1;
> + }
> +
> + phy->settings.cp_gate_cfg_always_on = 1;
> +
> + sdhci_cdns_sd6_phy_configure_dll(phy);
> +
> + sdhci_cdns_sd6_phy_calc_settings(phy);
> +
> + return 0;
> +}
> +
> +static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host,
> + unsigned int timing)
> +{
> + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> + u32 mode;
> +
> + switch (timing) {
> + case MMC_TIMING_MMC_HS:
> + mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
> + break;
> + case MMC_TIMING_MMC_DDR52:
> + mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
> + break;
> + case MMC_TIMING_MMC_HS200:
> + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
> + break;
> + case MMC_TIMING_MMC_HS400:
> + if (priv->enhanced_strobe)
> + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
> + else
> + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
> + break;
> + case MMC_TIMING_SD_HS:
> + mode = SDHCI_CDNS_HRS06_MODE_SD;
> + break;
> + default:
> + mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
> + break;
> + }
> +
> + return mode;
> +}
> +
> +static void sdhci_cdns_sd6_set_clock(struct sdhci_host *host,
> + unsigned int clock)
> +{
> + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> + struct sdhci_cdns_sd6_phy *phy = priv->phy;
> +
> + phy->t_sdclk = DIV_ROUND_DOWN_ULL(1e12, clock);
> +
> + pr_debug("%s %d %d\n", __func__, phy->mode, clock);
> +
> + if (sdhci_cdns_sd6_phy_update_timings(host))
> + pr_debug("%s: update timings failed\n", __func__);
> +
> + if (sdhci_cdns_sd6_phy_init(priv))
> + pr_debug("%s: phy init failed\n", __func__);
> +
> + sdhci_set_clock(host, clock);
> +}
> +
> static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,
> struct sdhci_cdns_priv *priv)
> {
> @@ -248,6 +1292,106 @@ static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,
> return 0;
> }
>
> +static int sdhci_cdns_sd6_phy_probe(struct platform_device *pdev,
> + struct sdhci_cdns_priv *priv)
> +{
> + struct device *dev = &pdev->dev;
> + struct sdhci_cdns_sd6_phy *phy;
> + u32 val;
> + struct clk *clk;
> + int ret;
> + const char *mode_name;
> +
> + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> + if (!phy)
> + return -ENOMEM;
> +
> + clk = devm_clk_get(dev, "sdmclk");
> + if (IS_ERR(clk)) {
> + dev_err(dev, "sdmclk get error\n");
> + return PTR_ERR(clk);
> + }
> +
> + val = clk_get_rate(clk);
> + phy->t_sdmclk = DIV_ROUND_DOWN_ULL(1e12, val);
> +
> + ret = of_property_read_u32(dev->of_node, "cdns,host_slew",
> + &phy->settings.slew);
> + if (ret)
> + phy->settings.slew = 3;
> +
> + ret = of_property_read_u32(dev->of_node, "cdns,host_drive",
> + &phy->settings.drive);
> + if (ret)
> + phy->settings.drive = 2;
> +
> + ret = of_property_read_u32(dev->of_node, "cdns,iocell-input-delay",
> + &phy->d.iocell_input_delay);
> + if (ret)
> + phy->d.iocell_input_delay = 2500;
> +
> + ret = of_property_read_u32(dev->of_node, "cdns,iocell-output-delay",
> + &phy->d.iocell_output_delay);
> + if (ret)
> + phy->d.iocell_output_delay = 2500;
> +
> + ret = of_property_read_u32(dev->of_node, "cdns,delay-element",
> + &phy->d.delay_element);
> + if (ret)
> + phy->d.delay_element = 24;
> +
> + ret = of_property_read_string_index(dev->of_node, "cdns,mode", 0,
> + &mode_name);
> + if (!ret) {
> + if (!strcmp("emmc_sdr", mode_name))
> + phy->mode = MMC_TIMING_MMC_HS;
> + else if (!strcmp("emmc_ddr", mode_name))
> + phy->mode = MMC_TIMING_MMC_DDR52;
> + else if (!strcmp("emmc_hs200", mode_name))
> + phy->mode = MMC_TIMING_MMC_HS200;
> + else if (!strcmp("emmc_hs400", mode_name))
> + phy->mode = MMC_TIMING_MMC_HS400;
> + else if (!strcmp("sd_hs", mode_name))
> + phy->mode = MMC_TIMING_SD_HS;
> + else
> + phy->mode = MMC_TIMING_MMC_HS;
> + } else {
> + phy->mode = MMC_TIMING_MMC_HS;
> + }
> +
> + phy->d.delay_element_org = phy->d.delay_element;
> + phy->d.iocell_input_delay = 650;
> + phy->d.iocell_output_delay = 1800;
> +
> + switch (phy->mode) {
> + case MMC_TIMING_MMC_HS:
> + phy->t_sdclk = 10000;
> + break;
> + case MMC_TIMING_MMC_DDR52:
> + phy->t_sdclk = 10000;
> + break;
> + case MMC_TIMING_MMC_HS200:
> + phy->t_sdclk = 5000;
> + break;
> + case MMC_TIMING_MMC_HS400:
> + phy->t_sdclk = 5000;
> + break;
> + case MMC_TIMING_SD_HS:
> + phy->t_sdclk = 100000;
> + break;
> + default:
> + phy->t_sdclk = 10000;
> + break;
> + }
> +
> + priv->phy = phy;
> +
> + sdhci_cdns_sd6_get_delay_params(dev, priv);
> +
> + sdhci_cdns_sd6_calc_phy(phy);
> + return 0;
> +}
> +
> static int sdhci_cdns_sd4_set_tune_val(struct sdhci_host *host, unsigned int val)
> {
> struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> @@ -281,6 +1425,57 @@ static int sdhci_cdns_sd4_set_tune_val(struct sdhci_host *host, unsigned int val
> return 0;
> }
>
> +/*
> + * In SD mode, software must not use the hardware tuning and instead perform
> + * an almost identical procedure to eMMC.
> + */
> +static int sdhci_cdns_sd6_execute_tuning(struct sdhci_host *host, u32 opcode)
> +{
> + int cur_streak = 0;
> + int max_streak = 0;
> + int end_of_streak = 0;
> + int i, midpoint, iter = 0;
> +
> + /*
> + * Do not execute tuning for UHS_SDR50 or UHS_DDR50.
> + * The delay is set by probe, based on the DT properties.
> + */
> + if (host->timing != MMC_TIMING_MMC_HS200 &&
> + host->timing != MMC_TIMING_UHS_SDR104)
> + return 0;
> +
> + for (i = tune_val_start; iter < max_tune_iter; iter++, i += tune_val_step) {
> + if (sdhci_cdns_sd6_set_tune_val(host, i) ||
> + mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
> + cur_streak = 0;
> + } else { /* good */
> + cur_streak++;
> + if (cur_streak > max_streak) {
> + max_streak = cur_streak;
> + end_of_streak = i;
> + pr_debug("%s (%d-%d = %d)", __func__,
> + end_of_streak - ((cur_streak - 1) * tune_val_step),
> + end_of_streak, cur_streak);
> + } else {
> + pr_debug("%s (%d-%d)", __func__,
> + i - ((cur_streak - 1) * tune_val_step), i);
> + }
> + }
> + }
> +
> + if (!max_streak) {
> + dev_err(mmc_dev(host->mmc), "no tuning point found\n");
> + return -EIO;
> + }
> +
> + pr_debug("max_streak: %d-%d", end_of_streak - ((max_streak - 1) * tune_val_step),
> + end_of_streak);
> +
> + midpoint = end_of_streak - (((max_streak - 1) * tune_val_step) / 2);
> +
> + return sdhci_cdns_sd6_set_tune_val(host, midpoint);
> +}
> +
> /*
> * In SD mode, software must not use the hardware tuning and instead perform
> * an almost identical procedure to eMMC.
> @@ -343,9 +1538,12 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
> else
> mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
> break;
> - default:
> + case MMC_TIMING_SD_HS:
> mode = SDHCI_CDNS_HRS06_MODE_SD;
> break;
> + default:
> + mode = SDHCI_CDNS_HRS06_MODE_LEGACY;
> + break;
This change affects all devices not just marvell,cdns-sd6hc
If it is needed, it should be a separate patch.
> }
>
> sdhci_cdns_set_emmc_mode(priv, mode);
> @@ -440,6 +1638,24 @@ static int elba_drv_init(struct platform_device *pdev)
> return 0;
> }
>
> +static void sdhci_cdns_sd6_set_uhs_signaling(struct sdhci_host *host,
> + unsigned int timing)
> +{
> + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> + struct sdhci_cdns_sd6_phy *phy = priv->phy;
> +
> + sdhci_cdns_set_uhs_signaling(host, timing);
> +
> + if ((phy->mode == -1) || (phy->t_sdclk == -1))
> + return;
> +
> + if (sdhci_cdns_sd6_phy_update_timings(host))
> + pr_debug("%s: update timings failed\n", __func__);
> +
> + if (sdhci_cdns_sd6_phy_init(priv))
> + pr_debug("%s: phy init failed\n", __func__);
> +}
> +
> static const struct sdhci_ops sdhci_cdns_sd4_ops = {
> .set_clock = sdhci_set_clock,
> .get_timeout_clock = sdhci_cdns_get_timeout_clock,
> @@ -449,6 +1665,16 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
> .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
> };
>
> +static const struct sdhci_ops sdhci_cdns_sd6_ops = {
> + .get_max_clock = sdhci_cdns_get_max_clock,
> + .set_clock = sdhci_cdns_sd6_set_clock,
> + .get_timeout_clock = sdhci_cdns_get_timeout_clock,
> + .set_bus_width = sdhci_set_bus_width,
> + .reset = sdhci_reset,
> + .platform_execute_tuning = sdhci_cdns_sd6_execute_tuning,
> + .set_uhs_signaling = sdhci_cdns_sd6_set_uhs_signaling,
> +};
> +
> static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
> .phy_init = sdhci_cdns_sd4_phy_init,
> .phy_probe = sdhci_cdns_sd4_phy_probe,
> @@ -475,6 +1701,14 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_sd4_drv_data = {
> },
> };
>
> +static const struct sdhci_cdns_drv_data sdhci_cdns_sd6_drv_data = {
> + .phy_init = sdhci_cdns_sd6_phy_init,
> + .phy_probe = sdhci_cdns_sd6_phy_probe,
> + .pltfm_data = {
> + .ops = &sdhci_cdns_sd6_ops,
> + },
> +};
> +
> static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
> struct mmc_ios *ios)
> {
> @@ -518,8 +1752,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> struct sdhci_pltfm_host *pltfm_host;
> struct sdhci_cdns_priv *priv;
> struct clk *clk;
> + bool sd6_ctrl;
> int ret;
> struct device *dev = &pdev->dev;
> + sd6_ctrl = of_device_is_compatible(dev->of_node, "marvell,cdns-sd6hc");
> +
> static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
>
> clk = devm_clk_get(dev, NULL);
> @@ -545,6 +1782,12 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> pltfm_host = sdhci_priv(host);
> pltfm_host->clk = clk;
>
> + if (sd6_ctrl) {
> + host->clk_mul = 0;
host->clk_mul is going to get overwritten, so this doesn't
do anything, but the value comes from caps.
> + host->max_clk = SDMCLK_MAX_FREQ;
host->max_clk is going to get overwritten, so this doesn't
do anything, but the value comes from caps.
> + host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
> + host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
Implement data->init() and put these there.
> + }
> priv = sdhci_pltfm_priv(pltfm_host);
> priv->hrs_addr = host->ioaddr;
> priv->enhanced_strobe = false;
> @@ -559,7 +1802,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> goto free;
> }
> sdhci_enable_v4_mode(host);
> - __sdhci_read_caps(host, &version, NULL, NULL);
> + if (sd6_ctrl)
> + __sdhci_read_caps(host, NULL, NULL, NULL);
__sdhci_read_caps() is only being used here to set the version,
otherwise probably it is not needed.
> + else
> + __sdhci_read_caps(host, &version, NULL, NULL);
Should be dealt with by data->init()
>
> sdhci_get_of_property(pdev);
>
> @@ -645,6 +1891,10 @@ static const struct of_device_id sdhci_cdns_match[] = {
> .compatible = "cdns,sd4hc",
> .data = &sdhci_cdns_sd4_drv_data,
> },
> + {
> + .compatible = "marvell,cdns-sd6hc",
> + .data = &sdhci_cdns_sd6_drv_data,
> + },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 4/6] mmc: sdhci-cadence: enable MMC_SDHCI_IO_ACCESSORS support
2023-07-17 12:51 [PATCH v4 0/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
` (2 preceding siblings ...)
2023-07-17 12:51 ` [PATCH v4 3/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
@ 2023-07-17 12:51 ` Piyush Malgujar
2023-07-26 12:42 ` Adrian Hunter
2023-07-17 12:51 ` [PATCH v4 5/6] dt-bindings: mmc: sdhci-cadence: SD6 support Piyush Malgujar
2023-07-17 12:51 ` [PATCH v4 6/6] mmc: sdhci-cadence: Add debug option for SD6 controller Piyush Malgujar
5 siblings, 1 reply; 16+ messages in thread
From: Piyush Malgujar @ 2023-07-17 12:51 UTC (permalink / raw)
To: linux-mmc, linux-kernel, adrian.hunter, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva, Piyush Malgujar
From: Jayanthi Annadurai <jannadurai@marvell.com>
Add support of CONFIG_MMC_SDHCI_IO_ACCESSORS to allow Marvell
SoC ops for SD6 controller to overwrite the SDHCI IO memory
accessors.
Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
---
drivers/mmc/host/sdhci-cadence.c | 59 ++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 8bcf585185053b0afaff2625d62316cec1824fa3..f1e597219c603f3921439cedb22dcb2884abe68d 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -448,6 +448,59 @@ static u32 read_dqs_cmd_delay, clk_wrdqs_delay, clk_wr_delay, read_dqs_delay;
static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host, unsigned int timing);
+static u32 sdhci_cdns_sd6_readl(struct sdhci_host *host, int reg)
+{
+ return readl(host->ioaddr + reg);
+}
+
+static void sdhci_cdns_sd6_writel(struct sdhci_host *host, u32 val, int reg)
+{
+ writel(val, host->ioaddr + reg);
+}
+
+static u16 sdhci_cdns_sd6_readw(struct sdhci_host *host, int reg)
+{
+ u32 val, regoff;
+
+ regoff = reg & ~3;
+
+ val = readl(host->ioaddr + regoff);
+ if ((reg & 0x3) == 0)
+ return (val & 0xFFFF);
+ else
+ return ((val >> 16) & 0xFFFF);
+}
+
+static void sdhci_cdns_sd6_writew(struct sdhci_host *host, u16 val, int reg)
+{
+ writew(val, host->ioaddr + reg);
+}
+
+static u8 sdhci_cdns_sd6_readb(struct sdhci_host *host, int reg)
+{
+ u32 val, regoff;
+
+ regoff = reg & ~3;
+
+ val = readl(host->ioaddr + regoff);
+ switch (reg & 3) {
+ case 0:
+ return (val & 0xFF);
+ case 1:
+ return ((val >> 8) & 0xFF);
+ case 2:
+ return ((val >> 16) & 0xFF);
+ case 3:
+ return ((val >> 24) & 0xFF);
+ }
+ return 0;
+}
+
+static void sdhci_cdns_sd6_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+ writeb(val, host->ioaddr + reg);
+}
+
static int sdhci_cdns_sd6_phy_lock_dll(struct sdhci_cdns_sd6_phy *phy)
{
u32 delay_element = phy->d.delay_element_org;
@@ -1666,6 +1719,12 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
};
static const struct sdhci_ops sdhci_cdns_sd6_ops = {
+ .read_l = sdhci_cdns_sd6_readl,
+ .write_l = sdhci_cdns_sd6_writel,
+ .read_w = sdhci_cdns_sd6_readw,
+ .write_w = sdhci_cdns_sd6_writew,
+ .read_b = sdhci_cdns_sd6_readb,
+ .write_b = sdhci_cdns_sd6_writeb,
.get_max_clock = sdhci_cdns_get_max_clock,
.set_clock = sdhci_cdns_sd6_set_clock,
.get_timeout_clock = sdhci_cdns_get_timeout_clock,
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v4 4/6] mmc: sdhci-cadence: enable MMC_SDHCI_IO_ACCESSORS support
2023-07-17 12:51 ` [PATCH v4 4/6] mmc: sdhci-cadence: enable MMC_SDHCI_IO_ACCESSORS support Piyush Malgujar
@ 2023-07-26 12:42 ` Adrian Hunter
0 siblings, 0 replies; 16+ messages in thread
From: Adrian Hunter @ 2023-07-26 12:42 UTC (permalink / raw)
To: Piyush Malgujar, linux-mmc, linux-kernel, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva
On 17/07/23 15:51, Piyush Malgujar wrote:
> From: Jayanthi Annadurai <jannadurai@marvell.com>
>
> Add support of CONFIG_MMC_SDHCI_IO_ACCESSORS to allow Marvell
> SoC ops for SD6 controller to overwrite the SDHCI IO memory
> accessors.
>
> Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> ---
> drivers/mmc/host/sdhci-cadence.c | 59 ++++++++++++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index 8bcf585185053b0afaff2625d62316cec1824fa3..f1e597219c603f3921439cedb22dcb2884abe68d 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -448,6 +448,59 @@ static u32 read_dqs_cmd_delay, clk_wrdqs_delay, clk_wr_delay, read_dqs_delay;
>
> static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host, unsigned int timing);
>
> +static u32 sdhci_cdns_sd6_readl(struct sdhci_host *host, int reg)
> +{
> + return readl(host->ioaddr + reg);
> +}
Doesn't need to be implemented if it is the same as the
default behaviour
> +
> +static void sdhci_cdns_sd6_writel(struct sdhci_host *host, u32 val, int reg)
> +{
> + writel(val, host->ioaddr + reg);
> +}
Doesn't need to be implemented if it is the same as the
default behaviour
> +
> +static u16 sdhci_cdns_sd6_readw(struct sdhci_host *host, int reg)
> +{
> + u32 val, regoff;
> +
> + regoff = reg & ~3;
> +
> + val = readl(host->ioaddr + regoff);
> + if ((reg & 0x3) == 0)
> + return (val & 0xFFFF);
> + else
> + return ((val >> 16) & 0xFFFF);
> +}
You can use upper_16_bits() etc e.g.
static u16 sdhci_cdns_sd6_readw(struct sdhci_host *host, int reg)
{
u32 val = readl(host->ioaddr + (reg & ~3));
return reg & 0x3 ? upper_16_bits(val) : lower_16_bits(val);
}
> +
> +static void sdhci_cdns_sd6_writew(struct sdhci_host *host, u16 val, int reg)
> +{
> + writew(val, host->ioaddr + reg);
> +}
Doesn't need to be implemented if it is the same as the
default behaviour
> +
> +static u8 sdhci_cdns_sd6_readb(struct sdhci_host *host, int reg)
> +{
> + u32 val, regoff;
> +
> + regoff = reg & ~3;
> +
> + val = readl(host->ioaddr + regoff);
> + switch (reg & 3) {
> + case 0:
> + return (val & 0xFF);
> + case 1:
> + return ((val >> 8) & 0xFF);
> + case 2:
> + return ((val >> 16) & 0xFF);
> + case 3:
> + return ((val >> 24) & 0xFF);
> + }
> + return 0;
> +}
Probably could just be:
static u8 sdhci_cdns_sd6_readb(struct sdhci_host *host, int reg)
{
u32 val = readl(host->ioaddr + (reg & ~3));
return val >> (8 * (reg & 3)));
}
> +
> +static void sdhci_cdns_sd6_writeb(struct sdhci_host *host, u8 val, int reg)
> +{
> + writeb(val, host->ioaddr + reg);
> +}
Doesn't need to be implemented if it is the same as the
default behaviour
> +
> static int sdhci_cdns_sd6_phy_lock_dll(struct sdhci_cdns_sd6_phy *phy)
> {
> u32 delay_element = phy->d.delay_element_org;
> @@ -1666,6 +1719,12 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
> };
>
> static const struct sdhci_ops sdhci_cdns_sd6_ops = {
> + .read_l = sdhci_cdns_sd6_readl,
> + .write_l = sdhci_cdns_sd6_writel,
> + .read_w = sdhci_cdns_sd6_readw,
> + .write_w = sdhci_cdns_sd6_writew,
> + .read_b = sdhci_cdns_sd6_readb,
> + .write_b = sdhci_cdns_sd6_writeb,
> .get_max_clock = sdhci_cdns_get_max_clock,
> .set_clock = sdhci_cdns_sd6_set_clock,
> .get_timeout_clock = sdhci_cdns_get_timeout_clock,
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 5/6] dt-bindings: mmc: sdhci-cadence: SD6 support
2023-07-17 12:51 [PATCH v4 0/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
` (3 preceding siblings ...)
2023-07-17 12:51 ` [PATCH v4 4/6] mmc: sdhci-cadence: enable MMC_SDHCI_IO_ACCESSORS support Piyush Malgujar
@ 2023-07-17 12:51 ` Piyush Malgujar
2023-07-17 18:31 ` Conor Dooley
2023-07-17 20:06 ` Krzysztof Kozlowski
2023-07-17 12:51 ` [PATCH v4 6/6] mmc: sdhci-cadence: Add debug option for SD6 controller Piyush Malgujar
5 siblings, 2 replies; 16+ messages in thread
From: Piyush Malgujar @ 2023-07-17 12:51 UTC (permalink / raw)
To: linux-mmc, linux-kernel, adrian.hunter, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva, Piyush Malgujar
From: Jayanthi Annadurai <jannadurai@marvell.com>
Add support for SD6 controller on Marvell CN10K series SOCs. The
existing sd4hc is not compatible with the SD6 changes.
Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
---
.../devicetree/bindings/mmc/cdns,sdhci.yaml | 52 ++++++++++++++++---
1 file changed, 45 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
index 6c40611405a08717520f4ce3a78a9cb8dd9aac69..51f44c00a50505684c7c7c49c59c1ebd8d85d5d0 100644
--- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
@@ -4,19 +4,23 @@
$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
+title: Cadence SD/SDIO/eMMC Host Controller (SD4HC, SD6HC)
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
compatible:
- items:
- - enum:
- - amd,pensando-elba-sd4hc
- - microchip,mpfs-sd4hc
- - socionext,uniphier-sd4hc
- - const: cdns,sd4hc
+ oneOf:
+ - items:
+ - enum:
+ - amd,pensando-elba-sd4hc
+ - microchip,mpfs-sd4hc
+ - socionext,uniphier-sd4hc
+ - const: cdns,sd4hc
+
+ - items:
+ - const: marvell,cdns-sd6hc
reg:
minItems: 1
@@ -139,6 +143,40 @@ allOf:
reg:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: marvell,cdns-sd6hc
+
+ then:
+ properties:
+ marvell,iocell-input-delay-ps:
+ description: Delay in ps across the input IO cells
+
+ marvell,iocell-output-delay-ps:
+ description: Delay in ps across the output IO cells
+
+ marvell,delay-element-ps:
+ description: Delay element in ps used for calculating phy timings
+
+ marvell,read-dqs-cmd-delay-ps:
+ description: Command delay used in HS200 tuning
+
+ marvell,tune-val-start-ps:
+ description: Staring value of data delay used in HS200 tuning
+
+ marvell,tune-val-step-ps:
+ description: Incremental value of data delay used in HS200 tuning
+
+ required:
+ - marvell,iocell-input-delay-ps
+ - marvell,iocell-output-delay-ps
+ - marvell,delay-element-ps
+ - marvell,read-dqs-cmd-delay-ps
+ - marvell,tune-val-start-ps
+ - marvell,tune-val-step-ps
+
unevaluatedProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v4 5/6] dt-bindings: mmc: sdhci-cadence: SD6 support
2023-07-17 12:51 ` [PATCH v4 5/6] dt-bindings: mmc: sdhci-cadence: SD6 support Piyush Malgujar
@ 2023-07-17 18:31 ` Conor Dooley
2023-07-17 20:06 ` Krzysztof Kozlowski
1 sibling, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2023-07-17 18:31 UTC (permalink / raw)
To: Piyush Malgujar
Cc: linux-mmc, linux-kernel, adrian.hunter, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree, jannadurai, cchavva
[-- Attachment #1: Type: text/plain, Size: 3317 bytes --]
On Mon, Jul 17, 2023 at 05:51:45AM -0700, Piyush Malgujar wrote:
> From: Jayanthi Annadurai <jannadurai@marvell.com>
>
> Add support for SD6 controller on Marvell CN10K series SOCs. The
> existing sd4hc is not compatible with the SD6 changes.
>
> Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> ---
> .../devicetree/bindings/mmc/cdns,sdhci.yaml | 52 ++++++++++++++++---
> 1 file changed, 45 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> index 6c40611405a08717520f4ce3a78a9cb8dd9aac69..51f44c00a50505684c7c7c49c59c1ebd8d85d5d0 100644
> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> @@ -4,19 +4,23 @@
> $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
> +title: Cadence SD/SDIO/eMMC Host Controller (SD4HC, SD6HC)
>
> maintainers:
> - Masahiro Yamada <yamada.masahiro@socionext.com>
>
> properties:
> compatible:
> - items:
> - - enum:
> - - amd,pensando-elba-sd4hc
> - - microchip,mpfs-sd4hc
> - - socionext,uniphier-sd4hc
> - - const: cdns,sd4hc
> + oneOf:
> + - items:
> + - enum:
> + - amd,pensando-elba-sd4hc
> + - microchip,mpfs-sd4hc
> + - socionext,uniphier-sd4hc
> + - const: cdns,sd4hc
> +
> + - items:
> + - const: marvell,cdns-sd6hc
This seems like a strange compatible. Why have you not gone for
something like:
compatible = "marvell,$socname-sd6hc", "cdns,sd6hc";
?
>
> reg:
> minItems: 1
> @@ -139,6 +143,40 @@ allOf:
> reg:
> maxItems: 1
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: marvell,cdns-sd6hc
> +
> + then:
> + properties:
> + marvell,iocell-input-delay-ps:
> + description: Delay in ps across the input IO cells
Are all of these things marvell specific, or would other (future) sd6hc
users need these properties too?
Thanks,
Conor.
> +
> + marvell,iocell-output-delay-ps:
> + description: Delay in ps across the output IO cells
> +
> + marvell,delay-element-ps:
> + description: Delay element in ps used for calculating phy timings
> +
> + marvell,read-dqs-cmd-delay-ps:
> + description: Command delay used in HS200 tuning
> +
> + marvell,tune-val-start-ps:
> + description: Staring value of data delay used in HS200 tuning
> +
> + marvell,tune-val-step-ps:
> + description: Incremental value of data delay used in HS200 tuning
> +
> + required:
> + - marvell,iocell-input-delay-ps
> + - marvell,iocell-output-delay-ps
> + - marvell,delay-element-ps
> + - marvell,read-dqs-cmd-delay-ps
> + - marvell,tune-val-start-ps
> + - marvell,tune-val-step-ps
> +
> unevaluatedProperties: false
>
> examples:
> --
> 2.17.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 5/6] dt-bindings: mmc: sdhci-cadence: SD6 support
2023-07-17 12:51 ` [PATCH v4 5/6] dt-bindings: mmc: sdhci-cadence: SD6 support Piyush Malgujar
2023-07-17 18:31 ` Conor Dooley
@ 2023-07-17 20:06 ` Krzysztof Kozlowski
1 sibling, 0 replies; 16+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-17 20:06 UTC (permalink / raw)
To: Piyush Malgujar, linux-mmc, linux-kernel, adrian.hunter,
ulf.hansson, p.zabel, robh+dt, krzysztof.kozlowski+dt, conor+dt,
yamada.masahiro, devicetree
Cc: jannadurai, cchavva
On 17/07/2023 14:51, Piyush Malgujar wrote:
> From: Jayanthi Annadurai <jannadurai@marvell.com>
>
> Add support for SD6 controller on Marvell CN10K series SOCs. The
> existing sd4hc is not compatible with the SD6 changes.
>
> Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> ---
> .../devicetree/bindings/mmc/cdns,sdhci.yaml | 52 ++++++++++++++++---
> 1 file changed, 45 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> index 6c40611405a08717520f4ce3a78a9cb8dd9aac69..51f44c00a50505684c7c7c49c59c1ebd8d85d5d0 100644
> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> @@ -4,19 +4,23 @@
> $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
> +title: Cadence SD/SDIO/eMMC Host Controller (SD4HC, SD6HC)
>
> maintainers:
> - Masahiro Yamada <yamada.masahiro@socionext.com>
>
> properties:
> compatible:
> - items:
> - - enum:
> - - amd,pensando-elba-sd4hc
> - - microchip,mpfs-sd4hc
> - - socionext,uniphier-sd4hc
> - - const: cdns,sd4hc
> + oneOf:
> + - items:
> + - enum:
> + - amd,pensando-elba-sd4hc
> + - microchip,mpfs-sd4hc
> + - socionext,uniphier-sd4hc
> + - const: cdns,sd4hc
> +
> + - items:
> + - const: marvell,cdns-sd6hc
Except what Conor said (that's not a correct compatible, because cdns is
vendor prefix, not device name), you do not have multiple items here, so
drop "items".
>
> reg:
> minItems: 1
> @@ -139,6 +143,40 @@ allOf:
> reg:
> maxItems: 1
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: marvell,cdns-sd6hc
> +
> + then:
> + properties:
> + marvell,iocell-input-delay-ps:
> + description: Delay in ps across the input IO cells
Properties should be defined in top-level properties. Require/disallow
them per variant.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 6/6] mmc: sdhci-cadence: Add debug option for SD6 controller
2023-07-17 12:51 [PATCH v4 0/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
` (4 preceding siblings ...)
2023-07-17 12:51 ` [PATCH v4 5/6] dt-bindings: mmc: sdhci-cadence: SD6 support Piyush Malgujar
@ 2023-07-17 12:51 ` Piyush Malgujar
2023-07-18 16:10 ` kernel test robot
2023-07-26 12:42 ` Adrian Hunter
5 siblings, 2 replies; 16+ messages in thread
From: Piyush Malgujar @ 2023-07-17 12:51 UTC (permalink / raw)
To: linux-mmc, linux-kernel, adrian.hunter, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva, Piyush Malgujar
From: Jayanthi Annadurai <jannadurai@marvell.com>
Add support dumping PHY and host controller register configuration
if debug config enabled.
Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
---
drivers/mmc/host/sdhci-cadence.c | 156 ++++++++++++++++++++++++++++++-
1 file changed, 155 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index f1e597219c603f3921439cedb22dcb2884abe68d..337a97bf906137f0eac4122cdd603f25df7ae8d9 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -116,6 +116,10 @@
#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WR_DELAY GENMASK(15, 8)
#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_DELAY GENMASK(7, 0)
+#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x201C
+#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x2020
+#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x2024
+
#define SDHCI_CDNS_SD6_PHY_CTRL 0x2080
#define SDHCI_CDNS_SD6_PHY_CTRL_PHONY_DQS_TIMING GENMASK(9, 4)
@@ -813,7 +817,7 @@ static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
}
static int sdhci_cdns_sd4_write_phy_reg(struct sdhci_cdns_priv *priv,
- u8 addr, u8 data)
+ u8 addr, u8 data)
{
void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
u32 tmp;
@@ -971,6 +975,154 @@ static void sdhci_cdns_sd6_calc_phy(struct sdhci_cdns_sd6_phy *phy)
}
}
+#if defined(DEBUG) || IS_ENABLED(CONFIG_DYNAMIC_DEBUG)
+
+static
+void sdhci_cdns_sd6_phy_dump(struct sdhci_cdns_sd6_phy *phy,
+ struct sdhci_host *host)
+{
+ dev_dbg(mmc_dev(host->mmc), "PHY Timings\n");
+ dev_dbg(mmc_dev(host->mmc), "mode %d t_sdclk %d\n", phy->mode,
+ phy->t_sdclk);
+
+ dev_dbg(mmc_dev(host->mmc), "cp_clk_wr_delay %d\n",
+ phy->settings.cp_clk_wr_delay);
+ dev_dbg(mmc_dev(host->mmc), "cp_clk_wrdqs_delay %d\n",
+ phy->settings.cp_clk_wrdqs_delay);
+ dev_dbg(mmc_dev(host->mmc), "cp_data_select_oe_end %d\n",
+ phy->settings.cp_data_select_oe_end);
+ dev_dbg(mmc_dev(host->mmc), "cp_dll_bypass_mode %d\n",
+ phy->settings.cp_dll_bypass_mode);
+ dev_dbg(mmc_dev(host->mmc), "cp_dll_locked_mode %d\n",
+ phy->settings.cp_dll_locked_mode);
+ dev_dbg(mmc_dev(host->mmc), "cp_dll_start_point %d\n",
+ phy->settings.cp_dll_start_point);
+ dev_dbg(mmc_dev(host->mmc), "cp_io_mask_always_on %d\n",
+ phy->settings.cp_io_mask_always_on);
+ dev_dbg(mmc_dev(host->mmc), "cp_io_mask_end %d\n",
+ phy->settings.cp_io_mask_end);
+ dev_dbg(mmc_dev(host->mmc), "cp_io_mask_start %d\n",
+ phy->settings.cp_io_mask_start);
+ dev_dbg(mmc_dev(host->mmc), "cp_rd_del_sel %d\n",
+ phy->settings.cp_rd_del_sel);
+ dev_dbg(mmc_dev(host->mmc), "cp_read_dqs_cmd_delay %d\n",
+ phy->settings.cp_read_dqs_cmd_delay);
+ dev_dbg(mmc_dev(host->mmc), "cp_read_dqs_delay %d\n",
+ phy->settings.cp_read_dqs_delay);
+ dev_dbg(mmc_dev(host->mmc), "cp_sw_half_cycle_shift %d\n",
+ phy->settings.cp_sw_half_cycle_shift);
+ dev_dbg(mmc_dev(host->mmc), "cp_sync_method %d\n",
+ phy->settings.cp_sync_method);
+ dev_dbg(mmc_dev(host->mmc), "cp_use_ext_lpbk_dqs %d\n",
+ phy->settings.cp_use_ext_lpbk_dqs);
+ dev_dbg(mmc_dev(host->mmc), "cp_use_lpbk_dqs %d\n",
+ phy->settings.cp_use_lpbk_dqs);
+ dev_dbg(mmc_dev(host->mmc), "cp_use_phony_dqs %d\n",
+ phy->settings.cp_use_phony_dqs);
+ dev_dbg(mmc_dev(host->mmc), "cp_use_phony_dqs_cmd %d\n",
+ phy->settings.cp_use_phony_dqs_cmd);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_extended_rd_mode %d\n",
+ phy->settings.sdhc_extended_rd_mode);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_extended_wr_mode %d\n",
+ phy->settings.sdhc_extended_wr_mode);
+
+ dev_dbg(mmc_dev(host->mmc), "sdhc_hcsdclkadj %d\n",
+ phy->settings.sdhc_hcsdclkadj);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_idelay_val %d\n",
+ phy->settings.sdhc_idelay_val);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_rdcmd_en %d\n",
+ phy->settings.sdhc_rdcmd_en);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_rddata_en %d\n",
+ phy->settings.sdhc_rddata_en);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_rw_compensate %d\n",
+ phy->settings.sdhc_rw_compensate);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_sdcfsh %d\n",
+ phy->settings.sdhc_sdcfsh);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_sdcfsl %d\n",
+ phy->settings.sdhc_sdcfsl);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_wrcmd0_dly %d %d\n",
+ phy->settings.sdhc_wrcmd0_dly,
+ phy->settings.sdhc_wrcmd0_sdclk_dly);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_wrcmd1_dly %d %d\n",
+ phy->settings.sdhc_wrcmd1_dly,
+ phy->settings.sdhc_wrcmd1_sdclk_dly);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_wrdata0_dly %d %d\n",
+ phy->settings.sdhc_wrdata0_dly,
+ phy->settings.sdhc_wrdata0_sdclk_dly);
+
+ dev_dbg(mmc_dev(host->mmc), "sdhc_wrdata1_dly %d %d\n",
+ phy->settings.sdhc_wrdata1_dly,
+ phy->settings.sdhc_wrdata1_sdclk_dly);
+ dev_dbg(mmc_dev(host->mmc), "hs200_tune_val %d\n",
+ phy->settings.hs200_tune_val);
+}
+
+static
+void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv, struct sdhci_host *host)
+{
+ struct sdhci_cdns_sd6_phy *phy = priv->phy;
+ int id;
+
+ sdhci_cdns_sd6_phy_dump(phy);
+
+ dev_dbg(mmc_dev(host->mmc), "Host controller Register Dump\n");
+ for (id = 0; id < 14; id++) {
+ dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
+ readl(priv->hrs_addr + (id * 4)));
+ }
+
+ id = 29;
+ dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
+ readl(priv->hrs_addr + (id * 4)));
+ id = 30;
+ dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
+ readl(priv->hrs_addr + (id * 4)));
+
+ for (id = 0; id < 27; id++) {
+ dev_dbg(mmc_dev(host->mmc), "SRS%d 0x%x\n", id,
+ readl(priv->hrs_addr + 0x200 + (id * 4)));
+ }
+
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQS_TIMING 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DQS_TIMING));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GATE_LPBK 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_GATE_LPBK));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_MASTER 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DLL_MASTER));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_SLAVE 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DLL_SLAVE));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_CTRL 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GPIO_CTRL0 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_GPIO_CTRL0));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQ_TIMING 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DQ_TIMING));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2));
+}
+
+#else
+
+static inline void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv,
+ struct sdhci_host *host)
+{
+}
+
+#endif
+
static
int sdhci_cdns_sd6_get_delay_params(struct device *dev,
struct sdhci_cdns_priv *priv)
@@ -1322,6 +1474,8 @@ static void sdhci_cdns_sd6_set_clock(struct sdhci_host *host,
pr_debug("%s: phy init failed\n", __func__);
sdhci_set_clock(host, clock);
+
+ sdhci_cdns_sd6_dump(priv, host);
}
static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v4 6/6] mmc: sdhci-cadence: Add debug option for SD6 controller
2023-07-17 12:51 ` [PATCH v4 6/6] mmc: sdhci-cadence: Add debug option for SD6 controller Piyush Malgujar
@ 2023-07-18 16:10 ` kernel test robot
2023-07-26 12:42 ` Adrian Hunter
1 sibling, 0 replies; 16+ messages in thread
From: kernel test robot @ 2023-07-18 16:10 UTC (permalink / raw)
To: Piyush Malgujar, linux-mmc, linux-kernel, adrian.hunter,
ulf.hansson, p.zabel, robh+dt, krzysztof.kozlowski+dt, conor+dt,
yamada.masahiro, devicetree
Cc: oe-kbuild-all, jannadurai, cchavva, Piyush Malgujar
Hi Piyush,
kernel test robot noticed the following build errors:
[auto build test ERROR on ulf-hansson-mmc-mirror/next]
[also build test ERROR on robh/for-next linus/master v6.5-rc2 next-20230718]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Piyush-Malgujar/mmc-sdhci-cadence-Rename-functions-structures-to-SD4-specific/20230718-175102
base: https://git.linaro.org/people/ulf.hansson/mmc-mirror.git next
patch link: https://lore.kernel.org/r/20230717125146.16791-7-pmalgujar%40marvell.com
patch subject: [PATCH v4 6/6] mmc: sdhci-cadence: Add debug option for SD6 controller
config: csky-randconfig-r023-20230718 (https://download.01.org/0day-ci/archive/20230718/202307182343.ZsoiCcbg-lkp@intel.com/config)
compiler: csky-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230718/202307182343.ZsoiCcbg-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202307182343.ZsoiCcbg-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/mmc/host/sdhci-cadence.c: In function 'sdhci_cdns_sd6_dump':
>> drivers/mmc/host/sdhci-cadence.c:1066:9: error: too few arguments to function 'sdhci_cdns_sd6_phy_dump'
1066 | sdhci_cdns_sd6_phy_dump(phy);
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/mmc/host/sdhci-cadence.c:981:6: note: declared here
981 | void sdhci_cdns_sd6_phy_dump(struct sdhci_cdns_sd6_phy *phy,
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/mmc/host/sdhci-cadence.c: In function 'sdhci_cdns_probe':
drivers/mmc/host/sdhci-cadence.c:1973:9: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
1973 | static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
| ^~~~~~
vim +/sdhci_cdns_sd6_phy_dump +1066 drivers/mmc/host/sdhci-cadence.c
1059
1060 static
1061 void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv, struct sdhci_host *host)
1062 {
1063 struct sdhci_cdns_sd6_phy *phy = priv->phy;
1064 int id;
1065
> 1066 sdhci_cdns_sd6_phy_dump(phy);
1067
1068 dev_dbg(mmc_dev(host->mmc), "Host controller Register Dump\n");
1069 for (id = 0; id < 14; id++) {
1070 dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
1071 readl(priv->hrs_addr + (id * 4)));
1072 }
1073
1074 id = 29;
1075 dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
1076 readl(priv->hrs_addr + (id * 4)));
1077 id = 30;
1078 dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
1079 readl(priv->hrs_addr + (id * 4)));
1080
1081 for (id = 0; id < 27; id++) {
1082 dev_dbg(mmc_dev(host->mmc), "SRS%d 0x%x\n", id,
1083 readl(priv->hrs_addr + 0x200 + (id * 4)));
1084 }
1085
1086 dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQS_TIMING 0x%x\n",
1087 sdhci_cdns_sd6_read_phy_reg(priv,
1088 SDHCI_CDNS_SD6_PHY_DQS_TIMING));
1089 dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GATE_LPBK 0x%x\n",
1090 sdhci_cdns_sd6_read_phy_reg(priv,
1091 SDHCI_CDNS_SD6_PHY_GATE_LPBK));
1092 dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_MASTER 0x%x\n",
1093 sdhci_cdns_sd6_read_phy_reg(priv,
1094 SDHCI_CDNS_SD6_PHY_DLL_MASTER));
1095 dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_SLAVE 0x%x\n",
1096 sdhci_cdns_sd6_read_phy_reg(priv,
1097 SDHCI_CDNS_SD6_PHY_DLL_SLAVE));
1098 dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_CTRL 0x%x\n",
1099 sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL));
1100 dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GPIO_CTRL0 0x%x\n",
1101 sdhci_cdns_sd6_read_phy_reg(priv,
1102 SDHCI_CDNS_SD6_PHY_GPIO_CTRL0));
1103 dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQ_TIMING 0x%x\n",
1104 sdhci_cdns_sd6_read_phy_reg(priv,
1105 SDHCI_CDNS_SD6_PHY_DQ_TIMING));
1106 dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x%x\n",
1107 sdhci_cdns_sd6_read_phy_reg(priv,
1108 SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0));
1109 dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x%x\n",
1110 sdhci_cdns_sd6_read_phy_reg(priv,
1111 SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1));
1112 dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x%x\n",
1113 sdhci_cdns_sd6_read_phy_reg(priv,
1114 SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2));
1115 }
1116
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v4 6/6] mmc: sdhci-cadence: Add debug option for SD6 controller
2023-07-17 12:51 ` [PATCH v4 6/6] mmc: sdhci-cadence: Add debug option for SD6 controller Piyush Malgujar
2023-07-18 16:10 ` kernel test robot
@ 2023-07-26 12:42 ` Adrian Hunter
1 sibling, 0 replies; 16+ messages in thread
From: Adrian Hunter @ 2023-07-26 12:42 UTC (permalink / raw)
To: Piyush Malgujar, linux-mmc, linux-kernel, ulf.hansson, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, yamada.masahiro,
devicetree
Cc: jannadurai, cchavva
On 17/07/23 15:51, Piyush Malgujar wrote:
> From: Jayanthi Annadurai <jannadurai@marvell.com>
>
> Add support dumping PHY and host controller register configuration
> if debug config enabled.
>
> Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> ---
> drivers/mmc/host/sdhci-cadence.c | 156 ++++++++++++++++++++++++++++++-
> 1 file changed, 155 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index f1e597219c603f3921439cedb22dcb2884abe68d..337a97bf906137f0eac4122cdd603f25df7ae8d9 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -116,6 +116,10 @@
> #define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WR_DELAY GENMASK(15, 8)
> #define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_DELAY GENMASK(7, 0)
>
> +#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x201C
> +#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x2020
> +#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x2024
> +
> #define SDHCI_CDNS_SD6_PHY_CTRL 0x2080
> #define SDHCI_CDNS_SD6_PHY_CTRL_PHONY_DQS_TIMING GENMASK(9, 4)
>
> @@ -813,7 +817,7 @@ static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
> }
>
> static int sdhci_cdns_sd4_write_phy_reg(struct sdhci_cdns_priv *priv,
> - u8 addr, u8 data)
> + u8 addr, u8 data)
Whitespace change should be done when renaming the function.
> {
> void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
> u32 tmp;
> @@ -971,6 +975,154 @@ static void sdhci_cdns_sd6_calc_phy(struct sdhci_cdns_sd6_phy *phy)
> }
> }
>
> +#if defined(DEBUG) || IS_ENABLED(CONFIG_DYNAMIC_DEBUG)
Not sure what madness caused my comment last version, but this
is actually redundant. If the condition above is not true
then the whole thing will get optimized away anyway. i.e.
conditional compilation is not needed here.
> +
> +static
> +void sdhci_cdns_sd6_phy_dump(struct sdhci_cdns_sd6_phy *phy,
> + struct sdhci_host *host)
> +{
> + dev_dbg(mmc_dev(host->mmc), "PHY Timings\n");
> + dev_dbg(mmc_dev(host->mmc), "mode %d t_sdclk %d\n", phy->mode,
> + phy->t_sdclk);
> +
> + dev_dbg(mmc_dev(host->mmc), "cp_clk_wr_delay %d\n",
> + phy->settings.cp_clk_wr_delay);
> + dev_dbg(mmc_dev(host->mmc), "cp_clk_wrdqs_delay %d\n",
> + phy->settings.cp_clk_wrdqs_delay);
> + dev_dbg(mmc_dev(host->mmc), "cp_data_select_oe_end %d\n",
> + phy->settings.cp_data_select_oe_end);
> + dev_dbg(mmc_dev(host->mmc), "cp_dll_bypass_mode %d\n",
> + phy->settings.cp_dll_bypass_mode);
> + dev_dbg(mmc_dev(host->mmc), "cp_dll_locked_mode %d\n",
> + phy->settings.cp_dll_locked_mode);
> + dev_dbg(mmc_dev(host->mmc), "cp_dll_start_point %d\n",
> + phy->settings.cp_dll_start_point);
> + dev_dbg(mmc_dev(host->mmc), "cp_io_mask_always_on %d\n",
> + phy->settings.cp_io_mask_always_on);
> + dev_dbg(mmc_dev(host->mmc), "cp_io_mask_end %d\n",
> + phy->settings.cp_io_mask_end);
> + dev_dbg(mmc_dev(host->mmc), "cp_io_mask_start %d\n",
> + phy->settings.cp_io_mask_start);
> + dev_dbg(mmc_dev(host->mmc), "cp_rd_del_sel %d\n",
> + phy->settings.cp_rd_del_sel);
> + dev_dbg(mmc_dev(host->mmc), "cp_read_dqs_cmd_delay %d\n",
> + phy->settings.cp_read_dqs_cmd_delay);
> + dev_dbg(mmc_dev(host->mmc), "cp_read_dqs_delay %d\n",
> + phy->settings.cp_read_dqs_delay);
> + dev_dbg(mmc_dev(host->mmc), "cp_sw_half_cycle_shift %d\n",
> + phy->settings.cp_sw_half_cycle_shift);
> + dev_dbg(mmc_dev(host->mmc), "cp_sync_method %d\n",
> + phy->settings.cp_sync_method);
> + dev_dbg(mmc_dev(host->mmc), "cp_use_ext_lpbk_dqs %d\n",
> + phy->settings.cp_use_ext_lpbk_dqs);
> + dev_dbg(mmc_dev(host->mmc), "cp_use_lpbk_dqs %d\n",
> + phy->settings.cp_use_lpbk_dqs);
> + dev_dbg(mmc_dev(host->mmc), "cp_use_phony_dqs %d\n",
> + phy->settings.cp_use_phony_dqs);
> + dev_dbg(mmc_dev(host->mmc), "cp_use_phony_dqs_cmd %d\n",
> + phy->settings.cp_use_phony_dqs_cmd);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_extended_rd_mode %d\n",
> + phy->settings.sdhc_extended_rd_mode);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_extended_wr_mode %d\n",
> + phy->settings.sdhc_extended_wr_mode);
> +
> + dev_dbg(mmc_dev(host->mmc), "sdhc_hcsdclkadj %d\n",
> + phy->settings.sdhc_hcsdclkadj);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_idelay_val %d\n",
> + phy->settings.sdhc_idelay_val);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_rdcmd_en %d\n",
> + phy->settings.sdhc_rdcmd_en);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_rddata_en %d\n",
> + phy->settings.sdhc_rddata_en);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_rw_compensate %d\n",
> + phy->settings.sdhc_rw_compensate);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_sdcfsh %d\n",
> + phy->settings.sdhc_sdcfsh);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_sdcfsl %d\n",
> + phy->settings.sdhc_sdcfsl);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_wrcmd0_dly %d %d\n",
> + phy->settings.sdhc_wrcmd0_dly,
> + phy->settings.sdhc_wrcmd0_sdclk_dly);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_wrcmd1_dly %d %d\n",
> + phy->settings.sdhc_wrcmd1_dly,
> + phy->settings.sdhc_wrcmd1_sdclk_dly);
> + dev_dbg(mmc_dev(host->mmc), "sdhc_wrdata0_dly %d %d\n",
> + phy->settings.sdhc_wrdata0_dly,
> + phy->settings.sdhc_wrdata0_sdclk_dly);
> +
> + dev_dbg(mmc_dev(host->mmc), "sdhc_wrdata1_dly %d %d\n",
> + phy->settings.sdhc_wrdata1_dly,
> + phy->settings.sdhc_wrdata1_sdclk_dly);
> + dev_dbg(mmc_dev(host->mmc), "hs200_tune_val %d\n",
> + phy->settings.hs200_tune_val);
> +}
> +
> +static
> +void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv, struct sdhci_host *host)
> +{
> + struct sdhci_cdns_sd6_phy *phy = priv->phy;
> + int id;
> +
> + sdhci_cdns_sd6_phy_dump(phy);
As the robot pointed out, that should be:
sdhci_cdns_sd6_phy_dump(phy, host);
> +
> + dev_dbg(mmc_dev(host->mmc), "Host controller Register Dump\n");
> + for (id = 0; id < 14; id++) {
> + dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
> + readl(priv->hrs_addr + (id * 4)));
> + }
> +
> + id = 29;
> + dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
> + readl(priv->hrs_addr + (id * 4)));
> + id = 30;
> + dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
> + readl(priv->hrs_addr + (id * 4)));
> +
> + for (id = 0; id < 27; id++) {
> + dev_dbg(mmc_dev(host->mmc), "SRS%d 0x%x\n", id,
> + readl(priv->hrs_addr + 0x200 + (id * 4)));
> + }
> +
> + dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQS_TIMING 0x%x\n",
> + sdhci_cdns_sd6_read_phy_reg(priv,
> + SDHCI_CDNS_SD6_PHY_DQS_TIMING));
> + dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GATE_LPBK 0x%x\n",
> + sdhci_cdns_sd6_read_phy_reg(priv,
> + SDHCI_CDNS_SD6_PHY_GATE_LPBK));
> + dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_MASTER 0x%x\n",
> + sdhci_cdns_sd6_read_phy_reg(priv,
> + SDHCI_CDNS_SD6_PHY_DLL_MASTER));
> + dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_SLAVE 0x%x\n",
> + sdhci_cdns_sd6_read_phy_reg(priv,
> + SDHCI_CDNS_SD6_PHY_DLL_SLAVE));
> + dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_CTRL 0x%x\n",
> + sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL));
> + dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GPIO_CTRL0 0x%x\n",
> + sdhci_cdns_sd6_read_phy_reg(priv,
> + SDHCI_CDNS_SD6_PHY_GPIO_CTRL0));
> + dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQ_TIMING 0x%x\n",
> + sdhci_cdns_sd6_read_phy_reg(priv,
> + SDHCI_CDNS_SD6_PHY_DQ_TIMING));
> + dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x%x\n",
> + sdhci_cdns_sd6_read_phy_reg(priv,
> + SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0));
> + dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x%x\n",
> + sdhci_cdns_sd6_read_phy_reg(priv,
> + SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1));
> + dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x%x\n",
> + sdhci_cdns_sd6_read_phy_reg(priv,
> + SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2));
> +}
> +
> +#else
> +
> +static inline void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv,
> + struct sdhci_host *host)
> +{
> +}
> +
> +#endif
> +
> static
> int sdhci_cdns_sd6_get_delay_params(struct device *dev,
> struct sdhci_cdns_priv *priv)
> @@ -1322,6 +1474,8 @@ static void sdhci_cdns_sd6_set_clock(struct sdhci_host *host,
> pr_debug("%s: phy init failed\n", __func__);
>
> sdhci_set_clock(host, clock);
> +
> + sdhci_cdns_sd6_dump(priv, host);
> }
>
> static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,
^ permalink raw reply [flat|nested] 16+ messages in thread