From: claudiu beznea <claudiu.beznea@tuxon.dev>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
ulf.hansson@linaro.org, linus.walleij@linaro.org,
gregkh@linuxfoundation.org, jirislaby@kernel.org,
magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org,
prabhakar.mahadev-lad.rj@bp.renesas.com,
biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com,
arnd@arndb.de, konrad.dybcio@linaro.org,
neil.armstrong@linaro.org, nfraprado@collabora.com,
rafal@milecki.pl, wsa+renesas@sang-engineering.com,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH 09/37] clk: renesas: rzg2l: fix computation formula
Date: Tue, 26 Sep 2023 14:47:06 +0300 [thread overview]
Message-ID: <dfe64c7c-2f90-65a2-05fc-e96ec5113a60@tuxon.dev> (raw)
In-Reply-To: <CAMuHMdVNzgHqURohOgpFEaGn+6+rQTqsDomoS1u_-jn=GgmHXw@mail.gmail.com>
Hi, Geert,
On 14.09.2023 15:55, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Tue, Sep 12, 2023 at 6:52 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> According to hardware manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf)
>> the computation formula for PLL rate is as follows:
>>
>> Fout = ((m + k/65536) * Fin) / (p * 2^s)
>>
>> and k has values in range [-32768, 32767]. Dividing k by 65536 with
>> integer variables leads all the time to zero. Thus we may have slight
>> differences b/w what has been set vs. what is displayed. Thus,
>> get rid of this and decompose the formula before dividing k by 65536.
>>
>> Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Thanks for your patch!
>
>> --- a/drivers/clk/renesas/rzg2l-cpg.c
>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
>> @@ -696,18 +696,22 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
>> struct pll_clk *pll_clk = to_pll(hw);
>> struct rzg2l_cpg_priv *priv = pll_clk->priv;
>> unsigned int val1, val2;
>> - unsigned int mult = 1;
>> - unsigned int div = 1;
>> + unsigned int div;
>> + u64 rate;
>> + s16 kdiv;
>>
>> if (pll_clk->type != CLK_TYPE_SAM_PLL)
>> return parent_rate;
>>
>> val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
>> val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
>> - mult = MDIV(val1) + KDIV(val1) / 65536;
>> + kdiv = KDIV(val1);
>> div = PDIV(val1) << SDIV(val2);
>>
>> - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
>> + rate = (u64)MDIV(val1) * parent_rate;
>> + rate += ((long long)parent_rate * kdiv) / 65536;
>
> As the division is a binary shift, you can use the mul_u64_u32_shr() helper,
> and incorporate the sdiv shift at the same time:
>
> rate += mul_u64_u32_shr(parent_rate, KDIV(val1), 16 + SDIV(val2));
>
> You can save a multiplication by premultiplying mdiv by 65536:
>
> rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16)) + KDIV(val1),
> 16 + SDIV(val2));
Looking again at this: KDIV (aka DIV_K) could have negative values thus
mul_u64_u32_shr() cannot be used here.
>
>> +
>> + return DIV_ROUND_CLOSEST_ULL(rate, div);
>
> return DIV_ROUND_CLOSEST_ULL(rate, PDIV(val1));
>
>> }
>>
>> static const struct clk_ops rzg2l_cpg_pll_ops = {
>
> Gr{oetje,eeting}s,
>
> Geert
>
next prev parent reply other threads:[~2023-09-26 11:47 UTC|newest]
Thread overview: 118+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 4:51 [PATCH 00/37] Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK Claudiu
2023-09-12 4:51 ` [PATCH 01/37] dt-bindings: serial: renesas,scif: document r9a08g045 support Claudiu
2023-09-12 16:00 ` Rob Herring
2023-09-14 9:35 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 02/37] dt-bindings: soc: renesas: document Renesas RZ/G3S SoC variants Claudiu
2023-09-12 16:01 ` Rob Herring
2023-09-14 9:49 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 03/37] dt-bindings: soc: renesas: renesas,rzg2l-sysc: document RZ/G3S SoC Claudiu
2023-09-12 16:01 ` Rob Herring
2023-09-14 9:49 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 04/37] soc: renesas: identify " Claudiu
2023-09-14 9:49 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 05/37] soc: renesas: remove blank lines Claudiu
2023-09-14 9:49 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 06/37] clk: renesas: rzg2l: wait for status bit of SD mux before continuing Claudiu
2023-09-14 11:42 ` Geert Uytterhoeven
2023-09-15 5:35 ` claudiu beznea
2023-09-12 4:51 ` [PATCH 07/37] clk: renesas: rzg2l: lock around writes to mux register Claudiu
2023-09-14 12:13 ` Geert Uytterhoeven
2023-09-15 5:46 ` claudiu beznea
2023-09-12 4:51 ` [PATCH 08/37] clk: renesas: rzg2l: trust value returned by hardware Claudiu
2023-09-12 16:43 ` Sergey Shtylyov
2023-09-14 12:18 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 09/37] clk: renesas: rzg2l: fix computation formula Claudiu
2023-09-14 12:55 ` Geert Uytterhoeven
2023-09-26 11:47 ` claudiu beznea [this message]
2023-09-26 14:44 ` Geert Uytterhoeven
2023-09-27 8:00 ` Geert Uytterhoeven
2023-09-28 4:55 ` claudiu beznea
2023-09-12 4:51 ` [PATCH 10/37] clk: renesas: rzg2l: use core->name for clock name Claudiu
2023-09-14 13:04 ` Geert Uytterhoeven
2023-09-15 5:47 ` claudiu beznea
2023-09-18 8:03 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 11/37] clk: renesas: rzg2l: simplify a bit the logic in rzg2l_mod_clock_endisable() Claudiu
2023-09-14 13:06 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 12/37] clk: renesas: rzg2l: reduce the critical area Claudiu
2023-09-14 13:12 ` Geert Uytterhoeven
2023-09-15 5:51 ` claudiu beznea
2023-09-15 7:05 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 13/37] clk: renesas: rzg2l: use FIELD_GET() for PLL register fields Claudiu
2023-09-14 13:19 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 14/37] clk: renesas: rzg2l: use u32 for flag and mux_flags Claudiu
2023-09-14 13:29 ` Geert Uytterhoeven
2023-09-18 8:03 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 15/37] clk: renesas: rzg2l: add support for RZ/G3S PLL Claudiu
2023-09-14 13:58 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 16/37] clk: renesas: rzg2l: add struct clk_hw_data Claudiu
2023-09-14 15:17 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 17/37] clk: renesas: rzg2l: remove CPG_SDHI_DSEL from generic header Claudiu
2023-09-14 15:18 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 18/37] clk: renesas: rzg2l: refactor sd mux driver Claudiu
2023-09-14 15:18 ` Geert Uytterhoeven
2023-09-15 7:30 ` claudiu beznea
2023-09-15 8:06 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 19/37] clk: renesas: rzg2l: add a divider clock for RZ/G3S Claudiu
2023-09-12 4:51 ` [PATCH 20/37] dt-bindings: clock: renesas,rzg2l-cpg: document RZ/G3S SoC Claudiu
2023-09-12 16:02 ` Rob Herring
2023-09-15 11:58 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 21/37] dt-bindings: clock: add r9a08g045 CPG clocks and resets definitions Claudiu
2023-09-12 16:03 ` Rob Herring
2023-09-14 15:26 ` Geert Uytterhoeven
2023-09-15 7:24 ` Krzysztof Kozlowski
2023-09-15 7:38 ` Geert Uytterhoeven
2023-09-15 7:42 ` Krzysztof Kozlowski
2023-09-15 11:59 ` Geert Uytterhoeven
2023-09-28 4:54 ` claudiu beznea
2023-09-28 7:25 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 22/37] clk: renesas: add minimal boot support for RZ/G3S SoC Claudiu
2023-09-15 12:52 ` Geert Uytterhoeven
2023-09-18 6:20 ` claudiu beznea
2023-09-18 7:00 ` Geert Uytterhoeven
2023-09-18 7:50 ` claudiu beznea
2023-09-18 9:05 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 23/37] pinctrl: renesas: rzg2l: index all registers based on port offset Claudiu
2023-09-20 13:20 ` Geert Uytterhoeven
2023-09-20 13:43 ` Lad, Prabhakar
2023-09-12 4:51 ` [PATCH 24/37] pinctrl: renesas: rzg2l: adapt for different SD, PWPR register offsets Claudiu
2023-09-21 12:07 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 25/37] pinctrl: renesas: rzg2l: adapt function number for RZ/G3S Claudiu
2023-09-21 12:51 ` Geert Uytterhoeven
2023-09-26 9:55 ` claudiu beznea
2023-09-26 14:23 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 26/37] pinctrl: renesas: rzg2l: move ds and oi to SoC specific configuration Claudiu
2023-09-21 12:54 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 27/37] pinctrl: renesas: rzg2l: add support for different ds values on different groups Claudiu
2023-09-21 13:07 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 28/37] pinctrl: renesas: rzg2l: make struct rzg2l_pinctrl_data::dedicated_pins constant Claudiu
2023-09-21 13:08 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 29/37] dt-bindings: pinctrl: renesas: document RZ/G3S SoC Claudiu
2023-09-12 16:13 ` Rob Herring
2023-09-21 15:00 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 30/37] pinctrl: renesas: rzg2l: add support for " Claudiu
2023-09-21 14:58 ` Geert Uytterhoeven
2023-09-26 10:58 ` claudiu beznea
2023-09-26 14:29 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 31/37] dt-bindings: mmc: renesas,sdhi: Document RZ/G3S support Claudiu
2023-09-12 16:13 ` Rob Herring
2023-09-14 14:47 ` Ulf Hansson
2023-09-14 15:35 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 32/37] arm64: dts: renesas: add initial DTSI for RZ/G3S SoC Claudiu
2023-09-15 13:17 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 33/37] arm64: dts: renesas: rzg3l-smarc-som: add initial support for RZ/G3S SMARC Carrier-II SoM Claudiu
2023-09-15 14:28 ` Geert Uytterhoeven
2023-09-18 6:02 ` claudiu beznea
2023-09-12 4:51 ` [PATCH 34/37] arm64: dts: renesas: rzg3s-smarc: add initial device tree for RZ SMARC Carrier-II board Claudiu
2023-09-15 14:32 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 35/37] dt-bindings: arm: renesas: document SMARC Carrier-II EVK Claudiu
2023-09-12 16:16 ` Rob Herring
2023-09-13 5:32 ` claudiu beznea
2023-09-13 15:16 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 36/37] arm64: dts: renesas: r9a08g045s33-smarc: add initial device tree for RZ/G3S SMARC EVK board Claudiu
2023-09-21 15:02 ` Geert Uytterhoeven
2023-09-12 4:51 ` [PATCH 37/37] arm64: defconfig: enable RZ/G3S (R9A08G045) SoC Claudiu
2023-09-15 14:34 ` Geert Uytterhoeven
2023-09-12 8:55 ` [PATCH 00/37] Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK Linus Walleij
2023-09-12 9:03 ` Geert Uytterhoeven
2023-09-12 9:05 ` Linus Walleij
2023-09-13 5:40 ` claudiu beznea
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