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From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
To: Jiaxing Hu <gahing@gahingwoo.com>
Cc: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org,
	will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org,
	p.zabel@pengutronix.de, ogabbay@kernel.org,
	zhangqing@rock-chips.com, royalnet026@gmail.com,
	abel.vesa@oss.qualcomm.com, sebastian.reichel@collabora.com,
	sidong.yang@furiosa.ai, u.kleine-koenig@baylibre.com,
	diederik@cknow-tech.com, alchark@flipper.net, leonard@lausen.nl,
	jeff.hugo@oss.qualcomm.com, rfoss@kernel.org,
	dri-devel@lists.freedesktop.org,
	linux-rockchip@lists.infradead.org, iommu@lists.linux.dev,
	linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v15 11/15] accel/rocket: select the per-core clock and reset counts from match data
Date: Mon, 2 Nov 2026 09:52:32 +0800	[thread overview]
Message-ID: <e0244072-2ace-4971-b237-dfea5806f114@rock-chips.com> (raw)
In-Reply-To: <20261101082307.151957-12-gahing@gahingwoo.com>

Hi Jiaxing,

On 11/1/2026 4:23 PM, Jiaxing Hu wrote:
> The RK3576 has the same RKNN block with a different number of clocks and
> resets. Take the counts from soc_data in the match data; RK3588 keeps four
> and two. Check soc before anything is allocated, since a device bound by
> name has no match data.
> 
> Signed-off-by: Jiaxing Hu <gahing@gahingwoo.com>
> ---
>  drivers/accel/rocket/rocket_core.c |  8 ++++----
>  drivers/accel/rocket/rocket_core.h |  7 +++++++
>  drivers/accel/rocket/rocket_drv.c  | 26 +++++++++++++++++++++++---
>  3 files changed, 34 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/rocket_core.c
> index 5dd260bacbff..b202d15816a3 100644
> --- a/drivers/accel/rocket/rocket_core.c
> +++ b/drivers/accel/rocket/rocket_core.c
> @@ -23,7 +23,7 @@ int rocket_core_init(struct rocket_core *core)
>  
>  	core->resets[0].id = "srst_a";
>  	core->resets[1].id = "srst_h";
> -	err = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(core->resets),
> +	err = devm_reset_control_bulk_get_exclusive(&pdev->dev, core->soc->num_resets,
>  						    core->resets);
>  	if (err)
>  		return dev_err_probe(dev, err, "failed to get resets for core %d\n", core->index);
> @@ -32,7 +32,7 @@ int rocket_core_init(struct rocket_core *core)
>  	core->clks[1].id = "hclk";
>  	core->clks[2].id = "npu";
>  	core->clks[3].id = "pclk";
> -	err = devm_clk_bulk_get(dev, ARRAY_SIZE(core->clks), core->clks);
> +	err = devm_clk_bulk_get(dev, core->soc->num_clks, core->clks);
>  	if (err)
>  		return dev_err_probe(dev, err, "failed to get clocks for core %d\n", core->index);
>  
> @@ -109,9 +109,9 @@ void rocket_core_fini(struct rocket_core *core)
>  
>  void rocket_core_reset(struct rocket_core *core)
>  {
> -	reset_control_bulk_assert(ARRAY_SIZE(core->resets), core->resets);
> +	reset_control_bulk_assert(core->soc->num_resets, core->resets);
>  
>  	udelay(10);
>  
> -	reset_control_bulk_deassert(ARRAY_SIZE(core->resets), core->resets);
> +	reset_control_bulk_deassert(core->soc->num_resets, core->resets);
>  }
> diff --git a/drivers/accel/rocket/rocket_core.h b/drivers/accel/rocket/rocket_core.h
> index f6d7382854ca..ba74c5339b94 100644
> --- a/drivers/accel/rocket/rocket_core.h
> +++ b/drivers/accel/rocket/rocket_core.h
> @@ -27,9 +27,16 @@
>  #define rocket_core_writel(core, reg, value) \
>  	writel(value, (core)->core_iomem + (REG_CORE_##reg) - REG_CORE_S_STATUS)
>  
> +/* Per-SoC differences, selected by the of_device_id match data. */
> +struct rocket_soc_data {
> +	unsigned int num_clks;		/* clk_bulk count */
> +	unsigned int num_resets;	/* reset_bulk count */
> +};
> +
>  struct rocket_core {
>  	struct device *dev;
>  	struct rocket_device *rdev;
> +	const struct rocket_soc_data *soc;
>  	unsigned int index;
>  
>  	int irq;
> diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c
> index 5d7805c41dc3..284af027f398 100644
> --- a/drivers/accel/rocket/rocket_drv.c
> +++ b/drivers/accel/rocket/rocket_drv.c
> @@ -159,8 +159,22 @@ static const struct drm_driver rocket_drm_driver = {
>  
>  static int rocket_probe(struct platform_device *pdev)
>  {
> +	const struct rocket_soc_data *soc = of_device_get_match_data(&pdev->dev);
>  	int ret;
>  
> +	/*
> +	 * soc is dereferenced without a check by every one of its users, and
> +	 * rocket_core_init() below is the first of them. A device that bound
> +	 * by name rather than by compatible has no match data, so fail before
> +	 * anything is allocated rather than at the first dereference: the
> +	 * number of cores comes from a walk of matching DT nodes, and a device
> +	 * with no of_node was never counted by it.
> +	 */

You don't need these comments because everyone already knows that.

> +	if (!soc) {
> +		dev_err(&pdev->dev, "no match data for this device\n");
> +		return -ENODEV;
> +	}
> +
>  	if (rdev == NULL) {
>  		/* First core probing, initialize DRM device. */
>  		rdev = rocket_device_init(drm_dev, &rocket_drm_driver);
> @@ -179,6 +193,7 @@ static int rocket_probe(struct platform_device *pdev)
>  
>  	rdev->cores[core].rdev = rdev;
>  	rdev->cores[core].dev = &pdev->dev;
> +	rdev->cores[core].soc = soc;
>  	rdev->cores[core].index = core;
>  
>  	rdev->num_cores++;
> @@ -216,8 +231,13 @@ static void rocket_remove(struct platform_device *pdev)
>  	}
>  }
>  
> +static const struct rocket_soc_data rk3588_soc_data = {
> +	.num_clks = 4,
> +	.num_resets = 2,
> +};
> +
>  static const struct of_device_id dt_match[] = {
> -	{ .compatible = "rockchip,rk3588-rknn-core" },
> +	{ .compatible = "rockchip,rk3588-rknn-core", .data = &rk3588_soc_data },
>  	{}
>  };
>  MODULE_DEVICE_TABLE(of, dt_match);
> @@ -243,7 +263,7 @@ static int rocket_device_runtime_resume(struct device *dev)
>  	if (core < 0)
>  		return -ENODEV;
>  
> -	err = clk_bulk_prepare_enable(ARRAY_SIZE(rdev->cores[core].clks), rdev->cores[core].clks);
> +	err = clk_bulk_prepare_enable(rdev->cores[core].soc->num_clks, rdev->cores[core].clks);
>  	if (err) {
>  		dev_err(dev, "failed to enable (%d) clocks for core %d\n", err, core);
>  		return err;
> @@ -263,7 +283,7 @@ static int rocket_device_runtime_suspend(struct device *dev)
>  	if (!rocket_job_is_idle(&rdev->cores[core]))
>  		return -EBUSY;
>  
> -	clk_bulk_disable_unprepare(ARRAY_SIZE(rdev->cores[core].clks), rdev->cores[core].clks);
> +	clk_bulk_disable_unprepare(rdev->cores[core].soc->num_clks, rdev->cores[core].clks);
>  
>  	return 0;
>  }

-- 
Best, 
Chaoyi


  reply	other threads:[~2026-11-02  1:52 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-01  8:22 [PATCH v15 00/15] accel/rocket: RK3576 NPU (RKNN) enablement Jiaxing Hu
2026-11-01  8:22 ` [PATCH v15 01/15] accel/rocket: request the core clocks by name Jiaxing Hu
2026-11-01  8:22 ` [PATCH v15 02/15] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-11-01  8:22 ` [PATCH v15 03/15] accel/rocket: wait for a running IRQ handler before resetting a core Jiaxing Hu
2026-11-01  8:55   ` sashiko-bot
2026-11-01  8:22 ` [PATCH v15 04/15] accel/rocket: let the core suspend after a reset Jiaxing Hu
2026-11-01  8:46   ` sashiko-bot
2026-11-01  8:22 ` [PATCH v15 05/15] accel/rocket: factor the completion tail out of the IRQ handler Jiaxing Hu
2026-11-01  8:22 ` [PATCH v15 06/15] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-11-01  8:37   ` [PATCH v15 06/15] dt-bindings: npu: rockchip: add rockchip, rk3576-rknn-core sashiko-bot
2026-11-01  8:22 ` [PATCH v15 07/15] dt-bindings: power: rockchip: allow resets in a power domain node Jiaxing Hu
2026-11-01  8:23 ` [PATCH v15 08/15] dt-bindings: iommu: rockchip: describe the RK3576 NPU MMU Jiaxing Hu
2026-11-01  8:23 ` [PATCH v15 09/15] pmdomain: rockchip: add optional per-domain power-on settle delay Jiaxing Hu
2026-11-01  8:47   ` sashiko-bot
2026-11-01  8:23 ` [PATCH v15 10/15] pmdomain: rockchip: cycle an optional power-domain reset on power-on Jiaxing Hu
2026-11-01  8:23 ` [PATCH v15 11/15] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-11-02  1:52   ` Chaoyi Chen [this message]
2026-11-01  8:23 ` [PATCH v15 12/15] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-11-01  8:23 ` [PATCH v15 13/15] arm64: dts: rockchip: add NPU core domain clocks and resets to rk3576 Jiaxing Hu
2026-11-01  8:23 ` [PATCH v15 14/15] arm64: dts: rockchip: add NPU (RKNN) nodes " Jiaxing Hu
2026-11-01  8:23 ` [PATCH v15 15/15] arm64: dts: rockchip: enable the NPU on rk3576-rock-4d Jiaxing Hu

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