From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Alexander Koskovich <akoskovich@pm.me>
Cc: Luca Weiss <luca.weiss@fairphone.com>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, devicetree@vger.kernel.org,
Rob Clark <robin.clark@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC v2 5/6] drm/msm/adreno: add Adreno 810 GPU support
Date: Wed, 8 Apr 2026 02:26:34 +0530 [thread overview]
Message-ID: <e069d7f9-e0ff-4908-b438-95689e577e3b@oss.qualcomm.com> (raw)
In-Reply-To: <20260402-adreno-810-v2-5-ce337ca87a9e@pm.me>
On 4/3/2026 4:39 AM, Alexander Koskovich wrote:
> Add catalog entry and register configuration for the Adreno 810
> found in Qualcomm SM7635 (Milos) based devices.
>
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 271 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +
> 2 files changed, 276 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 550ff3a9b82e..8a57e6f9cee0 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1799,6 +1799,240 @@ static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
> };
> DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist);
>
> +static const struct adreno_reglist_pipe a810_nonctxt_regs[] = {
> + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
> + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00f80800, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000023, BIT(PIPE_BV) }, /* Avoid partial waves at VFD */
> + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
> + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
> + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
> + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
> + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
> + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
> + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
> + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
> + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
> + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
> + /*
> + * BIT(22): Disable PS out of order retire
> + * BIT(23): Enable half wave mode and MM instruction src&dst is half precision
> + */
> + { REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) },
> + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
> + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
> + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
> + { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
> + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
> + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000724, BIT(PIPE_NONE) },
> + { REG_A6XX_UCHE_MODE_CNTL, 0x00020000, BIT(PIPE_NONE) },
> + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
> + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
> + { REG_A8XX_UCHE_CACHE_WAYS, 0x00080000, BIT(PIPE_NONE) },
> + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
> + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VSC_BIN_SIZE, 0x00010001, BIT(PIPE_NONE) },
> + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x00900000, BIT(PIPE_BR) },
> + { },
> +};
> +
> +static const u32 a810_protect_regs[] = {
> + A6XX_PROTECT_RDONLY(0x00000, 0x03a3),
> + A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
> + A6XX_PROTECT_NORDWR(0x00440, 0x001f),
> + A6XX_PROTECT_RDONLY(0x00580, 0x005f),
> + A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
> + A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
> + A6XX_PROTECT_RDONLY(0x00759, 0x0026),
> + A6XX_PROTECT_RDONLY(0x00789, 0x0000),
> + A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
> + A6XX_PROTECT_NORDWR(0x00800, 0x0029),
> + A6XX_PROTECT_NORDWR(0x00837, 0x00af),
> + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
> + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
> + A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
> + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
> + A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
> + A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
> + A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
> + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
> + A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
> + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
> + A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
> + A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
> + A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
> + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
> + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
> + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
> + A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
> + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
> + A6XX_PROTECT_NORDWR(0x0ae10, 0x036f),
> + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
> + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x18400, 0x003f),
> + A6XX_PROTECT_RDONLY(0x18440, 0x013f),
> + A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
> + A6XX_PROTECT_RDONLY(0x1f878, 0x0787),
> + A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
> + A6XX_PROTECT_NORDWR(0x20000, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x27800, 0x007f),
> + A6XX_PROTECT_RDONLY(0x27880, 0x0381),
> + A6XX_PROTECT_NORDWR(0x27882, 0x0001),
> + /* CP_PROTECT_REG[46, 62] are left untouched! */
> + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
This is unnecessary waste of space. Were you trying to align with the
downstream code?
> + A6XX_PROTECT_NORDWR(0x27c02, 0x0000),
> +};
> +DECLARE_ADRENO_PROTECT(a810_protect, 64);
Please add this to the __build_asserts() below.
> +
> +static const uint32_t a810_pwrup_reglist_regs[] = {
> + REG_A6XX_UCHE_MODE_CNTL,
> + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT,
> + REG_A8XX_UCHE_GBIF_GX_CONFIG,
> + REG_A8XX_UCHE_CACHE_WAYS,
> + REG_A8XX_UCHE_CCHE_MODE_CNTL,
> + REG_A8XX_UCHE_CCHE_CACHE_WAYS,
> + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN,
> + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1,
> + REG_A8XX_UCHE_WRITE_THRU_BASE,
> + REG_A8XX_UCHE_WRITE_THRU_BASE + 1,
> + REG_A8XX_UCHE_TRAP_BASE,
> + REG_A8XX_UCHE_TRAP_BASE + 1,
> + REG_A8XX_UCHE_CLIENT_PF,
> + REG_A8XX_VSC_BIN_SIZE,
> + REG_A8XX_RB_CMP_NC_MODE_CNTL,
> + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP,
> + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN,
> + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1,
> + REG_A7XX_SP_READ_SEL,
GEN8_UCHE_CCHE_TRAP_BASE_LO
GEN8_UCHE_CCHE_TRAP_BASE_HI
GEN8_UCHE_CCHE_WRITE_THRU_BASE_LO
GEN8_UCHE_CCHE_WRITE_THRU_BASE_HI
We need to include these here.
> +};
> +DECLARE_ADRENO_REGLIST_LIST(a810_pwrup_reglist);
> +
> +static const u32 a810_ifpc_reglist_regs[] = {
> + REG_A8XX_RBBM_NC_MODE_CNTL,
> + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL,
> + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL,
> + REG_A6XX_SP_NC_MODE_CNTL,
> + REG_A7XX_SP_CHICKEN_BITS_2,
> + REG_A7XX_SP_CHICKEN_BITS_3,
> + REG_A6XX_SP_PERFCTR_SHADER_MASK,
> + REG_A6XX_TPL1_NC_MODE_CNTL,
> + REG_A6XX_TPL1_DBG_ECO_CNTL,
> + REG_A6XX_TPL1_DBG_ECO_CNTL1,
> + REG_A8XX_RBBM_PERFCTR_CNTL,
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19),
TPL1 registers should be in pwrup_reglist as the latest code.
> + REG_A8XX_CP_PROTECT_GLOBAL(0),
> + REG_A8XX_CP_PROTECT_GLOBAL(1),
> + REG_A8XX_CP_PROTECT_GLOBAL(2),
> + REG_A8XX_CP_PROTECT_GLOBAL(3),
> + REG_A8XX_CP_PROTECT_GLOBAL(4),
> + REG_A8XX_CP_PROTECT_GLOBAL(5),
> + REG_A8XX_CP_PROTECT_GLOBAL(6),
> + REG_A8XX_CP_PROTECT_GLOBAL(7),
> + REG_A8XX_CP_PROTECT_GLOBAL(8),
> + REG_A8XX_CP_PROTECT_GLOBAL(9),
> + REG_A8XX_CP_PROTECT_GLOBAL(10),
> + REG_A8XX_CP_PROTECT_GLOBAL(11),
> + REG_A8XX_CP_PROTECT_GLOBAL(12),
> + REG_A8XX_CP_PROTECT_GLOBAL(13),
> + REG_A8XX_CP_PROTECT_GLOBAL(14),
> + REG_A8XX_CP_PROTECT_GLOBAL(15),
> + REG_A8XX_CP_PROTECT_GLOBAL(16),
> + REG_A8XX_CP_PROTECT_GLOBAL(17),
> + REG_A8XX_CP_PROTECT_GLOBAL(18),
> + REG_A8XX_CP_PROTECT_GLOBAL(19),
> + REG_A8XX_CP_PROTECT_GLOBAL(20),
> + REG_A8XX_CP_PROTECT_GLOBAL(21),
> + REG_A8XX_CP_PROTECT_GLOBAL(22),
> + REG_A8XX_CP_PROTECT_GLOBAL(23),
> + REG_A8XX_CP_PROTECT_GLOBAL(24),
> + REG_A8XX_CP_PROTECT_GLOBAL(25),
> + REG_A8XX_CP_PROTECT_GLOBAL(26),
> + REG_A8XX_CP_PROTECT_GLOBAL(27),
> + REG_A8XX_CP_PROTECT_GLOBAL(28),
> + REG_A8XX_CP_PROTECT_GLOBAL(29),
> + REG_A8XX_CP_PROTECT_GLOBAL(30),
> + REG_A8XX_CP_PROTECT_GLOBAL(31),
> + REG_A8XX_CP_PROTECT_GLOBAL(32),
> + REG_A8XX_CP_PROTECT_GLOBAL(33),
> + REG_A8XX_CP_PROTECT_GLOBAL(34),
> + REG_A8XX_CP_PROTECT_GLOBAL(35),
> + REG_A8XX_CP_PROTECT_GLOBAL(36),
> + REG_A8XX_CP_PROTECT_GLOBAL(37),
> + REG_A8XX_CP_PROTECT_GLOBAL(38),
> + REG_A8XX_CP_PROTECT_GLOBAL(39),
> + REG_A8XX_CP_PROTECT_GLOBAL(40),
> + REG_A8XX_CP_PROTECT_GLOBAL(41),
> + REG_A8XX_CP_PROTECT_GLOBAL(42),
> + REG_A8XX_CP_PROTECT_GLOBAL(43),
> + REG_A8XX_CP_PROTECT_GLOBAL(44),
> + REG_A8XX_CP_PROTECT_GLOBAL(45),
> + REG_A8XX_CP_PROTECT_GLOBAL(63),
nit: Better to include all protect registers here.
-Akhil
> +};
> +DECLARE_ADRENO_REGLIST_LIST(a810_ifpc_reglist);
> +
> +static const struct adreno_reglist_pipe a810_dyn_pwrup_reglist_regs[] = {
> + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
> + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) },
> + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> +};
> +DECLARE_ADRENO_REGLIST_PIPE_LIST(a810_dyn_pwrup_reglist);
> +
> static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
> { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
> { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
> @@ -2193,6 +2427,43 @@ static const struct adreno_info a8xx_gpus[] = {
> { 252, 2 },
> { 221, 3 },
> ),
> + }, {
> + .chip_ids = ADRENO_CHIP_IDS(0x44010000),
> + .family = ADRENO_8XX_GEN1,
> + .fw = {
> + [ADRENO_FW_SQE] = "gen80300_sqe.fw",
> + [ADRENO_FW_GMU] = "gen80300_gmu.bin",
> + },
> + .gmem = SZ_512K + SZ_64K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> + ADRENO_QUIRK_HAS_HW_APRIV |
> + ADRENO_QUIRK_PREEMPTION |
> + ADRENO_QUIRK_IFPC,
> + .funcs = &a8xx_gpu_funcs,
> + .zapfw = "gen80300_zap.mbn",
> + .a6xx = &(const struct a6xx_info) {
> + .protect = &a810_protect,
> + .nonctxt_reglist = a810_nonctxt_regs,
> + .pwrup_reglist = &a810_pwrup_reglist,
> + .dyn_pwrup_reglist = &a810_dyn_pwrup_reglist,
> + .ifpc_reglist = &a810_ifpc_reglist,
> + .gbif_cx = a840_gbif,
> + .max_slices = 1,
> + .gmu_chipid = 0x8030000,
> + .bcms = (const struct a6xx_bcm[]) {
> + { .name = "SH0", .buswidth = 16 },
> + { .name = "MC0", .buswidth = 4 },
> + {
> + .name = "ACV",
> + .fixed = true,
> + .perfmode = BIT(2),
> + .perfmode_bw = 10687500,
> + },
> + { /* sentinel */ },
> + },
> + },
> + .preempt_record_size = 4558 * SZ_1K,
> }
> };
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index c0ee544ce257..d474d88b9152 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -596,6 +596,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gpu)
> return gpu->info->family >= ADRENO_8XX_GEN1;
> }
>
> +static inline int adreno_is_a810(struct adreno_gpu *gpu)
> +{
> + return gpu->info->chip_ids[0] == 0x44010000;
> +}
> +
> static inline int adreno_is_x285(struct adreno_gpu *gpu)
> {
> return gpu->info->chip_ids[0] == 0x44070001;
>
next prev parent reply other threads:[~2026-04-07 20:56 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-02 23:08 [PATCH RFC v2 0/6] Add support for Adreno 810 GPU Alexander Koskovich
2026-04-02 23:09 ` [PATCH RFC v2 1/6] dt-bindings: display/msm/gmu: Document Adreno 810 GMU Alexander Koskovich
2026-04-07 19:45 ` Akhil P Oommen
2026-04-02 23:09 ` [PATCH RFC v2 2/6] drm/msm/adreno: rename llc_mmio to cx_misc_mmio Alexander Koskovich
2026-04-07 9:45 ` Konrad Dybcio
2026-04-07 19:47 ` Akhil P Oommen
2026-04-02 23:09 ` [PATCH RFC v2 3/6] drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC Alexander Koskovich
2026-04-07 20:04 ` Akhil P Oommen
2026-04-02 23:09 ` [PATCH RFC v2 4/6] drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature Alexander Koskovich
2026-04-07 21:14 ` Akhil P Oommen
2026-04-07 21:17 ` Akhil P Oommen
2026-04-02 23:09 ` [PATCH RFC v2 5/6] drm/msm/adreno: add Adreno 810 GPU support Alexander Koskovich
2026-04-07 20:56 ` Akhil P Oommen [this message]
2026-04-02 23:09 ` [PATCH RFC v2 6/6] arm64: dts: qcom: milos: Add Adreno 810 GPU and GMU nodes Alexander Koskovich
2026-04-04 21:57 ` Dmitry Baryshkov
2026-04-07 19:26 ` [PATCH RFC v2 0/6] Add support for Adreno 810 GPU Akhil P Oommen
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