Re: [PATCH v3 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 17/06/2023 14:54, Shiji Yang wrote:
>> void __init plat_time_init(void)
>> {
>> +	struct of_phandle_args clkspec;
>> 	struct clk *clk;
>> +	int cpu_clk_idx;
>>
>> 	ralink_of_remap();
>>
>> -	ralink_clk_init();
>> -	clk = clk_get_sys("cpu", NULL);
>> +	cpu_clk_idx = clk_cpu_index();
>> +	if (cpu_clk_idx == -1)
>> +		panic("unable to get CPU clock index");
>> +
>> +	of_clk_init(NULL);
>> +	clkspec.np = of_find_node_by_name(NULL, "sysc");
> 
> The node name should be "syscon" as the example node name in the
> dt-bindings document is "syscon".

NAK for both.

Node names must not be an ABI, unless you talk about child of some
device node. I don't think this is the case here. Look by phandle (for a
device context) or by compatible (looks the case here).



Best regards,
Krzysztof