Re: [PATCH] arm64: dts: qcom: sm8550: add SDHC4 controller node

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 4/23/26 6:50 PM, William Bright wrote:
> Add the SDC4 SDHCI controller node for the SM8550 SoC.
> 
> SMMU stream ID 0x80 was sourced from the UEFI bootloader IORT tables,
> as SDCC stream IDs are not documented in the register reference manual.
> Unlike SDC2, the data path is routed via aggre1_noc, matching
> MASTER_SDCC_4 in drivers/interconnect/qcom/sm8550.c.
> 
> Tested on the IMDT QCS8550 SBC at high-speed (HS) mode. UHS modes were
> masked out as they failed to initialise; the root cause has not yet
> been determined. This board is not currently supported in-tree.
> 
> Co-developed-by: Tendai Makumire <tendai.makumire@imd-tec.com>
> Signed-off-by: Tendai Makumire <tendai.makumire@imd-tec.com>
> Signed-off-by: William Bright <william.bright@imd-tec.com>
> Tested-by: William Bright <william.bright@imd-tec.com>

(we sure do hope you test your patch! ;))

[...]

> +			qcom,dll-config = <0x0007642c>;
> +			qcom,ddr-config = <0x80040868>;

I think these properties are invalid for this SDC instance (i.e.
should be removed)

[...]

> +			sdhc4_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-19200000 {
> +					opp-hz = /bits/ 64 <19200000>;
> +					required-opps = <&rpmhpd_opp_min_svs>;
> +				};

The only entry for this specific instance should be 75 MHz-low_svs

Konrad