* [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-11-17 16:27 [PATCH v2 0/6] Initial support for the Realtek interrupt controller James Tai
@ 2023-11-17 16:27 ` James Tai
2023-11-17 17:32 ` Rob Herring
` (2 more replies)
2023-11-17 16:27 ` [PATCH v2 2/6] irqchip: Add interrupt controller " James Tai
` (4 subsequent siblings)
5 siblings, 3 replies; 26+ messages in thread
From: James Tai @ 2023-11-17 16:27 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, James Tai
Cc: linux-kernel, devicetree
Add the YAML documentation for Realtek DHC SoCs.
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Marc Zyngier <maz@kernel.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Conor Dooley <conor+dt@kernel.org>
CC: linux-kernel@vger.kernel.org
CC: devicetree@vger.kernel.org
Signed-off-by: James Tai <james.tai@realtek.com>
---
v1 to v2 change:
- Tested the bindings using 'make dt_binding_check'
- Fixed code style issues
.../realtek,rtd1319-intc.yaml | 79 +++++++++++++++++++
.../realtek,rtd1319d-intc.yaml | 79 +++++++++++++++++++
.../realtek,rtd1325-intc.yaml | 79 +++++++++++++++++++
.../realtek,rtd1619b-intc.yaml | 78 ++++++++++++++++++
4 files changed, 315 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1325-intc.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1619b-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml
new file mode 100644
index 000000000000..b88f3ac07cd9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtd1319-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek DHC RTD1319 Interrupt Controller Device Tree Bindings
+
+description:
+ This interrupt controller is a component of Realtek DHC RTD1319 and
+ is designed to receive interrupts from peripheral devices.
+
+ Each DHC SoC has two sets of interrupt controllers, each capable of
+ handling up to 32 interrupts.
+
+maintainers:
+ - James Tai <james.tai@realtek.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ "#interrupt-cells":
+ const: 1
+
+ compatible:
+ enum:
+ - realtek,rtd1319-intc-iso
+ - realtek,rtd1319-intc-misc
+
+ "#address-cells":
+ const: 0
+
+ interrupt-controller: true
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4
+
+ reg:
+ maxItems: 1
+
+required:
+ - "#interrupt-cells"
+ - "#address-cells"
+ - compatible
+ - interrupt-controller
+ - interrupts-extended
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rtd1319_iso_irq: interrupt-controller@40 {
+ compatible = "realtek,rtd1319-intc-iso";
+ reg = <0x00 0x40>;
+ interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ rtd1319_misc_irq: interrupt-controller@80 {
+ compatible = "realtek,rtd1319-intc-misc";
+ reg = <0x00 0x80>;
+ interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml
new file mode 100644
index 000000000000..75aba448baf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtd1319d-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek DHC RTD1319D Interrupt Controller Device Tree Bindings
+
+description:
+ This interrupt controller is a component of Realtek DHC RTD1319D and
+ is designed to receive interrupts from peripheral devices.
+
+ Each DHC SoC has two sets of interrupt controllers, each capable of
+ handling up to 32 interrupts.
+
+maintainers:
+ - James Tai <james.tai@realtek.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ "#interrupt-cells":
+ const: 1
+
+ compatible:
+ enum:
+ - realtek,rtd1319d-intc-iso
+ - realtek,rtd1319d-intc-misc
+
+ "#address-cells":
+ const: 0
+
+ interrupt-controller: true
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4
+
+ reg:
+ maxItems: 1
+
+required:
+ - "#interrupt-cells"
+ - "#address-cells"
+ - compatible
+ - interrupt-controller
+ - interrupts-extended
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rtd1319d_iso_irq: interrupt-controller@40 {
+ compatible = "realtek,rtd1319d-intc-iso";
+ reg = <0x00 0x40>;
+ interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ rtd1319d_misc_irq: interrupt-controller@80 {
+ compatible = "realtek,rtd1319d-intc-misc";
+ reg = <0x00 0x80>;
+ interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1325-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1325-intc.yaml
new file mode 100644
index 000000000000..49e71d17390a
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1325-intc.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtd1325-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek DHC RTD1325 Interrupt Controller Device Tree Bindings
+
+description:
+ This interrupt controller is a component of Realtek DHC RTD1325 and
+ is designed to receive interrupts from peripheral devices.
+
+ Each DHC SoC has two sets of interrupt controllers, each capable of
+ handling up to 32 interrupts.
+
+maintainers:
+ - James Tai <james.tai@realtek.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ "#interrupt-cells":
+ const: 1
+
+ compatible:
+ enum:
+ - realtek,rtd1325-intc-iso
+ - realtek,rtd1325-intc-misc
+
+ "#address-cells":
+ const: 0
+
+ interrupt-controller: true
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4
+
+ reg:
+ maxItems: 1
+
+required:
+ - "#interrupt-cells"
+ - "#address-cells"
+ - compatible
+ - interrupt-controller
+ - interrupts-extended
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rtd1325_iso_irq: interrupt-controller@40 {
+ compatible = "realtek,rtd1325-intc-iso";
+ reg = <0x00 0x40>;
+ interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ rtd1325_misc_irq: interrupt-controller@80 {
+ compatible = "realtek,rtd1325-intc-misc";
+ reg = <0x00 0x80>;
+ interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1619b-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1619b-intc.yaml
new file mode 100644
index 000000000000..79d855d15893
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1619b-intc.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtd1619b-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek DHC RTD1619B Interrupt Controller Device Tree Bindings
+
+description:
+ This interrupt controller is a component of Realtek DHC RTD1619B and
+ is designed to receive interrupts from peripheral devices.
+
+ Each DHC SoC has two sets of interrupt controllers, each capable of
+ handling up to 32 interrupts.
+
+maintainers:
+ - James Tai <james.tai@realtek.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ "#interrupt-cells":
+ const: 1
+
+ compatible:
+ enum:
+ - realtek,rtd1619b-intc-iso
+ - realtek,rtd1619b-intc-misc
+
+ "#address-cells":
+ const: 0
+
+ interrupt-controller: true
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4
+
+ reg:
+ maxItems: 1
+
+required:
+ - "#interrupt-cells"
+ - "#address-cells"
+ - compatible
+ - interrupt-controller
+ - interrupts-extended
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rtd1619b_iso_irq: interrupt-controller@40 {
+ compatible = "realtek,rtd1619b-intc-iso";
+ reg = <0x00 0x40>;
+ interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ rtd1619b_misc_irq: interrupt-controller@80 {
+ compatible = "realtek,rtd1619b-intc-misc";
+ reg = <0x00 0x80>;
+ interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+...
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-11-17 16:27 ` [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs James Tai
@ 2023-11-17 17:32 ` Rob Herring
2023-11-18 13:32 ` James Tai [戴志峰]
2023-11-18 1:37 ` kernel test robot
2023-11-19 12:47 ` Krzysztof Kozlowski
2 siblings, 1 reply; 26+ messages in thread
From: Rob Herring @ 2023-11-17 17:32 UTC (permalink / raw)
To: James Tai
Cc: linux-kernel, Rob Herring, Thomas Gleixner, Marc Zyngier,
Krzysztof Kozlowski, devicetree, Conor Dooley
On Sat, 18 Nov 2023 00:27:04 +0800, James Tai wrote:
> Add the YAML documentation for Realtek DHC SoCs.
>
> CC: Thomas Gleixner <tglx@linutronix.de>
> CC: Marc Zyngier <maz@kernel.org>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> CC: Conor Dooley <conor+dt@kernel.org>
> CC: linux-kernel@vger.kernel.org
> CC: devicetree@vger.kernel.org
> Signed-off-by: James Tai <james.tai@realtek.com>
> ---
> v1 to v2 change:
> - Tested the bindings using 'make dt_binding_check'
> - Fixed code style issues
>
> .../realtek,rtd1319-intc.yaml | 79 +++++++++++++++++++
> .../realtek,rtd1319d-intc.yaml | 79 +++++++++++++++++++
> .../realtek,rtd1325-intc.yaml | 79 +++++++++++++++++++
> .../realtek,rtd1619b-intc.yaml | 78 ++++++++++++++++++
> 4 files changed, 315 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1325-intc.yaml
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1619b-intc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml: title: 'Realtek DHC RTD1319D Interrupt Controller Device Tree Bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1325-intc.yaml: title: 'Realtek DHC RTD1325 Interrupt Controller Device Tree Bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1619b-intc.yaml: title: 'Realtek DHC RTD1619B Interrupt Controller Device Tree Bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml: title: 'Realtek DHC RTD1319 Interrupt Controller Device Tree Bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20231117162709.1096585-2-james.tai@realtek.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-11-17 17:32 ` Rob Herring
@ 2023-11-18 13:32 ` James Tai [戴志峰]
0 siblings, 0 replies; 26+ messages in thread
From: James Tai [戴志峰] @ 2023-11-18 13:32 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel@vger.kernel.org, Rob Herring, Thomas Gleixner,
Marc Zyngier, Krzysztof Kozlowski, devicetree@vger.kernel.org,
Conor Dooley
Hi Rob,
>yamllint warnings/errors:
>
>dtschema/dtc warnings/errors:
>/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/inter
>rupt-controller/realtek,rtd1319d-intc.yaml: title: 'Realtek DHC RTD1319D
>Interrupt Controller Device Tree Bindings' should not be valid under {'pattern':
>'([Bb]inding| [Ss]chema)'}
> hint: Everything is a binding/schema, no need to say it. Describe what
>hardware the binding is for.
> from schema $id: http://devicetree.org/meta-schemas/base.yaml#
>/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/inter
>rupt-controller/realtek,rtd1325-intc.yaml: title: 'Realtek DHC RTD1325 Interrupt
>Controller Device Tree Bindings' should not be valid under {'pattern':
>'([Bb]inding| [Ss]chema)'}
> hint: Everything is a binding/schema, no need to say it. Describe what
>hardware the binding is for.
> from schema $id: http://devicetree.org/meta-schemas/base.yaml#
>/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/inter
>rupt-controller/realtek,rtd1619b-intc.yaml: title: 'Realtek DHC RTD1619B
>Interrupt Controller Device Tree Bindings' should not be valid under {'pattern':
>'([Bb]inding| [Ss]chema)'}
> hint: Everything is a binding/schema, no need to say it. Describe what
>hardware the binding is for.
> from schema $id: http://devicetree.org/meta-schemas/base.yaml#
>/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/inter
>rupt-controller/realtek,rtd1319-intc.yaml: title: 'Realtek DHC RTD1319 Interrupt
>Controller Device Tree Bindings' should not be valid under {'pattern':
>'([Bb]inding| [Ss]chema)'}
> hint: Everything is a binding/schema, no need to say it. Describe what
>hardware the binding is for.
> from schema $id: http://devicetree.org/meta-schemas/base.yaml#
>
>doc reference errors (make refcheckdocs):
>
>See
>https://patchwork.ozlabs.org/project/devicetree-bindings/patch/202311171627
>09.1096585-2-james.tai@realtek.com
>
>The base for the series is generally the latest rc1. A different dependency should
>be noted in *this* patch.
>
>If you already ran 'make dt_binding_check' and didn't see the above error(s),
>then make sure 'yamllint' is installed and dt-schema is up to
>date:
>
>pip3 install dtschema --upgrade
>
>Please check and re-submit after running the above command yourself. Note
>that DT_SCHEMA_FILES can be set to your schema file to speed up checking
>your schema. However, it must be unset to test all examples with your schema.
OK. I will update the dtschema and rerun 'make dt_binding_check'.
Thank you for your feedback.
Regards,
James
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-11-17 16:27 ` [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs James Tai
2023-11-17 17:32 ` Rob Herring
@ 2023-11-18 1:37 ` kernel test robot
2023-11-19 12:47 ` Krzysztof Kozlowski
2 siblings, 0 replies; 26+ messages in thread
From: kernel test robot @ 2023-11-18 1:37 UTC (permalink / raw)
To: James Tai, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: oe-kbuild-all, linux-kernel, devicetree
Hi James,
kernel test robot noticed the following build warnings:
[auto build test WARNING on tip/irq/core]
[also build test WARNING on robh/for-next linus/master v6.7-rc1 next-20231117]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/James-Tai/dt-bindings-interrupt-controller-Add-support-for-Realtek-DHC-SoCs/20231118-003036
base: tip/irq/core
patch link: https://lore.kernel.org/r/20231117162709.1096585-2-james.tai%40realtek.com
patch subject: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
compiler: loongarch64-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20231118/202311180921.ayKhiFHL-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311180921.ayKhiFHL-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1619b-intc.yaml: title: 'Realtek DHC RTD1619B Interrupt Controller Device Tree Bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
>> Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml: title: 'Realtek DHC RTD1319 Interrupt Controller Device Tree Bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
>> Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml: title: 'Realtek DHC RTD1319D Interrupt Controller Device Tree Bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
>> Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1325-intc.yaml: title: 'Realtek DHC RTD1325 Interrupt Controller Device Tree Bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-11-17 16:27 ` [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs James Tai
2023-11-17 17:32 ` Rob Herring
2023-11-18 1:37 ` kernel test robot
@ 2023-11-19 12:47 ` Krzysztof Kozlowski
2023-11-20 9:08 ` James Tai [戴志峰]
2023-12-02 16:42 ` James Tai [戴志峰]
2 siblings, 2 replies; 26+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-19 12:47 UTC (permalink / raw)
To: James Tai, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel, devicetree
On 17/11/2023 17:27, James Tai wrote:
> Add the YAML documentation for Realtek DHC SoCs.
>
> CC: Thomas Gleixner <tglx@linutronix.de>
> CC: Marc Zyngier <maz@kernel.org>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> CC: Conor Dooley <conor+dt@kernel.org>
> CC: linux-kernel@vger.kernel.org
> CC: devicetree@vger.kernel.org
> Signed-off-by: James Tai <james.tai@realtek.com>
> ---
> v1 to v2 change:
> - Tested the bindings using 'make dt_binding_check'
I doubt it.
And bot prooves it.
> - Fixed code style issues
Be specific - what code style issues did you fix?
>
> .../realtek,rtd1319-intc.yaml | 79 +++++++++++++++++++
> .../realtek,rtd1319d-intc.yaml | 79 +++++++++++++++++++
> .../realtek,rtd1325-intc.yaml | 79 +++++++++++++++++++
> .../realtek,rtd1619b-intc.yaml | 78 ++++++++++++++++++
> 4 files changed, 315 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1325-intc.yaml
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1619b-intc.yaml
Why do you have four bindings for the same? Please explain me the
differences.
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml
> new file mode 100644
> index 000000000000..b88f3ac07cd9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319-intc.yaml
> @@ -0,0 +1,79 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtd1319-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Realtek DHC RTD1319 Interrupt Controller Device Tree Bindings
> +
> +description:
> + This interrupt controller is a component of Realtek DHC RTD1319 and
> + is designed to receive interrupts from peripheral devices.
> +
> + Each DHC SoC has two sets of interrupt controllers, each capable of
> + handling up to 32 interrupts.
> +
> +maintainers:
> + - James Tai <james.tai@realtek.com>
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> + "#interrupt-cells":
> + const: 1
compatible is first, put the cells next to other interrupt controller
properties.
> +
> + compatible:
> + enum:
> + - realtek,rtd1319-intc-iso
> + - realtek,rtd1319-intc-misc
> +
> + "#address-cells":
> + const: 0
> +
> + interrupt-controller: true
> +
> + interrupts-extended:
interrupts instead.
Anyway, you must describe the items. Why this is not fixed but flexible?
Hardware has different number of pins? That's unlikely.
> + minItems: 1
> + maxItems: 4
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - "#interrupt-cells"
> + - "#address-cells"
> + - compatible
> + - interrupt-controller
> + - interrupts-extended
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + rtd1319_iso_irq: interrupt-controller@40 {
> + compatible = "realtek,rtd1319-intc-iso";
> + reg = <0x00 0x40>;
> + interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> + <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> +
> + rtd1319_misc_irq: interrupt-controller@80 {
> + compatible = "realtek,rtd1319-intc-misc";
Drop, one example is enough. This is the same as previous.
> + reg = <0x00 0x80>;
> + interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
> + <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
> + <&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml
> new file mode 100644
> index 000000000000..75aba448baf7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319d-intc.yaml
> @@ -0,0 +1,79 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtd1319d-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Realtek DHC RTD1319D Interrupt Controller Device Tree Bindings
> +
> +description:
> + This interrupt controller is a component of Realtek DHC RTD1319D and
> + is designed to receive interrupts from peripheral devices.
> +
> + Each DHC SoC has two sets of interrupt controllers, each capable of
> + handling up to 32 interrupts.
> +
> +maintainers:
> + - James Tai <james.tai@realtek.com>
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> + "#interrupt-cells":
> + const: 1
> +
> + compatible:
> + enum:
> + - realtek,rtd1319d-intc-iso
> + - realtek,rtd1319d-intc-misc
So this is the same as the other one? Why it cannot be part of that one?
...
> +
> +maintainers:
> + - James Tai <james.tai@realtek.com>
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> + "#interrupt-cells":
> + const: 1
> +
> + compatible:
> + enum:
> + - realtek,rtd1325-intc-iso
> + - realtek,rtd1325-intc-misc
All my comments apply to all your bindings...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-11-19 12:47 ` Krzysztof Kozlowski
@ 2023-11-20 9:08 ` James Tai [戴志峰]
2023-12-02 16:18 ` James Tai [戴志峰]
2023-12-02 16:39 ` James Tai [戴志峰]
2023-12-02 16:42 ` James Tai [戴志峰]
1 sibling, 2 replies; 26+ messages in thread
From: James Tai [戴志峰] @ 2023-11-20 9:08 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Hi Krzysztof,
>I doubt it.
>
>And bot prooves it.
My 'dtschema' is outdated, and I encountered errors after updating it.
I will fix it in next patches.
>> - Fixed code style issues
>
>Be specific - what code style issues did you fix?
>
I fixed the code style issue related to the license declaration.
>>
>> .../realtek,rtd1319-intc.yaml | 79
>+++++++++++++++++++
>> .../realtek,rtd1319d-intc.yaml | 79
>+++++++++++++++++++
>> .../realtek,rtd1325-intc.yaml | 79
>+++++++++++++++++++
>> .../realtek,rtd1619b-intc.yaml | 78 ++++++++++++++++++
>> 4 files changed, 315 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319
>> -intc.yaml create mode 100644
>> Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1319
>> d-intc.yaml create mode 100644
>> Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1325
>> -intc.yaml create mode 100644
>> Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1619
>> b-intc.yaml
>
>Why do you have four bindings for the same? Please explain me the differences.
>
If the bindings can be shared, I will consolidate it into one.
>>
>> diff --git
>> a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd13
>> 19-intc.yaml
>> b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd13
>> 19-intc.yaml
>> new file mode 100644
>> index 000000000000..b88f3ac07cd9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,r
>> +++ td1319-intc.yaml
>> @@ -0,0 +1,79 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>> +---
>> +$id:
>> +http://devicetree.org/schemas/interrupt-controller/realtek,rtd1319-in
>> +tc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Realtek DHC RTD1319 Interrupt Controller Device Tree Bindings
>> +
>> +description:
>> + This interrupt controller is a component of Realtek DHC RTD1319 and
>> + is designed to receive interrupts from peripheral devices.
>> +
>> + Each DHC SoC has two sets of interrupt controllers, each capable of
>> + handling up to 32 interrupts.
>> +
>> +maintainers:
>> + - James Tai <james.tai@realtek.com>
>> +
>> +allOf:
>> + - $ref: /schemas/interrupt-controller.yaml#
>> +
>> +properties:
>> + "#interrupt-cells":
>> + const: 1
>
>
>compatible is first, put the cells next to other interrupt controller properties.
>
I will fix it in next patches.
>> +
>> + compatible:
>> + enum:
>> + - realtek,rtd1319-intc-iso
>> + - realtek,rtd1319-intc-misc
>> +
>> + "#address-cells":
>> + const: 0
>> +
>> + interrupt-controller: true
>> +
>> + interrupts-extended:
>
>interrupts instead.
>
>Anyway, you must describe the items. Why this is not fixed but flexible?
>Hardware has different number of pins? That's unlikely.
>
I will replace it with 'interrupts'. Since our Interrupt controller architecture doesn't involve multiple interrupt sources, using 'interrupts' should suffice.
>> + minItems: 1
>> + maxItems: 4
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +required:
>> + - "#interrupt-cells"
>> + - "#address-cells"
>> + - compatible
>> + - interrupt-controller
>> + - interrupts-extended
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + rtd1319_iso_irq: interrupt-controller@40 {
>> + compatible = "realtek,rtd1319-intc-iso";
>> + reg = <0x00 0x40>;
>> + interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
>> + <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + rtd1319_misc_irq: interrupt-controller@80 {
>> + compatible = "realtek,rtd1319-intc-misc";
>
>Drop, one example is enough. This is the same as previous.
>
I will fix it in next patches.
>> + reg = <0x00 0x80>;
>> + interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> + <&gic GIC_SPI 89
>IRQ_TYPE_LEVEL_HIGH>,
>> + <&gic GIC_SPI 90
>IRQ_TYPE_LEVEL_HIGH>,
>> + <&gic GIC_SPI 39
>IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + };
>> +...
>> diff --git
>> a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd13
>> 19d-intc.yaml
>> b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd13
>> 19d-intc.yaml
>> new file mode 100644
>> index 000000000000..75aba448baf7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,r
>> +++ td1319d-intc.yaml
>> @@ -0,0 +1,79 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>> +---
>> +$id:
>> +http://devicetree.org/schemas/interrupt-controller/realtek,rtd1319d-i
>> +ntc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Realtek DHC RTD1319D Interrupt Controller Device Tree Bindings
>> +
>> +description:
>> + This interrupt controller is a component of Realtek DHC RTD1319D
>> +and
>> + is designed to receive interrupts from peripheral devices.
>> +
>> + Each DHC SoC has two sets of interrupt controllers, each capable of
>> + handling up to 32 interrupts.
>> +
>> +maintainers:
>> + - James Tai <james.tai@realtek.com>
>> +
>> +allOf:
>> + - $ref: /schemas/interrupt-controller.yaml#
>> +
>> +properties:
>> + "#interrupt-cells":
>> + const: 1
>> +
>> + compatible:
>> + enum:
>> + - realtek,rtd1319d-intc-iso
>> + - realtek,rtd1319d-intc-misc
>
>So this is the same as the other one? Why it cannot be part of that one?
I will consolidate these parts into a single file.
Thank you for your feedback.
Regards,
James
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-11-20 9:08 ` James Tai [戴志峰]
@ 2023-12-02 16:18 ` James Tai [戴志峰]
2023-12-03 15:04 ` Krzysztof Kozlowski
2023-12-02 16:39 ` James Tai [戴志峰]
1 sibling, 1 reply; 26+ messages in thread
From: James Tai [戴志峰] @ 2023-12-02 16:18 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Hi Krzysztof,
>>> +
>>> + compatible:
>>> + enum:
>>> + - realtek,rtd1319-intc-iso
>>> + - realtek,rtd1319-intc-misc
>>> +
>>> + "#address-cells":
>>> + const: 0
>>> +
>>> + interrupt-controller: true
>>> +
>>> + interrupts-extended:
>>
>>interrupts instead.
>>
>>Anyway, you must describe the items. Why this is not fixed but flexible?
>>Hardware has different number of pins? That's unlikely.
>>
>I will replace it with 'interrupts'. Since our Interrupt controller architecture
>doesn't involve multiple interrupt sources, using 'interrupts' should suffice.
>
Due to changes in hardware design, some peripheral interrupts pin initially connected to the Realtek interrupt controller were redirected to the GIC.
However, the associated fields and statuses in the Realtek interrupt controller registers were not removed.
As a result, these interrupts cannot be cleared by peripheral register, and their status clearing is still needing the Realtek interrupt controller driver to manage.
That's why flexibility is necessary.
Regards,
James
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-12-02 16:18 ` James Tai [戴志峰]
@ 2023-12-03 15:04 ` Krzysztof Kozlowski
2023-12-03 15:56 ` James Tai [戴志峰]
0 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2023-12-03 15:04 UTC (permalink / raw)
To: James Tai [戴志峰], Thomas Gleixner,
Marc Zyngier, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
On 02/12/2023 17:18, James Tai [戴志峰] wrote:
> Hi Krzysztof,
>
>>>> +
>>>> + compatible:
>>>> + enum:
>>>> + - realtek,rtd1319-intc-iso
>>>> + - realtek,rtd1319-intc-misc
>>>> +
>>>> + "#address-cells":
>>>> + const: 0
>>>> +
>>>> + interrupt-controller: true
>>>> +
>>>> + interrupts-extended:
>>>
>>> interrupts instead.
>>>
>>> Anyway, you must describe the items. Why this is not fixed but flexible?
>>> Hardware has different number of pins? That's unlikely.
>>>
>> I will replace it with 'interrupts'. Since our Interrupt controller architecture
>> doesn't involve multiple interrupt sources, using 'interrupts' should suffice.
>>
>
> Due to changes in hardware design, some peripheral interrupts pin initially connected to the Realtek interrupt controller were redirected to the GIC.
> However, the associated fields and statuses in the Realtek interrupt controller registers were not removed.
> As a result, these interrupts cannot be cleared by peripheral register, and their status clearing is still needing the Realtek interrupt controller driver to manage.
>
> That's why flexibility is necessary.
This does not explain why this is not fixed per variant.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-12-03 15:04 ` Krzysztof Kozlowski
@ 2023-12-03 15:56 ` James Tai [戴志峰]
2023-12-03 16:32 ` Krzysztof Kozlowski
0 siblings, 1 reply; 26+ messages in thread
From: James Tai [戴志峰] @ 2023-12-03 15:56 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Hi Krzysztof,
>>>>> +
>>>>> + compatible:
>>>>> + enum:
>>>>> + - realtek,rtd1319-intc-iso
>>>>> + - realtek,rtd1319-intc-misc
>>>>> +
>>>>> + "#address-cells":
>>>>> + const: 0
>>>>> +
>>>>> + interrupt-controller: true
>>>>> +
>>>>> + interrupts-extended:
>>>>
>>>> interrupts instead.
>>>>
>>>> Anyway, you must describe the items. Why this is not fixed but flexible?
>>>> Hardware has different number of pins? That's unlikely.
>>>>
>>> I will replace it with 'interrupts'. Since our Interrupt controller
>>> architecture doesn't involve multiple interrupt sources, using 'interrupts'
>should suffice.
>>>
>>
>> Due to changes in hardware design, some peripheral interrupts pin initially
>connected to the Realtek interrupt controller were redirected to the GIC.
>> However, the associated fields and statuses in the Realtek interrupt controller
>registers were not removed.
>> As a result, these interrupts cannot be cleared by peripheral register, and their
>status clearing is still needing the Realtek interrupt controller driver to manage.
>>
>> That's why flexibility is necessary.
>
>This does not explain why this is not fixed per variant.
>
Does the definition of "fixed" you mentioned refer to fixed interrupt pins? If not, could you please give me an example and let me know what you mean by "fixed"?
Thank you for your feedback.
Regards,
James
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-12-03 15:56 ` James Tai [戴志峰]
@ 2023-12-03 16:32 ` Krzysztof Kozlowski
2023-12-05 8:43 ` James Tai [戴志峰]
0 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2023-12-03 16:32 UTC (permalink / raw)
To: James Tai [戴志峰], Thomas Gleixner,
Marc Zyngier, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
On 03/12/2023 16:56, James Tai [戴志峰] wrote:
>>>>>> + interrupts-extended:
>>>>>
>>>>> interrupts instead.
>>>>>
>>>>> Anyway, you must describe the items. Why this is not fixed but flexible?
>>>>> Hardware has different number of pins? That's unlikely.
>>>>>
>>>> I will replace it with 'interrupts'. Since our Interrupt controller
>>>> architecture doesn't involve multiple interrupt sources, using 'interrupts'
>> should suffice.
>>>>
>>>
>>> Due to changes in hardware design, some peripheral interrupts pin initially
>> connected to the Realtek interrupt controller were redirected to the GIC.
>>> However, the associated fields and statuses in the Realtek interrupt controller
>> registers were not removed.
>>> As a result, these interrupts cannot be cleared by peripheral register, and their
>> status clearing is still needing the Realtek interrupt controller driver to manage.
>>>
>>> That's why flexibility is necessary.
>>
>> This does not explain why this is not fixed per variant.
>>
>
> Does the definition of "fixed" you mentioned refer to fixed interrupt pins? If not, could you please give me an example and let me know what you mean by "fixed"?
Number of the interrupts per each device or variant should be strictly
defined, not variable.
Please wrap your emails according to mail netiquette.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-12-03 16:32 ` Krzysztof Kozlowski
@ 2023-12-05 8:43 ` James Tai [戴志峰]
2023-12-05 8:47 ` Krzysztof Kozlowski
0 siblings, 1 reply; 26+ messages in thread
From: James Tai [戴志峰] @ 2023-12-05 8:43 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Hi Krzysztof,
>>>>>>> + interrupts-extended:
>>>>>>
>>>>>> interrupts instead.
>>>>>>
>>>>>> Anyway, you must describe the items. Why this is not fixed but flexible?
>>>>>> Hardware has different number of pins? That's unlikely.
>>>>>>
>>>>> I will replace it with 'interrupts'. Since our Interrupt controller
>>>>> architecture doesn't involve multiple interrupt sources, using 'interrupts'
>>> should suffice.
>>>>>
>>>>
>>>> Due to changes in hardware design, some peripheral interrupts pin
>>>> initially
>>> connected to the Realtek interrupt controller were redirected to the GIC.
>>>> However, the associated fields and statuses in the Realtek interrupt
>>>> controller
>>> registers were not removed.
>>>> As a result, these interrupts cannot be cleared by peripheral
>>>> register, and their
>>> status clearing is still needing the Realtek interrupt controller driver to
>manage.
>>>>
>>>> That's why flexibility is necessary.
>>>
>>> This does not explain why this is not fixed per variant.
>>>
>>
>> Does the definition of "fixed" you mentioned refer to fixed interrupt pins? If
>> not, could you please give me an example and let me know what you mean by
>> "fixed"?
>
>Number of the interrupts per each device or variant should be strictly defined,
>not variable.
Thank you for your explanation.
The DHC platforms contain two interrupt controllers, each handling peripheral device interrupts in the two power domains.
While each has a fixed IRQ numbers, the specific IRQ varies depending on the platform.
>Please wrap your emails according to mail netiquette.
I apologize for my rude way of asking the question. I will improve my expression.
Thank for your feedback.
Regards,
James
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-12-05 8:43 ` James Tai [戴志峰]
@ 2023-12-05 8:47 ` Krzysztof Kozlowski
2023-12-06 15:07 ` James Tai [戴志峰]
0 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2023-12-05 8:47 UTC (permalink / raw)
To: James Tai [戴志峰], Thomas Gleixner,
Marc Zyngier, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
On 05/12/2023 09:43, James Tai [戴志峰] wrote:
> Hi Krzysztof,
>
>>>>>>>> + interrupts-extended:
>>>>>>>
>>>>>>> interrupts instead.
>>>>>>>
>>>>>>> Anyway, you must describe the items. Why this is not fixed but flexible?
>>>>>>> Hardware has different number of pins? That's unlikely.
>>>>>>>
>>>>>> I will replace it with 'interrupts'. Since our Interrupt controller
>>>>>> architecture doesn't involve multiple interrupt sources, using 'interrupts'
>>>> should suffice.
>>>>>>
>>>>>
>>>>> Due to changes in hardware design, some peripheral interrupts pin
>>>>> initially
>>>> connected to the Realtek interrupt controller were redirected to the GIC.
>>>>> However, the associated fields and statuses in the Realtek interrupt
>>>>> controller
>>>> registers were not removed.
>>>>> As a result, these interrupts cannot be cleared by peripheral
>>>>> register, and their
>>>> status clearing is still needing the Realtek interrupt controller driver to
>> manage.
>>>>>
>>>>> That's why flexibility is necessary.
>>>>
>>>> This does not explain why this is not fixed per variant.
>>>>
>>>
>>> Does the definition of "fixed" you mentioned refer to fixed interrupt pins? If
>>> not, could you please give me an example and let me know what you mean by
>>> "fixed"?
>>
>> Number of the interrupts per each device or variant should be strictly defined,
>> not variable.
>
> Thank you for your explanation.
>
> The DHC platforms contain two interrupt controllers, each handling peripheral device interrupts in the two power domains.
> While each has a fixed IRQ numbers, the specific IRQ varies depending on the platform.
Srsly, what "specific IRQ" has anything to do with "number of interrupts
per each device or variant"?
Look at all other bindings covering multiple devices and their
clocks/interrupts/interconnects/reg etc.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-12-05 8:47 ` Krzysztof Kozlowski
@ 2023-12-06 15:07 ` James Tai [戴志峰]
2023-12-06 17:48 ` Krzysztof Kozlowski
0 siblings, 1 reply; 26+ messages in thread
From: James Tai [戴志峰] @ 2023-12-06 15:07 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Hi Krzysztof,
>>>>>>>>> + interrupts-extended:
>>>>>>>>
>>>>>>>> interrupts instead.
>>>>>>>>
>>>>>>>> Anyway, you must describe the items. Why this is not fixed but
>flexible?
>>>>>>>> Hardware has different number of pins? That's unlikely.
>>>>>>>>
>>>>>>> I will replace it with 'interrupts'. Since our Interrupt
>>>>>>> controller architecture doesn't involve multiple interrupt sources, using
>'interrupts'
>>>>> should suffice.
>>>>>>>
>>>>>>
>>>>>> Due to changes in hardware design, some peripheral interrupts pin
>>>>>> initially
>>>>> connected to the Realtek interrupt controller were redirected to the GIC.
>>>>>> However, the associated fields and statuses in the Realtek
>>>>>> interrupt controller
>>>>> registers were not removed.
>>>>>> As a result, these interrupts cannot be cleared by peripheral
>>>>>> register, and their
>>>>> status clearing is still needing the Realtek interrupt controller
>>>>> driver to
>>> manage.
>>>>>>
>>>>>> That's why flexibility is necessary.
>>>>>
>>>>> This does not explain why this is not fixed per variant.
>>>>>
>>>>
>>>> Does the definition of "fixed" you mentioned refer to fixed
>>>> interrupt pins? If not, could you please give me an example and let
>>>> me know what you mean by "fixed"?
>>>
>>> Number of the interrupts per each device or variant should be
>>> strictly defined, not variable.
>>
>> Thank you for your explanation.
>>
>> The DHC platforms contain two interrupt controllers, each handling peripheral
>device interrupts in the two power domains.
>> While each has a fixed IRQ numbers, the specific IRQ varies depending on the
>>platform.
>
>Srsly, what "specific IRQ" has anything to do with "number of interrupts per
>each device or variant"?
Each Realtek interrupt controller is assigned a fixed IRQ, which gathers interrupts from peripheral devices such as i2c, spi, ethernet phy, timer, uart, watchdog, rtc, pwm, etc.
Due to modifications in the hardware circuit, certain peripheral device interrupts including watchdog, rtc, uart1, and uart2 are now redirected to the GIC.
Consequently, these devices cannot clear interrupt statuses through their own registers. To resolve this, we manage their interrupts through the Realtek interrupt controller.
This results in a variation in the number of IRQs registered by the interrupt controllers of ISO (isolation) and MSIC (miscellaneous).
In the DTS examples provided in the initial patch release, IRQs 41 and 42 are assigned to the Realtek interrupt controller.
As watchdog, rtc, uart1, and uart2 interrupts no longer use IRQs 41 or 42, their IRQs (0, 39, 89, 90) are assigned to be registered by the Realtek interrupt controller.
Fixed IRQs:
- 41: peripheral devices (iso power domain)
- 42: peripheral devices (misc power domain)
Specific IRQs:
- 0: watchdog (iso power domain)
- 39: rtc (misc power domain)
- 89: uart1 (misc power domain)
- 90: uart2 (misc power domain)
Examples(v1 patches):
iso_irq_mux: iso_irq_mux@40 {
compatible = "realtek,rtd1319-intc-iso";
reg = <0x00 0x40>;
interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
misc_irq_mux: misc_irq_mux@80 {
compatible = "realtek,rtd1319-intc-misc";
reg = <0x00 0x80>;
interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
iso_irq_mux: iso_irq_mux@40 {
compatible = "realtek,rtd1319d-intc-iso";
reg = <0x00 0x40>;
interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
misc_irq_mux: misc_irq_mux@80 {
compatible = "realtek,rtd1319d-intc-misc";
reg = <0x00 0x80>;
interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
iso_irq_mux: iso_irq_mux@40 {
compatible = "realtek,rtd1325-intc-iso";
reg = <0x00 0x40>;
interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
misc_irq_mux: misc_irq_mux@80 {
compatible = "realtek,rtd1325-intc-misc";
reg = <0x00 0x80>;
interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
iso_irq_mux: iso_irq_mux@40 {
compatible = "realtek,rtd1619b-intc-iso";
reg = <0x00 0x40>;
interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
misc_irq_mux: misc_irq_mux@80 {
compatible = "realtek,rtd1619b-intc-misc";
reg = <0x00 0x80>;
interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
>
>Look at all other bindings covering multiple devices and their
>clocks/interrupts/interconnects/reg etc.
May I adopt the approach used in this YAML for my case?
https://www.kernel.org/doc/Documentation/devicetree/bindings/timer/allwinner%2Csun4i-a10-timer.yaml
Thank you for your feedback.
Regards,
James
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-12-06 15:07 ` James Tai [戴志峰]
@ 2023-12-06 17:48 ` Krzysztof Kozlowski
2023-12-07 5:59 ` James Tai [戴志峰]
0 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2023-12-06 17:48 UTC (permalink / raw)
To: James Tai [戴志峰], Thomas Gleixner,
Marc Zyngier, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
On 06/12/2023 16:07, James Tai [戴志峰] wrote:
>
> misc_irq_mux: misc_irq_mux@80 {
> compatible = "realtek,rtd1619b-intc-misc";
> reg = <0x00 0x80>;
> interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
> <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
> interrupt-controller;
> #address-cells = <0>;
> #interrupt-cells = <1>;
> };
So you have strictly defined number of interrupts and the actual
interrupts per variant.
>
>>
>> Look at all other bindings covering multiple devices and their
>> clocks/interrupts/interconnects/reg etc.
>
> May I adopt the approach used in this YAML for my case?
> https://www.kernel.org/doc/Documentation/devicetree/bindings/timer/allwinner%2Csun4i-a10-timer.yaml
I am asking for this since few emails.
Look:
"Anyway, you must describe the items. Why this is not fixed but flexible?
Hardware has different number of pins? That's unlikely."
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-12-06 17:48 ` Krzysztof Kozlowski
@ 2023-12-07 5:59 ` James Tai [戴志峰]
0 siblings, 0 replies; 26+ messages in thread
From: James Tai [戴志峰] @ 2023-12-07 5:59 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Hi Krzysztof,
>>
>> misc_irq_mux: misc_irq_mux@80 {
>> compatible = "realtek,rtd1619b-intc-misc";
>> reg = <0x00 0x80>;
>> interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
>> <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
>> interrupt-controller;
>> #address-cells = <0>;
>> #interrupt-cells = <1>;
>> };
>
>So you have strictly defined number of interrupts and the actual interrupts per
>variant.
>
Yes, I have defined them.
>>
>>>
>>> Look at all other bindings covering multiple devices and their
>>> clocks/interrupts/interconnects/reg etc.
>>
>> May I adopt the approach used in this YAML for my case?
>> https://www.kernel.org/doc/Documentation/devicetree/bindings/timer/all
>> winner%2Csun4i-a10-timer.yaml
>
>
>I am asking for this since few emails.
>
>Look:
>"Anyway, you must describe the items. Why this is not fixed but flexible?
>Hardware has different number of pins? That's unlikely."
>
It is fixed, and the hardware has the same number of pins.
Regards,
James
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-11-20 9:08 ` James Tai [戴志峰]
2023-12-02 16:18 ` James Tai [戴志峰]
@ 2023-12-02 16:39 ` James Tai [戴志峰]
1 sibling, 0 replies; 26+ messages in thread
From: James Tai [戴志峰] @ 2023-12-02 16:39 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Hi Krzysztof,
>>> diff --git
>>> a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1
>>> 3
>>> 19d-intc.yaml
>>> b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1
>>> 3
>>> 19d-intc.yaml
>>> new file mode 100644
>>> index 000000000000..75aba448baf7
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,
>>> +++ r
>>> +++ td1319d-intc.yaml
>>> @@ -0,0 +1,79 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>>> +---
>>> +$id:
>>> +http://devicetree.org/schemas/interrupt-controller/realtek,rtd1319d-
>>> +i
>>> +ntc.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Realtek DHC RTD1319D Interrupt Controller Device Tree
>>> +Bindings
>>> +
>>> +description:
>>> + This interrupt controller is a component of Realtek DHC RTD1319D
>>> +and
>>> + is designed to receive interrupts from peripheral devices.
>>> +
>>> + Each DHC SoC has two sets of interrupt controllers, each capable
>>> + of handling up to 32 interrupts.
>>> +
>>> +maintainers:
>>> + - James Tai <james.tai@realtek.com>
>>> +
>>> +allOf:
>>> + - $ref: /schemas/interrupt-controller.yaml#
>>> +
>>> +properties:
>>> + "#interrupt-cells":
>>> + const: 1
>>> +
>>> + compatible:
>>> + enum:
>>> + - realtek,rtd1319d-intc-iso
>>> + - realtek,rtd1319d-intc-misc
>>
>>So this is the same as the other one? Why it cannot be part of that one?
>
>I will consolidate these parts into a single file.
>
I initially believed that each platform needed its YAML file for documentation and specific configurations.
However, it appears that this isn't the case.
Regards,
James
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
2023-11-19 12:47 ` Krzysztof Kozlowski
2023-11-20 9:08 ` James Tai [戴志峰]
@ 2023-12-02 16:42 ` James Tai [戴志峰]
1 sibling, 0 replies; 26+ messages in thread
From: James Tai [戴志峰] @ 2023-12-02 16:42 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Hi Krzysztof,
>> +
>> +maintainers:
>> + - James Tai <james.tai@realtek.com>
>> +
>> +allOf:
>> + - $ref: /schemas/interrupt-controller.yaml#
>> +
>> +properties:
>> + "#interrupt-cells":
>> + const: 1
>> +
>> + compatible:
>> + enum:
>> + - realtek,rtd1325-intc-iso
>> + - realtek,rtd1325-intc-misc
>
>All my comments apply to all your bindings...
>
Okay, I will apply to all My bindings.
Regards,
James
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2 2/6] irqchip: Add interrupt controller support for Realtek DHC SoCs
2023-11-17 16:27 [PATCH v2 0/6] Initial support for the Realtek interrupt controller James Tai
2023-11-17 16:27 ` [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs James Tai
@ 2023-11-17 16:27 ` James Tai
2023-11-17 16:27 ` [PATCH v2 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver James Tai
` (3 subsequent siblings)
5 siblings, 0 replies; 26+ messages in thread
From: James Tai @ 2023-11-17 16:27 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, James Tai
Cc: linux-kernel, devicetree
Realtek DHC (Digital Home Center) SoCs share a common interrupt controller
design. This universal interrupt controller driver provides support for
various variants within the Realtek DHC SoC family.
Each DHC SoC features two sets of extended interrupt controllers, each
capable of handling up to 32 interrupts. These expansion controllers are
connected to the GIC (Generic Interrupt Controller).
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Marc Zyngier <maz@kernel.org>
CC: linux-kernel@vger.kernel.org
Signed-off-by: James Tai <james.tai@realtek.com>
---
v1 to v2 change:
- Fixed code style issues
- Removed the realtek_intc_set_affinity funcation
- Replaced spin_lock_irqsave with raw_spin_lock
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-intc-common.c | 192 ++++++++++++++++++++++
drivers/irqchip/irq-realtek-intc-common.h | 77 +++++++++
4 files changed, 274 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-intc-common.c
create mode 100644 drivers/irqchip/irq-realtek-intc-common.h
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f7149d0f3d45..267c3429b48d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -218,6 +218,10 @@ config RDA_INTC
bool
select IRQ_DOMAIN
+config REALTEK_DHC_INTC
+ tristate
+ select IRQ_DOMAIN
+
config RENESAS_INTC_IRQPIN
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index ffd945fe71aa..f6774af7fde2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o
obj-$(CONFIG_IXP4XX_IRQ) += irq-ixp4xx.o
obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o
+obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
diff --git a/drivers/irqchip/irq-realtek-intc-common.c b/drivers/irqchip/irq-realtek-intc-common.c
new file mode 100644
index 000000000000..f701d9e7d141
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-intc-common.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek DHC SoCs interrupt controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "irq-realtek-intc-common.h"
+
+struct realtek_intc_data;
+
+static inline unsigned int realtek_intc_get_ints(struct realtek_intc_data *data)
+{
+ return readl(data->base + data->info->isr_offset);
+}
+
+static inline void realtek_intc_clear_ints_bit(struct realtek_intc_data *data, int bit)
+{
+ writel(BIT(bit) & ~1, data->base + data->info->isr_offset);
+}
+
+static inline unsigned int realtek_intc_get_inte(struct realtek_intc_data *data)
+{
+ unsigned int val;
+
+ raw_spin_lock(&data->lock);
+ val = readl(data->base + data->info->scpu_int_en_offset);
+ raw_spin_unlock(&data->lock);
+
+ return val;
+}
+
+static void realtek_intc_handler(struct irq_desc *desc)
+{
+ struct realtek_intc_subset_data *subset_data = irq_desc_get_handler_data(desc);
+ struct realtek_intc_data *data = subset_data->common;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ u32 ints, inte, mask;
+ int irq;
+
+ chained_irq_enter(chip, desc);
+
+ ints = realtek_intc_get_ints(data) & subset_data->cfg->ints_mask;
+ inte = realtek_intc_get_inte(data);
+
+ while (ints) {
+ irq = __ffs(ints);
+ ints &= ~BIT(irq);
+
+ mask = data->info->isr_to_scpu_int_en_mask[irq];
+ if (mask != IRQ_ALWAYS_ENABLED && !(inte & mask))
+ continue;
+
+ generic_handle_irq(irq_find_mapping(data->domain, irq));
+ realtek_intc_clear_ints_bit(data, irq);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void realtek_intc_mask_irq(struct irq_data *data)
+{
+ struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(data);
+
+ writel(BIT(data->hwirq), intc_data->base + intc_data->info->isr_offset);
+}
+
+static void realtek_intc_unmask_irq(struct irq_data *data)
+{
+ struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(data);
+
+ writel(BIT(data->hwirq), intc_data->base + intc_data->info->umsk_isr_offset);
+}
+
+static void realtek_intc_enable_irq(struct irq_data *data)
+{
+ struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(data);
+ u32 scpu_int_en, mask;
+
+ mask = intc_data->info->isr_to_scpu_int_en_mask[data->hwirq];
+ if (!mask)
+ return;
+
+ raw_spin_lock(&intc_data->lock);
+ scpu_int_en = readl(intc_data->base + intc_data->info->scpu_int_en_offset);
+ scpu_int_en |= mask;
+ writel(scpu_int_en, intc_data->base + intc_data->info->umsk_isr_offset);
+ raw_spin_unlock(&intc_data->lock);
+}
+
+static void realtek_intc_disable_irq(struct irq_data *data)
+{
+ struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(data);
+ u32 scpu_int_en, mask;
+
+ mask = intc_data->info->isr_to_scpu_int_en_mask[data->hwirq];
+ if (!mask)
+ return;
+
+ raw_spin_lock(&intc_data->lock);
+ scpu_int_en = readl(intc_data->base + intc_data->info->scpu_int_en_offset);
+ scpu_int_en &= ~mask;
+ writel(scpu_int_en, intc_data->base + intc_data->info->umsk_isr_offset);
+ raw_spin_unlock(&intc_data->lock);
+}
+
+static struct irq_chip realtek_intc_chip = {
+ .name = "realtek-intc",
+ .irq_mask = realtek_intc_mask_irq,
+ .irq_unmask = realtek_intc_unmask_irq,
+ .irq_enable = realtek_intc_enable_irq,
+ .irq_disable = realtek_intc_disable_irq,
+};
+
+static int realtek_intc_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+ struct realtek_intc_data *data = d->host_data;
+
+ irq_set_chip_and_handler(irq, &realtek_intc_chip, handle_level_irq);
+ irq_set_chip_data(irq, data);
+ irq_set_probe(irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops realtek_intc_domain_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = realtek_intc_domain_map,
+};
+
+static int realtek_intc_subset(struct device_node *node, struct realtek_intc_data *data, int index)
+{
+ struct realtek_intc_subset_data *subset_data = &data->subset_data[index];
+ const struct realtek_intc_subset_cfg *cfg = &data->info->cfg[index];
+ int irq;
+
+ irq = irq_of_parse_and_map(node, index);
+ if (irq <= 0)
+ return irq;
+
+ subset_data->common = data;
+ subset_data->cfg = cfg;
+ subset_data->parent_irq = irq;
+ irq_set_chained_handler_and_data(irq, realtek_intc_handler, subset_data);
+
+ return 0;
+}
+
+int realtek_intc_probe(struct platform_device *pdev, const struct realtek_intc_info *info)
+{
+ struct realtek_intc_data *data;
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ int ret, i;
+
+ data = devm_kzalloc(dev, struct_size(data, subset_data, info->cfg_num), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->base = of_iomap(node, 0);
+ if (!data->base)
+ return -ENOMEM;
+
+ data->info = info;
+
+ raw_spin_lock_init(&data->lock);
+
+ data->domain = irq_domain_add_linear(node, 32, &realtek_intc_domain_ops, data);
+ if (!data->domain)
+ return -ENOMEM;
+
+ data->subset_data_num = info->cfg_num;
+ for (i = 0; i < info->cfg_num; i++) {
+ ret = realtek_intc_subset(node, data, i);
+ WARN(ret, "failed to init subset %d: %d", i, ret);
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(pdev, data);
+
+ return 0;
+}
+EXPORT_SYMBOL(realtek_intc_probe);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek DHC SoC Interrupt Controller Driver");
diff --git a/drivers/irqchip/irq-realtek-intc-common.h b/drivers/irqchip/irq-realtek-intc-common.h
new file mode 100644
index 000000000000..38be116dba60
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-intc-common.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#ifndef _IRQ_REALTEK_COMMON_H
+#define _IRQ_REALTEK_COMMON_H
+
+#include <linux/bits.h>
+#include <linux/limits.h>
+#include <linux/hwspinlock.h>
+
+/**
+ * realtek_intc_subset_cfg - subset interrupt mask
+ * @ints_mask: inetrrupt mask
+ */
+struct realtek_intc_subset_cfg {
+ unsigned int ints_mask;
+};
+
+/**
+ * realtek_intc_info - interrupt controller data.
+ * @isr_offset: interrupt status register offset.
+ * @umsk_isr_offset: unmask interrupt status register offset.
+ * @scpu_int_en_offset: interrupt enable register offset.
+ * @cfg: cfg of the subset.
+ * @cfg_num: number of cfg.
+ */
+struct realtek_intc_info {
+ const struct realtek_intc_subset_cfg *cfg;
+ unsigned int isr_offset;
+ unsigned int umsk_isr_offset;
+ unsigned int scpu_int_en_offset;
+ const u32 *isr_to_scpu_int_en_mask;
+ int cfg_num;
+};
+
+/**
+ * realtek_intc_subset_data - handler of a interrupt source only handles ints
+ * bits in the mask.
+ * @cfg: cfg of the subset.
+ * @common: common data.
+ * @parent_irq: interrupt source.
+ */
+struct realtek_intc_subset_data {
+ const struct realtek_intc_subset_cfg *cfg;
+ struct realtek_intc_data *common;
+ int parent_irq;
+};
+
+/**
+ * realtek_intc_data - configuration data for realtek interrupt controller driver.
+ * @base: base of interrupt register
+ * @info: info of intc
+ * @domain: interrupt domain
+ * @lock: lock
+ * @saved_en: status of interrupt enable
+ * @subset_data_num: number of subset data
+ * @subset_data: subset data
+ */
+struct realtek_intc_data {
+ void __iomem *base;
+ const struct realtek_intc_info *info;
+ struct irq_domain *domain;
+ struct raw_spinlock lock;
+ unsigned int saved_en;
+ int subset_data_num;
+ struct realtek_intc_subset_data subset_data[];
+};
+
+#define IRQ_ALWAYS_ENABLED U32_MAX
+#define DISABLE_INTC (0)
+#define CLEAN_INTC_STATUS GENMASK(31, 1)
+
+int realtek_intc_probe(struct platform_device *pdev, const struct realtek_intc_info *info);
+
+#endif /* _IRQ_REALTEK_COMMON_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v2 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver
2023-11-17 16:27 [PATCH v2 0/6] Initial support for the Realtek interrupt controller James Tai
2023-11-17 16:27 ` [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs James Tai
2023-11-17 16:27 ` [PATCH v2 2/6] irqchip: Add interrupt controller " James Tai
@ 2023-11-17 16:27 ` James Tai
2023-11-20 16:18 ` Dan Carpenter
2024-01-03 9:45 ` Dan Carpenter
2023-11-17 16:27 ` [PATCH v2 4/6] irqchip: Introduce RTD1319D " James Tai
` (2 subsequent siblings)
5 siblings, 2 replies; 26+ messages in thread
From: James Tai @ 2023-11-17 16:27 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, James Tai
Cc: linux-kernel, devicetree
Add support for the RTD1319 platform.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202311061208.hJmxGqym-lkp@intel.com/
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Marc Zyngier <maz@kernel.org>
CC: linux-kernel@vger.kernel.org
Signed-off-by: James Tai <james.tai@realtek.com>
---
v1 to v2 change:
- Resolved kernel test robot build warnings
- Replaced magic number with macro
- Fixed code style issues
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-rtd1319.c | 218 ++++++++++++++++++++++++++
3 files changed, 225 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-rtd1319.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 267c3429b48d..05856ce885fa 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -222,6 +222,12 @@ config REALTEK_DHC_INTC
tristate
select IRQ_DOMAIN
+config REALTEK_RTD1319_INTC
+ tristate "Realtek RTD1319 interrupt controller"
+ select REALTEK_DHC_INTC
+ help
+ Support for Realtek RTD1319 Interrupt Controller.
+
config RENESAS_INTC_IRQPIN
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index f6774af7fde2..6a2650b0a924 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_IXP4XX_IRQ) += irq-ixp4xx.o
obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o
obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o
+obj-$(CONFIG_REALTEK_RTD1319_INTC) += irq-realtek-rtd1319.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
diff --git a/drivers/irqchip/irq-realtek-rtd1319.c b/drivers/irqchip/irq-realtek-rtd1319.c
new file mode 100644
index 000000000000..23c13c218b04
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-rtd1319.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1319 interrupt controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "irq-realtek-intc-common.h"
+
+#define ISO_NORMAL_MASK 0xffffcffe
+#define ISO_RTC_MASK 0x00003001
+#define MISC_NMI_WDT_MASK 0x00000004
+#define MISC_NORMAL_MASK 0xffffc0d2
+#define MISC_UART1_MASK 0x00000028
+#define MISC_UART2_MASK 0x00002100
+
+#define ISO_ISR_EN_OFFSET 0x40
+#define ISO_ISR_OFFSET 0
+#define ISO_ISR_UMSK_OFFSET 0x4
+#define MISC_ISR_EN_OFFSET 0x80
+#define MISC_ISR_OFFSET 0xc
+#define MISC_ISR_UMSK_OFFSET 0x8
+
+enum rtd1319_iso_isr_bits {
+ RTD1319_ISO_ISR_TC3_SHIFT = 1,
+ RTD1319_ISO_ISR_UR0_SHIFT = 2,
+ RTD1319_ISO_ISR_LSADC0_SHIFT = 3,
+ RTD1319_ISO_ISR_IRDA_SHIFT = 5,
+ RTD1319_ISO_ISR_SPI1_SHIFT = 6,
+ RTD1319_ISO_ISR_WDOG_NMI_SHIFT = 7,
+ RTD1319_ISO_ISR_I2C0_SHIFT = 8,
+ RTD1319_ISO_ISR_TC4_SHIFT = 9,
+ RTD1319_ISO_ISR_TC7_SHIFT = 10,
+ RTD1319_ISO_ISR_I2C1_SHIFT = 11,
+ RTD1319_ISO_ISR_RTC_HSEC_SHIFT = 12,
+ RTD1319_ISO_ISR_RTC_ALARM_SHIFT = 13,
+ RTD1319_ISO_ISR_GPIOA_SHIFT = 19,
+ RTD1319_ISO_ISR_GPIODA_SHIFT = 20,
+ RTD1319_ISO_ISR_ISO_MISC_SHIFT = 21,
+ RTD1319_ISO_ISR_CBUS_SHIFT = 22,
+ RTD1319_ISO_ISR_ETN_SHIFT = 23,
+ RTD1319_ISO_ISR_USB_HOST_SHIFT = 24,
+ RTD1319_ISO_ISR_USB_U3_DRD_SHIFT = 25,
+ RTD1319_ISO_ISR_USB_U2_DRD_SHIFT = 26,
+ RTD1319_ISO_ISR_PORB_HV_SHIFT = 28,
+ RTD1319_ISO_ISR_PORB_DV_SHIFT = 29,
+ RTD1319_ISO_ISR_PORB_AV_SHIFT = 30,
+ RTD1319_ISO_ISR_I2C1_REQ_SHIFT = 31,
+};
+
+static const u32 rtd1319_iso_isr_to_scpu_int_en_mask[32] = {
+ [RTD1319_ISO_ISR_SPI1_SHIFT] = BIT(1),
+ [RTD1319_ISO_ISR_UR0_SHIFT] = BIT(2),
+ [RTD1319_ISO_ISR_LSADC0_SHIFT] = BIT(3),
+ [RTD1319_ISO_ISR_IRDA_SHIFT] = BIT(5),
+ [RTD1319_ISO_ISR_I2C0_SHIFT] = BIT(8),
+ [RTD1319_ISO_ISR_I2C1_SHIFT] = BIT(11),
+ [RTD1319_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12),
+ [RTD1319_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13),
+ [RTD1319_ISO_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1319_ISO_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1319_ISO_ISR_PORB_HV_SHIFT] = BIT(28),
+ [RTD1319_ISO_ISR_PORB_DV_SHIFT] = BIT(29),
+ [RTD1319_ISO_ISR_PORB_AV_SHIFT] = BIT(30),
+ [RTD1319_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31),
+};
+
+enum rtd1319_misc_isr_bits {
+ RTD1319_ISR_WDOG_NMI_SHIFT = 2,
+ RTD1319_ISR_UR1_SHIFT = 3,
+ RTD1319_ISR_TC5_SHIFT = 4,
+ RTD1319_ISR_UR1_TO_SHIFT = 5,
+ RTD1319_ISR_TC0_SHIFT = 6,
+ RTD1319_ISR_TC1_SHIFT = 7,
+ RTD1319_ISR_UR2_SHIFT = 8,
+ RTD1319_ISR_RTC_HSEC_SHIFT = 9,
+ RTD1319_ISR_RTC_MIN_SHIFT = 10,
+ RTD1319_ISR_RTC_HOUR_SHIFT = 11,
+ RTD1319_ISR_RTC_DATE_SHIFT = 12,
+ RTD1319_ISR_UR2_TO_SHIFT = 13,
+ RTD1319_ISR_I2C5_SHIFT = 14,
+ RTD1319_ISR_I2C3_SHIFT = 23,
+ RTD1319_ISR_SC0_SHIFT = 24,
+ RTD1319_ISR_SC1_SHIFT = 25,
+ RTD1319_ISR_SPI_SHIFT = 27,
+ RTD1319_ISR_FAN_SHIFT = 29,
+};
+
+static const u32 rtd1319_misc_isr_to_scpu_int_en_mask[32] = {
+ [RTD1319_ISR_UR1_SHIFT] = BIT(3),
+ [RTD1319_ISR_UR1_TO_SHIFT] = BIT(5),
+ [RTD1319_ISR_UR2_TO_SHIFT] = BIT(6),
+ [RTD1319_ISR_UR2_SHIFT] = BIT(7),
+ [RTD1319_ISR_RTC_MIN_SHIFT] = BIT(10),
+ [RTD1319_ISR_RTC_HOUR_SHIFT] = BIT(11),
+ [RTD1319_ISR_RTC_DATE_SHIFT] = BIT(12),
+ [RTD1319_ISR_I2C5_SHIFT] = BIT(14),
+ [RTD1319_ISR_SC0_SHIFT] = BIT(24),
+ [RTD1319_ISR_SC1_SHIFT] = BIT(25),
+ [RTD1319_ISR_SPI_SHIFT] = BIT(27),
+ [RTD1319_ISR_I2C3_SHIFT] = BIT(28),
+ [RTD1319_ISR_FAN_SHIFT] = BIT(29),
+ [RTD1319_ISR_WDOG_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+};
+
+static struct realtek_intc_subset_cfg rtd1319_intc_iso_cfgs[] = {
+ { ISO_NORMAL_MASK, },
+ { ISO_RTC_MASK, },
+};
+
+static const struct realtek_intc_info rtd1319_intc_iso_info = {
+ .isr_offset = ISO_ISR_OFFSET,
+ .umsk_isr_offset = ISO_ISR_UMSK_OFFSET,
+ .scpu_int_en_offset = ISO_ISR_EN_OFFSET,
+ .isr_to_scpu_int_en_mask = rtd1319_iso_isr_to_scpu_int_en_mask,
+ .cfg = rtd1319_intc_iso_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1319_intc_iso_cfgs),
+};
+
+static struct realtek_intc_subset_cfg rtd1319_intc_misc_cfgs[] = {
+ { MISC_NORMAL_MASK, },
+ { MISC_NMI_WDT_MASK, },
+ { MISC_UART1_MASK, },
+ { MISC_UART2_MASK, },
+};
+
+static const struct realtek_intc_info rtd1319_intc_misc_info = {
+ .isr_offset = MISC_ISR_OFFSET,
+ .umsk_isr_offset = MISC_ISR_UMSK_OFFSET,
+ .scpu_int_en_offset = MISC_ISR_EN_OFFSET,
+ .isr_to_scpu_int_en_mask = rtd1319_misc_isr_to_scpu_int_en_mask,
+ .cfg = rtd1319_intc_misc_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1319_intc_misc_cfgs),
+};
+
+static const struct of_device_id realtek_intc_rtd1319_dt_matches[] = {
+ {
+ .compatible = "realtek,rtd1319-intc-iso",
+ .data = &rtd1319_intc_iso_info,
+ }, {
+ .compatible = "realtek,rtd1319-intc-misc",
+ .data = &rtd1319_intc_misc_info,
+ },
+ { /* sentinel */ }
+};
+
+static int realtek_intc_rtd1319_suspend(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ data->saved_en = readl(data->base + info->scpu_int_en_offset);
+
+ writel(DISABLE_INTC, data->base + info->scpu_int_en_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+
+ return 0;
+}
+
+static int realtek_intc_rtd1319_resume(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+ writel(data->saved_en, data->base + info->scpu_int_en_offset);
+
+ return 0;
+}
+
+static const struct dev_pm_ops realtek_intc_rtd1319_pm_ops = {
+ .suspend_noirq = realtek_intc_rtd1319_suspend,
+ .resume_noirq = realtek_intc_rtd1319_resume,
+};
+
+static int rtd1319_intc_probe(struct platform_device *pdev)
+{
+ const struct realtek_intc_info *info;
+
+ info = of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -EINVAL;
+
+ return realtek_intc_probe(pdev, info);
+}
+
+static struct platform_driver realtek_intc_rtd1319_driver = {
+ .probe = rtd1319_intc_probe,
+ .driver = {
+ .name = "realtek_intc_rtd1319",
+ .of_match_table = realtek_intc_rtd1319_dt_matches,
+ .suppress_bind_attrs = true,
+ .pm = &realtek_intc_rtd1319_pm_ops,
+ },
+};
+
+static int __init realtek_intc_rtd1319_init(void)
+{
+ return platform_driver_register(&realtek_intc_rtd1319_driver);
+}
+core_initcall(realtek_intc_rtd1319_init);
+
+static void __exit realtek_intc_rtd1319_exit(void)
+{
+ platform_driver_unregister(&realtek_intc_rtd1319_driver);
+}
+module_exit(realtek_intc_rtd1319_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek RTD1319 Interrupt Controller Driver");
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v2 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver
2023-11-17 16:27 ` [PATCH v2 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver James Tai
@ 2023-11-20 16:18 ` Dan Carpenter
2023-11-22 8:39 ` James Tai [戴志峰]
2024-01-03 9:45 ` Dan Carpenter
1 sibling, 1 reply; 26+ messages in thread
From: Dan Carpenter @ 2023-11-20 16:18 UTC (permalink / raw)
To: oe-kbuild, James Tai, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: lkp, oe-kbuild-all, linux-kernel, devicetree
Hi James,
kernel test robot noticed the following build warnings:
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/James-Tai/dt-bindings-interrupt-controller-Add-support-for-Realtek-DHC-SoCs/20231118-003036
base: tip/irq/core
patch link: https://lore.kernel.org/r/20231117162709.1096585-4-james.tai%40realtek.com
patch subject: [PATCH v2 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver
config: nios2-randconfig-r081-20231120 (https://download.01.org/0day-ci/archive/20231120/202311201929.2FpvMRlg-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20231120/202311201929.2FpvMRlg-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202311201929.2FpvMRlg-lkp@intel.com/
smatch warnings:
drivers/irqchip/irq-realtek-intc-common.c:179 realtek_intc_probe() warn: ignoring unreachable code.
drivers/irqchip/irq-realtek-intc-common.c:187 realtek_intc_probe() warn: 'data->base' from of_iomap() not released on lines: 176,182.
vim +179 drivers/irqchip/irq-realtek-intc-common.c
40e5ff4eaef72b James Tai 2023-11-18 155 int realtek_intc_probe(struct platform_device *pdev, const struct realtek_intc_info *info)
40e5ff4eaef72b James Tai 2023-11-18 156 {
40e5ff4eaef72b James Tai 2023-11-18 157 struct realtek_intc_data *data;
40e5ff4eaef72b James Tai 2023-11-18 158 struct device *dev = &pdev->dev;
40e5ff4eaef72b James Tai 2023-11-18 159 struct device_node *node = dev->of_node;
40e5ff4eaef72b James Tai 2023-11-18 160 int ret, i;
40e5ff4eaef72b James Tai 2023-11-18 161
40e5ff4eaef72b James Tai 2023-11-18 162 data = devm_kzalloc(dev, struct_size(data, subset_data, info->cfg_num), GFP_KERNEL);
40e5ff4eaef72b James Tai 2023-11-18 163 if (!data)
40e5ff4eaef72b James Tai 2023-11-18 164 return -ENOMEM;
40e5ff4eaef72b James Tai 2023-11-18 165
40e5ff4eaef72b James Tai 2023-11-18 166 data->base = of_iomap(node, 0);
40e5ff4eaef72b James Tai 2023-11-18 167 if (!data->base)
40e5ff4eaef72b James Tai 2023-11-18 168 return -ENOMEM;
40e5ff4eaef72b James Tai 2023-11-18 169
40e5ff4eaef72b James Tai 2023-11-18 170 data->info = info;
40e5ff4eaef72b James Tai 2023-11-18 171
40e5ff4eaef72b James Tai 2023-11-18 172 raw_spin_lock_init(&data->lock);
40e5ff4eaef72b James Tai 2023-11-18 173
40e5ff4eaef72b James Tai 2023-11-18 174 data->domain = irq_domain_add_linear(node, 32, &realtek_intc_domain_ops, data);
40e5ff4eaef72b James Tai 2023-11-18 175 if (!data->domain)
40e5ff4eaef72b James Tai 2023-11-18 176 return -ENOMEM;
40e5ff4eaef72b James Tai 2023-11-18 177
40e5ff4eaef72b James Tai 2023-11-18 178 data->subset_data_num = info->cfg_num;
40e5ff4eaef72b James Tai 2023-11-18 @179 for (i = 0; i < info->cfg_num; i++) {
40e5ff4eaef72b James Tai 2023-11-18 180 ret = realtek_intc_subset(node, data, i);
40e5ff4eaef72b James Tai 2023-11-18 181 WARN(ret, "failed to init subset %d: %d", i, ret);
40e5ff4eaef72b James Tai 2023-11-18 182 return -ENOMEM;
This loop just returns -ENOMEM. Missing if statement?
No clean up either. Needs to release resources before returning.
40e5ff4eaef72b James Tai 2023-11-18 183 }
40e5ff4eaef72b James Tai 2023-11-18 184
40e5ff4eaef72b James Tai 2023-11-18 185 platform_set_drvdata(pdev, data);
40e5ff4eaef72b James Tai 2023-11-18 186
40e5ff4eaef72b James Tai 2023-11-18 @187 return 0;
40e5ff4eaef72b James Tai 2023-11-18 188 }
40e5ff4eaef72b James Tai 2023-11-18 189 EXPORT_SYMBOL(realtek_intc_probe);
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH v2 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver
2023-11-20 16:18 ` Dan Carpenter
@ 2023-11-22 8:39 ` James Tai [戴志峰]
0 siblings, 0 replies; 26+ messages in thread
From: James Tai [戴志峰] @ 2023-11-22 8:39 UTC (permalink / raw)
To: Dan Carpenter, oe-kbuild@lists.linux.dev, Thomas Gleixner,
Marc Zyngier, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: lkp@intel.com, oe-kbuild-all@lists.linux.dev,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Hi Dan,
>smatch warnings:
>drivers/irqchip/irq-realtek-intc-common.c:179 realtek_intc_probe() warn:
>ignoring unreachable code.
>drivers/irqchip/irq-realtek-intc-common.c:187 realtek_intc_probe() warn:
>'data->base' from of_iomap() not released on lines: 176,182.
>
>vim +179 drivers/irqchip/irq-realtek-intc-common.c
>
>40e5ff4eaef72b James Tai 2023-11-18 155 int realtek_intc_probe(struct
>platform_device *pdev, const struct realtek_intc_info *info) 40e5ff4eaef72b
>James Tai 2023-11-18 156 {
>40e5ff4eaef72b James Tai 2023-11-18 157 struct realtek_intc_data
>*data;
>40e5ff4eaef72b James Tai 2023-11-18 158 struct device *dev =
>&pdev->dev;
>40e5ff4eaef72b James Tai 2023-11-18 159 struct device_node *node
>= dev->of_node;
>40e5ff4eaef72b James Tai 2023-11-18 160 int ret, i;
>40e5ff4eaef72b James Tai 2023-11-18 161
>40e5ff4eaef72b James Tai 2023-11-18 162 data = devm_kzalloc(dev,
>struct_size(data, subset_data, info->cfg_num), GFP_KERNEL);
>40e5ff4eaef72b James Tai 2023-11-18 163 if (!data)
>40e5ff4eaef72b James Tai 2023-11-18 164 return
>-ENOMEM;
>40e5ff4eaef72b James Tai 2023-11-18 165
>40e5ff4eaef72b James Tai 2023-11-18 166 data->base =
>of_iomap(node, 0);
>40e5ff4eaef72b James Tai 2023-11-18 167 if (!data->base)
>40e5ff4eaef72b James Tai 2023-11-18 168 return
>-ENOMEM;
>40e5ff4eaef72b James Tai 2023-11-18 169
>40e5ff4eaef72b James Tai 2023-11-18 170 data->info = info;
>40e5ff4eaef72b James Tai 2023-11-18 171
>40e5ff4eaef72b James Tai 2023-11-18 172
>raw_spin_lock_init(&data->lock);
>40e5ff4eaef72b James Tai 2023-11-18 173
>40e5ff4eaef72b James Tai 2023-11-18 174 data->domain =
>irq_domain_add_linear(node, 32, &realtek_intc_domain_ops, data);
>40e5ff4eaef72b James Tai 2023-11-18 175 if (!data->domain)
>40e5ff4eaef72b James Tai 2023-11-18 176 return
>-ENOMEM;
>40e5ff4eaef72b James Tai 2023-11-18 177
>40e5ff4eaef72b James Tai 2023-11-18 178 data->subset_data_num
>= info->cfg_num;
>40e5ff4eaef72b James Tai 2023-11-18 @179 for (i = 0; i <
>info->cfg_num; i++) {
>40e5ff4eaef72b James Tai 2023-11-18 180 ret =
>realtek_intc_subset(node, data, i);
>40e5ff4eaef72b James Tai 2023-11-18 181 WARN(ret,
>"failed to init subset %d: %d", i, ret);
>40e5ff4eaef72b James Tai 2023-11-18 182 return
>-ENOMEM;
>
>This loop just returns -ENOMEM. Missing if statement?
>No clean up either. Needs to release resources before returning.
I will fix it in next patches.
Thank you for your feedback.
Regards,
James
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver
2023-11-17 16:27 ` [PATCH v2 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver James Tai
2023-11-20 16:18 ` Dan Carpenter
@ 2024-01-03 9:45 ` Dan Carpenter
1 sibling, 0 replies; 26+ messages in thread
From: Dan Carpenter @ 2024-01-03 9:45 UTC (permalink / raw)
To: oe-kbuild, James Tai, Thomas Gleixner, Marc Zyngier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: lkp, oe-kbuild-all, linux-kernel, devicetree
Hi James,
kernel test robot noticed the following build warnings:
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/James-Tai/dt-bindings-interrupt-controller-Add-support-for-Realtek-DHC-SoCs/20231118-003036
base: tip/irq/core
patch link: https://lore.kernel.org/r/20231117162709.1096585-4-james.tai%40realtek.com
patch subject: [PATCH v2 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver
config: nios2-randconfig-r081-20231120 (https://download.01.org/0day-ci/archive/20231217/202312172011.8iKGuYB9-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 13.2.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202312172011.8iKGuYB9-lkp@intel.com/
smatch warnings:
drivers/irqchip/irq-realtek-intc-common.c:179 realtek_intc_probe() warn: ignoring unreachable code.
drivers/irqchip/irq-realtek-intc-common.c:187 realtek_intc_probe() warn: 'data->base' from of_iomap() not released on lines: 176,182.
vim +179 drivers/irqchip/irq-realtek-intc-common.c
40e5ff4eaef72b James Tai 2023-11-18 155 int realtek_intc_probe(struct platform_device *pdev, const struct realtek_intc_info *info)
40e5ff4eaef72b James Tai 2023-11-18 156 {
40e5ff4eaef72b James Tai 2023-11-18 157 struct realtek_intc_data *data;
40e5ff4eaef72b James Tai 2023-11-18 158 struct device *dev = &pdev->dev;
40e5ff4eaef72b James Tai 2023-11-18 159 struct device_node *node = dev->of_node;
40e5ff4eaef72b James Tai 2023-11-18 160 int ret, i;
40e5ff4eaef72b James Tai 2023-11-18 161
40e5ff4eaef72b James Tai 2023-11-18 162 data = devm_kzalloc(dev, struct_size(data, subset_data, info->cfg_num), GFP_KERNEL);
40e5ff4eaef72b James Tai 2023-11-18 163 if (!data)
40e5ff4eaef72b James Tai 2023-11-18 164 return -ENOMEM;
40e5ff4eaef72b James Tai 2023-11-18 165
40e5ff4eaef72b James Tai 2023-11-18 166 data->base = of_iomap(node, 0);
40e5ff4eaef72b James Tai 2023-11-18 167 if (!data->base)
40e5ff4eaef72b James Tai 2023-11-18 168 return -ENOMEM;
40e5ff4eaef72b James Tai 2023-11-18 169
40e5ff4eaef72b James Tai 2023-11-18 170 data->info = info;
40e5ff4eaef72b James Tai 2023-11-18 171
40e5ff4eaef72b James Tai 2023-11-18 172 raw_spin_lock_init(&data->lock);
40e5ff4eaef72b James Tai 2023-11-18 173
40e5ff4eaef72b James Tai 2023-11-18 174 data->domain = irq_domain_add_linear(node, 32, &realtek_intc_domain_ops, data);
40e5ff4eaef72b James Tai 2023-11-18 175 if (!data->domain)
40e5ff4eaef72b James Tai 2023-11-18 176 return -ENOMEM;
40e5ff4eaef72b James Tai 2023-11-18 177
40e5ff4eaef72b James Tai 2023-11-18 178 data->subset_data_num = info->cfg_num;
40e5ff4eaef72b James Tai 2023-11-18 @179 for (i = 0; i < info->cfg_num; i++) {
40e5ff4eaef72b James Tai 2023-11-18 180 ret = realtek_intc_subset(node, data, i);
40e5ff4eaef72b James Tai 2023-11-18 181 WARN(ret, "failed to init subset %d: %d", i, ret);
if statement missing
40e5ff4eaef72b James Tai 2023-11-18 182 return -ENOMEM;
40e5ff4eaef72b James Tai 2023-11-18 183 }
40e5ff4eaef72b James Tai 2023-11-18 184
40e5ff4eaef72b James Tai 2023-11-18 185 platform_set_drvdata(pdev, data);
40e5ff4eaef72b James Tai 2023-11-18 186
40e5ff4eaef72b James Tai 2023-11-18 @187 return 0;
40e5ff4eaef72b James Tai 2023-11-18 188 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2 4/6] irqchip: Introduce RTD1319D support using the Realtek common interrupt controller driver
2023-11-17 16:27 [PATCH v2 0/6] Initial support for the Realtek interrupt controller James Tai
` (2 preceding siblings ...)
2023-11-17 16:27 ` [PATCH v2 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver James Tai
@ 2023-11-17 16:27 ` James Tai
2023-11-17 16:27 ` [PATCH v2 5/6] irqchip: Introduce RTD1325 " James Tai
2023-11-17 16:27 ` [PATCH v2 6/6] irqchip: Introduce RTD1619B " James Tai
5 siblings, 0 replies; 26+ messages in thread
From: James Tai @ 2023-11-17 16:27 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, James Tai
Cc: linux-kernel, devicetree
Add support for the RTD1319D platform.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202311061137.FRpoKwcm-lkp@intel.com/
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Marc Zyngier <maz@kernel.org>
CC: linux-kernel@vger.kernel.org
Signed-off-by: James Tai <james.tai@realtek.com>
---
v1 to v2 change:
- Resolved kernel test robot build warnings
- Replaced magic number with macro
- Fixed code style issues
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-rtd1319d.c | 227 +++++++++++++++++++++++++
3 files changed, 234 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-rtd1319d.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 05856ce885fa..c6552c513442 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -228,6 +228,12 @@ config REALTEK_RTD1319_INTC
help
Support for Realtek RTD1319 Interrupt Controller.
+config REALTEK_RTD1319D_INTC
+ tristate "Realtek RTD1319D interrupt controller"
+ select REALTEK_DHC_INTC
+ help
+ Support for Realtek RTD1319D Interrupt Controller.
+
config RENESAS_INTC_IRQPIN
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 6a2650b0a924..c8adaed4c1b2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o
obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o
obj-$(CONFIG_REALTEK_RTD1319_INTC) += irq-realtek-rtd1319.o
+obj-$(CONFIG_REALTEK_RTD1319D_INTC) += irq-realtek-rtd1319d.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
diff --git a/drivers/irqchip/irq-realtek-rtd1319d.c b/drivers/irqchip/irq-realtek-rtd1319d.c
new file mode 100644
index 000000000000..2a9c85a84dc9
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-rtd1319d.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1319D interrupt controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "irq-realtek-intc-common.h"
+
+#define ISO_NMI_WDT_MASK 0x08008090
+#define ISO_NORMAL_MASK 0xf7ff7f6e
+#define MISC_NORMAL_MASK 0xffe0ded6
+#define MISC_UART1_MASK 0x00000028
+#define MISC_UART2_MASK 0x00002100
+
+#define ISO_ISR_EN_OFFSET 0x40
+#define ISO_ISR_OFFSET 0
+#define ISO_ISR_UMSK_OFFSET 0x4
+#define MISC_ISR_EN_OFFSET 0x80
+#define MISC_ISR_OFFSET 0xc
+#define MISC_ISR_UMSK_OFFSET 0x8
+
+enum rtd1319d_iso_isr_bits {
+ RTD1319D_ISO_ISR_TC3_SHIFT = 1,
+ RTD1319D_ISO_ISR_UR0_SHIFT = 2,
+ RTD1319D_ISO_ISR_LSADC0_SHIFT = 3,
+ RTD1319D_ISO_ISR_WDOG1_NMI_SHIFT = 4,
+ RTD1319D_ISO_ISR_IRDA_SHIFT = 5,
+ RTD1319D_ISO_ISR_SPI1_SHIFT = 6,
+ RTD1319D_ISO_ISR_WDOG2_NMI_SHIFT = 7,
+ RTD1319D_ISO_ISR_I2C0_SHIFT = 8,
+ RTD1319D_ISO_ISR_TC4_SHIFT = 9,
+ RTD1319D_ISO_ISR_TC7_SHIFT = 10,
+ RTD1319D_ISO_ISR_I2C1_SHIFT = 11,
+ RTD1319D_ISO_ISR_HIFI_WAKEUP_SHIFT = 14,
+ RTD1319D_ISO_ISR_WDOG4_NMI_SHIFT = 15,
+ RTD1319D_ISO_ISR_TC8_SHIFT = 16,
+ RTD1319D_ISO_ISR_VFD_SHIFT = 17,
+ RTD1319D_ISO_ISR_VTC_SHIFT = 18,
+ RTD1319D_ISO_ISR_GPIOA_SHIFT = 19,
+ RTD1319D_ISO_ISR_GPIODA_SHIFT = 20,
+ RTD1319D_ISO_ISR_ISO_MISC_SHIFT = 21,
+ RTD1319D_ISO_ISR_CBUS_SHIFT = 22,
+ RTD1319D_ISO_ISR_ETN_SHIFT = 23,
+ RTD1319D_ISO_ISR_USB_HOST_SHIFT = 24,
+ RTD1319D_ISO_ISR_USB_U3_DRD_SHIFT = 25,
+ RTD1319D_ISO_ISR_USB_U2_DRD_SHIFT = 26,
+ RTD1319D_ISO_ISR_WDOG3_NMI_SHIFT = 27,
+ RTD1319D_ISO_ISR_PORB_HV_CEN_SHIFT = 28,
+ RTD1319D_ISO_ISR_PORB_DV_CEN_SHIFT = 29,
+ RTD1319D_ISO_ISR_PORB_AV_CEN_SHIFT = 30,
+ RTD1319D_ISO_ISR_I2C1_REQ_SHIFT = 31,
+};
+
+static const u32 rtd1319d_iso_isr_to_scpu_int_en_mask[32] = {
+ [RTD1319D_ISO_ISR_SPI1_SHIFT] = BIT(1),
+ [RTD1319D_ISO_ISR_UR0_SHIFT] = BIT(2),
+ [RTD1319D_ISO_ISR_LSADC0_SHIFT] = BIT(3),
+ [RTD1319D_ISO_ISR_IRDA_SHIFT] = BIT(5),
+ [RTD1319D_ISO_ISR_I2C0_SHIFT] = BIT(8),
+ [RTD1319D_ISO_ISR_I2C1_SHIFT] = BIT(11),
+ [RTD1319D_ISO_ISR_VFD_SHIFT] = BIT(17),
+ [RTD1319D_ISO_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1319D_ISO_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1319D_ISO_ISR_PORB_HV_CEN_SHIFT] = BIT(28),
+ [RTD1319D_ISO_ISR_PORB_DV_CEN_SHIFT] = BIT(29),
+ [RTD1319D_ISO_ISR_PORB_AV_CEN_SHIFT] = BIT(30),
+ [RTD1319D_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31),
+ [RTD1319D_ISO_ISR_WDOG1_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1319D_ISO_ISR_WDOG2_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1319D_ISO_ISR_WDOG3_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1319D_ISO_ISR_WDOG4_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+};
+
+enum rtd1319d_misc_isr_bits {
+ RTD1319D_ISR_UR1_SHIFT = 3,
+ RTD1319D_ISR_TC5_SHIFT = 4,
+ RTD1319D_ISR_UR1_TO_SHIFT = 5,
+ RTD1319D_ISR_TC0_SHIFT = 6,
+ RTD1319D_ISR_TC1_SHIFT = 7,
+ RTD1319D_ISR_UR2_SHIFT = 8,
+ RTD1319D_ISR_UR2_TO_SHIFT = 13,
+ RTD1319D_ISR_I2C5_SHIFT = 14,
+ RTD1319D_ISR_I2C4_SHIFT = 15,
+ RTD1319D_ISR_DRTC_HSEC_SHIFT = 16,
+ RTD1319D_ISR_DRTC_MIN_SHIFT = 17,
+ RTD1319D_ISR_DRTC_HOUR_SHIFT = 18,
+ RTD1319D_ISR_DRTC_DATE_SHIFT = 19,
+ RTD1319D_ISR_DRTC_ALARM_SHIFT = 20,
+ RTD1319D_ISR_I2C3_SHIFT = 23,
+ RTD1319D_ISR_SC0_SHIFT = 24,
+ RTD1319D_ISR_SC1_SHIFT = 25,
+ RTD1319D_ISR_SPI_SHIFT = 27,
+ RTD1319D_ISR_FAN_SHIFT = 29,
+};
+
+static const u32 rtd1319d_misc_isr_to_scpu_int_en_mask[32] = {
+ [RTD1319D_ISR_UR1_SHIFT] = BIT(3),
+ [RTD1319D_ISR_UR1_TO_SHIFT] = BIT(5),
+ [RTD1319D_ISR_UR2_TO_SHIFT] = BIT(6),
+ [RTD1319D_ISR_UR2_SHIFT] = BIT(7),
+ [RTD1319D_ISR_I2C5_SHIFT] = BIT(14),
+ [RTD1319D_ISR_I2C4_SHIFT] = BIT(15),
+ [RTD1319D_ISR_DRTC_HSEC_SHIFT] = BIT(16),
+ [RTD1319D_ISR_DRTC_MIN_SHIFT] = BIT(17),
+ [RTD1319D_ISR_DRTC_HOUR_SHIFT] = BIT(18),
+ [RTD1319D_ISR_DRTC_DATE_SHIFT] = BIT(19),
+ [RTD1319D_ISR_DRTC_ALARM_SHIFT] = BIT(20),
+ [RTD1319D_ISR_SC0_SHIFT] = BIT(24),
+ [RTD1319D_ISR_SC1_SHIFT] = BIT(25),
+ [RTD1319D_ISR_SPI_SHIFT] = BIT(27),
+ [RTD1319D_ISR_I2C3_SHIFT] = BIT(28),
+ [RTD1319D_ISR_FAN_SHIFT] = BIT(29),
+};
+
+static struct realtek_intc_subset_cfg rtd1319d_intc_iso_cfgs[] = {
+ { ISO_NORMAL_MASK, },
+ { ISO_NMI_WDT_MASK, },
+};
+
+static const struct realtek_intc_info rtd1319d_intc_iso_info = {
+ .isr_offset = ISO_ISR_OFFSET,
+ .umsk_isr_offset = ISO_ISR_UMSK_OFFSET,
+ .scpu_int_en_offset = ISO_ISR_EN_OFFSET,
+ .isr_to_scpu_int_en_mask = rtd1319d_iso_isr_to_scpu_int_en_mask,
+ .cfg = rtd1319d_intc_iso_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1319d_intc_iso_cfgs),
+};
+
+static struct realtek_intc_subset_cfg rtd1319d_intc_misc_cfgs[] = {
+ { MISC_NORMAL_MASK, },
+ { MISC_UART1_MASK, },
+ { MISC_UART2_MASK, },
+};
+
+static const struct realtek_intc_info rtd1319d_intc_misc_info = {
+ .isr_offset = MISC_ISR_OFFSET,
+ .umsk_isr_offset = MISC_ISR_UMSK_OFFSET,
+ .scpu_int_en_offset = MISC_ISR_EN_OFFSET,
+ .isr_to_scpu_int_en_mask = rtd1319d_misc_isr_to_scpu_int_en_mask,
+ .cfg = rtd1319d_intc_misc_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1319d_intc_misc_cfgs),
+};
+
+static const struct of_device_id realtek_intc_rtd1319d_dt_matches[] = {
+ {
+ .compatible = "realtek,rtd1319d-intc-iso",
+ .data = &rtd1319d_intc_iso_info,
+ }, {
+ .compatible = "realtek,rtd1319d-intc-misc",
+ .data = &rtd1319d_intc_misc_info,
+ },
+ { /* sentinel */ }
+};
+
+static int realtek_intc_rtd1319d_suspend(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ data->saved_en = readl(data->base + info->scpu_int_en_offset);
+
+ writel(DISABLE_INTC, data->base + info->scpu_int_en_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+
+ return 0;
+}
+
+static int realtek_intc_rtd1319d_resume(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+ writel(data->saved_en, data->base + info->scpu_int_en_offset);
+
+ return 0;
+}
+
+static const struct dev_pm_ops realtek_intc_rtd1319d_pm_ops = {
+ .suspend_noirq = realtek_intc_rtd1319d_suspend,
+ .resume_noirq = realtek_intc_rtd1319d_resume,
+};
+
+static int rtd1319d_intc_probe(struct platform_device *pdev)
+{
+ const struct realtek_intc_info *info;
+
+ info = of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -EINVAL;
+
+ return realtek_intc_probe(pdev, info);
+}
+
+static struct platform_driver realtek_intc_rtd1319d_driver = {
+ .probe = rtd1319d_intc_probe,
+ .driver = {
+ .name = "realtek_intc_rtd1319d",
+ .of_match_table = realtek_intc_rtd1319d_dt_matches,
+ .suppress_bind_attrs = true,
+ .pm = &realtek_intc_rtd1319d_pm_ops,
+ },
+};
+
+static int __init realtek_intc_rtd1319d_init(void)
+{
+ return platform_driver_register(&realtek_intc_rtd1319d_driver);
+}
+core_initcall(realtek_intc_rtd1319d_init);
+
+static void __exit realtek_intc_rtd1319d_exit(void)
+{
+ platform_driver_unregister(&realtek_intc_rtd1319d_driver);
+}
+module_exit(realtek_intc_rtd1319d_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek RTD1319D Interrupt Controller Driver");
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v2 5/6] irqchip: Introduce RTD1325 support using the Realtek common interrupt controller driver
2023-11-17 16:27 [PATCH v2 0/6] Initial support for the Realtek interrupt controller James Tai
` (3 preceding siblings ...)
2023-11-17 16:27 ` [PATCH v2 4/6] irqchip: Introduce RTD1319D " James Tai
@ 2023-11-17 16:27 ` James Tai
2023-11-17 16:27 ` [PATCH v2 6/6] irqchip: Introduce RTD1619B " James Tai
5 siblings, 0 replies; 26+ messages in thread
From: James Tai @ 2023-11-17 16:27 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, James Tai
Cc: linux-kernel, devicetree
Add support for the RTD1325 platform.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202311061408.qjl1jfVl-lkp@intel.com/
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Marc Zyngier <maz@kernel.org>
CC: linux-kernel@vger.kernel.org
Signed-off-by: James Tai <james.tai@realtek.com>
---
v1 to v2 change:
- Resolved kernel test robot build warnings
- Replaced magic number with macro
- Fixed code style issues
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-rtd1325.c | 227 ++++++++++++++++++++++++++
3 files changed, 234 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-rtd1325.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c6552c513442..65e2d67d1505 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -234,6 +234,12 @@ config REALTEK_RTD1319D_INTC
help
Support for Realtek RTD1319D Interrupt Controller.
+config REALTEK_RTD1325_INTC
+ tristate "Realtek RTD1325 interrupt controller"
+ select REALTEK_DHC_INTC
+ help
+ Support for Realtek RTD1325 Interrupt Controller.
+
config RENESAS_INTC_IRQPIN
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c8adaed4c1b2..eaa12928d60b 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o
obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o
obj-$(CONFIG_REALTEK_RTD1319_INTC) += irq-realtek-rtd1319.o
obj-$(CONFIG_REALTEK_RTD1319D_INTC) += irq-realtek-rtd1319d.o
+obj-$(CONFIG_REALTEK_RTD1325_INTC) += irq-realtek-rtd1325.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
diff --git a/drivers/irqchip/irq-realtek-rtd1325.c b/drivers/irqchip/irq-realtek-rtd1325.c
new file mode 100644
index 000000000000..7ff164795634
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-rtd1325.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1325 interrupt controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "irq-realtek-intc-common.h"
+
+#define ISO_NMI_WDT_MASK 0x08008090
+#define ISO_NORMAL_MASK 0xf7ff7f6e
+#define MISC_NORMAL_MASK 0xffe0ded6
+#define MISC_UART1_MASK 0x00000028
+#define MISC_UART2_MASK 0x00002100
+
+#define ISO_ISR_EN_OFFSET 0x40
+#define ISO_ISR_OFFSET 0
+#define ISO_ISR_UMSK_OFFSET 0x4
+#define MISC_ISR_EN_OFFSET 0x80
+#define MISC_ISR_OFFSET 0xc
+#define MISC_ISR_UMSK_OFFSET 0x8
+
+enum rtd1325_iso_isr_bits {
+ RTD1325_ISO_ISR_TC3_SHIFT = 1,
+ RTD1325_ISO_ISR_UR0_SHIFT = 2,
+ RTD1325_ISO_ISR_LSADC0_SHIFT = 3,
+ RTD1325_ISO_ISR_WDOG1_NMI_SHIFT = 4,
+ RTD1325_ISO_ISR_IRDA_SHIFT = 5,
+ RTD1325_ISO_ISR_SPI1_SHIFT = 6,
+ RTD1325_ISO_ISR_WDOG2_NMI_SHIFT = 7,
+ RTD1325_ISO_ISR_I2C0_SHIFT = 8,
+ RTD1325_ISO_ISR_TC4_SHIFT = 9,
+ RTD1325_ISO_ISR_TC7_SHIFT = 10,
+ RTD1325_ISO_ISR_I2C1_SHIFT = 11,
+ RTD1325_ISO_ISR_HIFI_WAKEUP_SHIFT = 14,
+ RTD1325_ISO_ISR_WDOG4_NMI_SHIFT = 15,
+ RTD1325_ISO_ISR_TC8_SHIFT = 16,
+ RTD1325_ISO_ISR_VFD_SHIFT = 17,
+ RTD1325_ISO_ISR_VTC_SHIFT = 18,
+ RTD1325_ISO_ISR_GPIOA_SHIFT = 19,
+ RTD1325_ISO_ISR_GPIODA_SHIFT = 20,
+ RTD1325_ISO_ISR_ISO_MISC_SHIFT = 21,
+ RTD1325_ISO_ISR_CBUS_SHIFT = 22,
+ RTD1325_ISO_ISR_ETN_SHIFT = 23,
+ RTD1325_ISO_ISR_USB_HOST_SHIFT = 24,
+ RTD1325_ISO_ISR_USB_U3_DRD_SHIFT = 25,
+ RTD1325_ISO_ISR_USB_U2_DRD_SHIFT = 26,
+ RTD1325_ISO_ISR_WDOG3_NMI_SHIFT = 27,
+ RTD1325_ISO_ISR_PORB_HV_CEN_SHIFT = 28,
+ RTD1325_ISO_ISR_PORB_DV_CEN_SHIFT = 29,
+ RTD1325_ISO_ISR_PORB_AV_CEN_SHIFT = 30,
+ RTD1325_ISO_ISR_I2C1_REQ_SHIFT = 31,
+};
+
+static const u32 rtd1325_iso_isr_to_scpu_int_en_mask[32] = {
+ [RTD1325_ISO_ISR_SPI1_SHIFT] = BIT(1),
+ [RTD1325_ISO_ISR_UR0_SHIFT] = BIT(2),
+ [RTD1325_ISO_ISR_LSADC0_SHIFT] = BIT(3),
+ [RTD1325_ISO_ISR_IRDA_SHIFT] = BIT(5),
+ [RTD1325_ISO_ISR_I2C0_SHIFT] = BIT(8),
+ [RTD1325_ISO_ISR_I2C1_SHIFT] = BIT(11),
+ [RTD1325_ISO_ISR_VFD_SHIFT] = BIT(17),
+ [RTD1325_ISO_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1325_ISO_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1325_ISO_ISR_PORB_HV_CEN_SHIFT] = BIT(28),
+ [RTD1325_ISO_ISR_PORB_DV_CEN_SHIFT] = BIT(29),
+ [RTD1325_ISO_ISR_PORB_AV_CEN_SHIFT] = BIT(30),
+ [RTD1325_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31),
+ [RTD1325_ISO_ISR_WDOG1_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1325_ISO_ISR_WDOG2_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1325_ISO_ISR_WDOG3_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1325_ISO_ISR_WDOG4_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+};
+
+enum rtd1325_misc_isr_bits {
+ RTD1325_ISR_UR1_SHIFT = 3,
+ RTD1325_ISR_TC5_SHIFT = 4,
+ RTD1325_ISR_UR1_TO_SHIFT = 5,
+ RTD1325_ISR_TC0_SHIFT = 6,
+ RTD1325_ISR_TC1_SHIFT = 7,
+ RTD1325_ISR_UR2_SHIFT = 8,
+ RTD1325_ISR_UR2_TO_SHIFT = 13,
+ RTD1325_ISR_I2C5_SHIFT = 14,
+ RTD1325_ISR_I2C4_SHIFT = 15,
+ RTD1325_ISR_DRTC_HSEC_SHIFT = 16,
+ RTD1325_ISR_DRTC_MIN_SHIFT = 17,
+ RTD1325_ISR_DRTC_HOUR_SHIFT = 18,
+ RTD1325_ISR_DRTC_DATE_SHIFT = 19,
+ RTD1325_ISR_DRTC_ALARM_SHIFT = 20,
+ RTD1325_ISR_I2C3_SHIFT = 23,
+ RTD1325_ISR_SC0_SHIFT = 24,
+ RTD1325_ISR_SC1_SHIFT = 25,
+ RTD1325_ISR_SPI_SHIFT = 27,
+ RTD1325_ISR_FAN_SHIFT = 29,
+};
+
+static const u32 rtd1325_misc_isr_to_scpu_int_en_mask[32] = {
+ [RTD1325_ISR_UR1_SHIFT] = BIT(3),
+ [RTD1325_ISR_UR1_TO_SHIFT] = BIT(5),
+ [RTD1325_ISR_UR2_TO_SHIFT] = BIT(6),
+ [RTD1325_ISR_UR2_SHIFT] = BIT(7),
+ [RTD1325_ISR_I2C5_SHIFT] = BIT(14),
+ [RTD1325_ISR_I2C4_SHIFT] = BIT(15),
+ [RTD1325_ISR_DRTC_HSEC_SHIFT] = BIT(16),
+ [RTD1325_ISR_DRTC_MIN_SHIFT] = BIT(17),
+ [RTD1325_ISR_DRTC_HOUR_SHIFT] = BIT(18),
+ [RTD1325_ISR_DRTC_DATE_SHIFT] = BIT(19),
+ [RTD1325_ISR_DRTC_ALARM_SHIFT] = BIT(20),
+ [RTD1325_ISR_SC0_SHIFT] = BIT(24),
+ [RTD1325_ISR_SC1_SHIFT] = BIT(25),
+ [RTD1325_ISR_SPI_SHIFT] = BIT(27),
+ [RTD1325_ISR_I2C3_SHIFT] = BIT(28),
+ [RTD1325_ISR_FAN_SHIFT] = BIT(29),
+};
+
+static struct realtek_intc_subset_cfg rtd1325_intc_iso_cfgs[] = {
+ { ISO_NORMAL_MASK, },
+ { ISO_NMI_WDT_MASK, },
+};
+
+static const struct realtek_intc_info rtd1325_intc_iso_info = {
+ .isr_offset = ISO_ISR_OFFSET,
+ .umsk_isr_offset = ISO_ISR_UMSK_OFFSET,
+ .scpu_int_en_offset = ISO_ISR_EN_OFFSET,
+ .isr_to_scpu_int_en_mask = rtd1325_iso_isr_to_scpu_int_en_mask,
+ .cfg = rtd1325_intc_iso_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1325_intc_iso_cfgs),
+};
+
+static struct realtek_intc_subset_cfg rtd1325_intc_misc_cfgs[] = {
+ { MISC_NORMAL_MASK, },
+ { MISC_UART1_MASK, },
+ { MISC_UART2_MASK, },
+};
+
+static const struct realtek_intc_info rtd1325_intc_misc_info = {
+ .isr_offset = MISC_ISR_OFFSET,
+ .umsk_isr_offset = MISC_ISR_UMSK_OFFSET,
+ .scpu_int_en_offset = MISC_ISR_EN_OFFSET,
+ .isr_to_scpu_int_en_mask = rtd1325_misc_isr_to_scpu_int_en_mask,
+ .cfg = rtd1325_intc_misc_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1325_intc_misc_cfgs),
+};
+
+static const struct of_device_id realtek_intc_rtd1325_dt_matches[] = {
+ {
+ .compatible = "realtek,rtd1325-intc-iso",
+ .data = &rtd1325_intc_iso_info,
+ }, {
+ .compatible = "realtek,rtd1325-intc-misc",
+ .data = &rtd1325_intc_misc_info,
+ },
+ { /* sentinel */ }
+};
+
+static int realtek_intc_rtd1325_suspend(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ data->saved_en = readl(data->base + info->scpu_int_en_offset);
+
+ writel(DISABLE_INTC, data->base + info->scpu_int_en_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+
+ return 0;
+}
+
+static int realtek_intc_rtd1325_resume(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+ writel(data->saved_en, data->base + info->scpu_int_en_offset);
+
+ return 0;
+}
+
+static const struct dev_pm_ops realtek_intc_rtd1325_pm_ops = {
+ .suspend_noirq = realtek_intc_rtd1325_suspend,
+ .resume_noirq = realtek_intc_rtd1325_resume,
+};
+
+static int rtd1325_intc_probe(struct platform_device *pdev)
+{
+ const struct realtek_intc_info *info;
+
+ info = of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -EINVAL;
+
+ return realtek_intc_probe(pdev, info);
+}
+
+static struct platform_driver realtek_intc_rtd1325_driver = {
+ .probe = rtd1325_intc_probe,
+ .driver = {
+ .name = "realtek_intc_rtd1325",
+ .of_match_table = realtek_intc_rtd1325_dt_matches,
+ .suppress_bind_attrs = true,
+ .pm = &realtek_intc_rtd1325_pm_ops,
+ },
+};
+
+static int __init realtek_intc_rtd1325_init(void)
+{
+ return platform_driver_register(&realtek_intc_rtd1325_driver);
+}
+core_initcall(realtek_intc_rtd1325_init);
+
+static void __exit realtek_intc_rtd1325_exit(void)
+{
+ platform_driver_unregister(&realtek_intc_rtd1325_driver);
+}
+module_exit(realtek_intc_rtd1325_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek RTD1325 Interrupt Controller Driver");
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v2 6/6] irqchip: Introduce RTD1619B support using the Realtek common interrupt controller driver
2023-11-17 16:27 [PATCH v2 0/6] Initial support for the Realtek interrupt controller James Tai
` (4 preceding siblings ...)
2023-11-17 16:27 ` [PATCH v2 5/6] irqchip: Introduce RTD1325 " James Tai
@ 2023-11-17 16:27 ` James Tai
5 siblings, 0 replies; 26+ messages in thread
From: James Tai @ 2023-11-17 16:27 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, James Tai
Cc: linux-kernel, devicetree
Add support for the RTD1619B platform.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202311061822.551ieaoI-lkp@intel.com/
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Marc Zyngier <maz@kernel.org>
CC: linux-kernel@vger.kernel.org
Signed-off-by: James Tai <james.tai@realtek.com>
---
v1 to v2 change:
- Resolved kernel test robot build warnings
- Replaced magic number with macro
- Fixed code style issues
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-rtd1619b.c | 217 +++++++++++++++++++++++++
3 files changed, 224 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-rtd1619b.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 65e2d67d1505..c5b2762df420 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -240,6 +240,12 @@ config REALTEK_RTD1325_INTC
help
Support for Realtek RTD1325 Interrupt Controller.
+config REALTEK_RTD1619B_INTC
+ tristate "Realtek RTD1619B interrupt controller"
+ select REALTEK_DHC_INTC
+ help
+ Support for Realtek RTD1619B Interrupt Controller.
+
config RENESAS_INTC_IRQPIN
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index eaa12928d60b..da308aefcb87 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o
obj-$(CONFIG_REALTEK_RTD1319_INTC) += irq-realtek-rtd1319.o
obj-$(CONFIG_REALTEK_RTD1319D_INTC) += irq-realtek-rtd1319d.o
obj-$(CONFIG_REALTEK_RTD1325_INTC) += irq-realtek-rtd1325.o
+obj-$(CONFIG_REALTEK_RTD1619B_INTC) += irq-realtek-rtd1619b.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
diff --git a/drivers/irqchip/irq-realtek-rtd1619b.c b/drivers/irqchip/irq-realtek-rtd1619b.c
new file mode 100644
index 000000000000..27bc4f9ef3bf
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-rtd1619b.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1619B interrupt controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "irq-realtek-intc-common.h"
+
+#define ISO_NMI_WDT_MASK 0x08008090
+#define ISO_NORMAL_MASK 0xf7ff7f6e
+#define MISC_NORMAL_MASK 0xffffded6
+#define MISC_UART1_MASK 0x00000028
+#define MISC_UART2_MASK 0x00002100
+
+#define ISO_ISR_EN_OFFSET 0x40
+#define ISO_ISR_OFFSET 0
+#define ISO_ISR_UMSK_OFFSET 0x4
+#define MISC_ISR_EN_OFFSET 0x80
+#define MISC_ISR_OFFSET 0xc
+#define MISC_ISR_UMSK_OFFSET 0x8
+
+enum rtd1619b_iso_isr_bits {
+ RTD1619B_ISO_ISR_TC3_SHIFT = 1,
+ RTD1619B_ISO_ISR_UR0_SHIFT = 2,
+ RTD1619B_ISO_ISR_LSADC0_SHIFT = 3,
+ RTD1619B_ISO_ISR_WDOG1_NMI_SHIFT = 4,
+ RTD1619B_ISO_ISR_IRDA_SHIFT = 5,
+ RTD1619B_ISO_ISR_SPI1_SHIFT = 6,
+ RTD1619B_ISO_ISR_WDOG2_NMI_SHIFT = 7,
+ RTD1619B_ISO_ISR_I2C0_SHIFT = 8,
+ RTD1619B_ISO_ISR_TC4_SHIFT = 9,
+ RTD1619B_ISO_ISR_TC7_SHIFT = 10,
+ RTD1619B_ISO_ISR_I2C1_SHIFT = 11,
+ RTD1619B_ISO_ISR_HIFI_WAKEUP_SHIFT = 14,
+ RTD1619B_ISO_ISR_WDOG4_NMI_SHIFT = 15,
+ RTD1619B_ISO_ISR_TC8_SHIFT = 16,
+ RTD1619B_ISO_ISR_VFD_SHIFT = 17,
+ RTD1619B_ISO_ISR_VTC_SHIFT = 18,
+ RTD1619B_ISO_ISR_GPIOA_SHIFT = 19,
+ RTD1619B_ISO_ISR_GPIODA_SHIFT = 20,
+ RTD1619B_ISO_ISR_ISO_MISC_SHIFT = 21,
+ RTD1619B_ISO_ISR_CBUS_SHIFT = 22,
+ RTD1619B_ISO_ISR_ETN_SHIFT = 23,
+ RTD1619B_ISO_ISR_USB_HOST_SHIFT = 24,
+ RTD1619B_ISO_ISR_USB_U3_DRD_SHIFT = 25,
+ RTD1619B_ISO_ISR_USB_U2_DRD_SHIFT = 26,
+ RTD1619B_ISO_ISR_WDOG3_NMI_SHIFT = 27,
+ RTD1619B_ISO_ISR_PORB_HV_CEN_SHIFT = 28,
+ RTD1619B_ISO_ISR_PORB_DV_CEN_SHIFT = 29,
+ RTD1619B_ISO_ISR_PORB_AV_CEN_SHIFT = 30,
+ RTD1619B_ISO_ISR_I2C1_REQ_SHIFT = 31,
+};
+
+static const u32 rtd1619b_iso_isr_to_scpu_int_en_mask[32] = {
+ [RTD1619B_ISO_ISR_SPI1_SHIFT] = BIT(1),
+ [RTD1619B_ISO_ISR_UR0_SHIFT] = BIT(2),
+ [RTD1619B_ISO_ISR_LSADC0_SHIFT] = BIT(3),
+ [RTD1619B_ISO_ISR_IRDA_SHIFT] = BIT(5),
+ [RTD1619B_ISO_ISR_I2C0_SHIFT] = BIT(8),
+ [RTD1619B_ISO_ISR_I2C1_SHIFT] = BIT(11),
+ [RTD1619B_ISO_ISR_VFD_SHIFT] = BIT(17),
+ [RTD1619B_ISO_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1619B_ISO_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1619B_ISO_ISR_PORB_HV_CEN_SHIFT] = BIT(28),
+ [RTD1619B_ISO_ISR_PORB_DV_CEN_SHIFT] = BIT(29),
+ [RTD1619B_ISO_ISR_PORB_AV_CEN_SHIFT] = BIT(30),
+ [RTD1619B_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31),
+ [RTD1619B_ISO_ISR_WDOG1_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1619B_ISO_ISR_WDOG2_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1619B_ISO_ISR_WDOG3_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1619B_ISO_ISR_WDOG4_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+};
+
+enum rtd1619b_misc_isr_bits {
+ RTD1619B_ISR_UR1_SHIFT = 3,
+ RTD1619B_ISR_TC5_SHIFT = 4,
+ RTD1619B_ISR_UR1_TO_SHIFT = 5,
+ RTD1619B_ISR_TC0_SHIFT = 6,
+ RTD1619B_ISR_TC1_SHIFT = 7,
+ RTD1619B_ISR_UR2_SHIFT = 8,
+ RTD1619B_ISR_UR2_TO_SHIFT = 13,
+ RTD1619B_ISR_I2C5_SHIFT = 14,
+ RTD1619B_ISR_I2C4_SHIFT = 15,
+ RTD1619B_ISR_I2C3_SHIFT = 23,
+ RTD1619B_ISR_SC0_SHIFT = 24,
+ RTD1619B_ISR_SC1_SHIFT = 25,
+ RTD1619B_ISR_SPI_SHIFT = 27,
+ RTD1619B_ISR_FAN_SHIFT = 29,
+};
+
+static const u32 rtd1619b_misc_isr_to_scpu_int_en_mask[32] = {
+ [RTD1619B_ISR_UR1_SHIFT] = BIT(3),
+ [RTD1619B_ISR_UR1_TO_SHIFT] = BIT(5),
+ [RTD1619B_ISR_UR2_TO_SHIFT] = BIT(6),
+ [RTD1619B_ISR_UR2_SHIFT] = BIT(7),
+ [RTD1619B_ISR_I2C5_SHIFT] = BIT(14),
+ [RTD1619B_ISR_I2C4_SHIFT] = BIT(15),
+ [RTD1619B_ISR_SC0_SHIFT] = BIT(24),
+ [RTD1619B_ISR_SC1_SHIFT] = BIT(25),
+ [RTD1619B_ISR_SPI_SHIFT] = BIT(27),
+ [RTD1619B_ISR_I2C3_SHIFT] = BIT(28),
+ [RTD1619B_ISR_FAN_SHIFT] = BIT(29),
+};
+
+static struct realtek_intc_subset_cfg rtd1619b_intc_iso_cfgs[] = {
+ { ISO_NORMAL_MASK, },
+ { ISO_NMI_WDT_MASK, },
+};
+
+static const struct realtek_intc_info rtd1619b_intc_iso_info = {
+ .isr_offset = ISO_ISR_OFFSET,
+ .umsk_isr_offset = ISO_ISR_UMSK_OFFSET,
+ .scpu_int_en_offset = ISO_ISR_EN_OFFSET,
+ .isr_to_scpu_int_en_mask = rtd1619b_iso_isr_to_scpu_int_en_mask,
+ .cfg = rtd1619b_intc_iso_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1619b_intc_iso_cfgs),
+};
+
+static struct realtek_intc_subset_cfg rtd1619b_intc_misc_cfgs[] = {
+ { MISC_NORMAL_MASK, },
+ { MISC_UART1_MASK, },
+ { MISC_UART2_MASK, },
+};
+
+static const struct realtek_intc_info rtd1619b_intc_misc_info = {
+ .isr_offset = MISC_ISR_OFFSET,
+ .umsk_isr_offset = MISC_ISR_UMSK_OFFSET,
+ .scpu_int_en_offset = MISC_ISR_EN_OFFSET,
+ .isr_to_scpu_int_en_mask = rtd1619b_misc_isr_to_scpu_int_en_mask,
+ .cfg = rtd1619b_intc_misc_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1619b_intc_misc_cfgs),
+};
+
+static const struct of_device_id realtek_intc_rtd1619b_dt_matches[] = {
+ {
+ .compatible = "realtek,rtd1619b-intc-iso",
+ .data = &rtd1619b_intc_iso_info,
+ }, {
+ .compatible = "realtek,rtd1619b-intc-misc",
+ .data = &rtd1619b_intc_misc_info,
+ },
+ { /* sentinel */ }
+};
+
+static int realtek_intc_rtd1619b_suspend(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ data->saved_en = readl(data->base + info->scpu_int_en_offset);
+
+ writel(DISABLE_INTC, data->base + info->scpu_int_en_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+
+ return 0;
+}
+
+static int realtek_intc_rtd1619b_resume(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+ writel(data->saved_en, data->base + info->scpu_int_en_offset);
+
+ return 0;
+}
+
+static const struct dev_pm_ops realtek_intc_rtd1619b_pm_ops = {
+ .suspend_noirq = realtek_intc_rtd1619b_suspend,
+ .resume_noirq = realtek_intc_rtd1619b_resume,
+};
+
+static int rtd1619b_intc_probe(struct platform_device *pdev)
+{
+ const struct realtek_intc_info *info;
+
+ info = of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -EINVAL;
+
+ return realtek_intc_probe(pdev, info);
+}
+
+static struct platform_driver realtek_intc_rtd1619b_driver = {
+ .probe = rtd1619b_intc_probe,
+ .driver = {
+ .name = "realtek_intc_rtd1619b",
+ .of_match_table = realtek_intc_rtd1619b_dt_matches,
+ .suppress_bind_attrs = true,
+ .pm = &realtek_intc_rtd1619b_pm_ops,
+ },
+};
+
+static int __init realtek_intc_rtd1619b_init(void)
+{
+ return platform_driver_register(&realtek_intc_rtd1619b_driver);
+}
+core_initcall(realtek_intc_rtd1619b_init);
+
+static void __exit realtek_intc_rtd1619b_exit(void)
+{
+ platform_driver_unregister(&realtek_intc_rtd1619b_driver);
+}
+module_exit(realtek_intc_rtd1619b_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek RTD1619B Interrupt Controller Driver");
--
2.25.1
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