From: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
iommu@lists.linux-foundation.org, bhelgaas@google.com,
robh+dt@kernel.org, mark.rutland@arm.com,
lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,
sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,
will.deacon@arm.com, robin.murphy@arm.com, okaya@codeaurora.org,
sunil.kovvuri@gmail.com, thunder.leizhen@huawei.com,
tn@semihalf.com
Subject: Re: [PATCH 6/7] iommu/arm-smmu-v3: Add support for PCI ATS
Date: Tue, 30 May 2017 11:58:41 +0100 [thread overview]
Message-ID: <e162ad57-0fab-b65c-49b1-d083fcbf61d7@arm.com> (raw)
In-Reply-To: <20170530102831.GJ2818@8bytes.org>
On 30/05/17 11:28, Joerg Roedel wrote:
> On Wed, May 24, 2017 at 07:01:42PM +0100, Jean-Philippe Brucker wrote:
>> * TLB invalidation by range is batched and committed with a single sync.
>> Batching ATC invalidation is inconvenient, endpoints limit the number of
>> inflight invalidations. We'd have to count the number of invalidations
>> queued and send a sync periodically. In addition, I suspect we always
>> need a sync between TLB and ATC invalidation for the same page.
>
> This sounds like the number of outstanding ATS invalidations is not
> managed by the SMMU hardware, is that right?
Yes, the hardware doesn't know about ATS queue depth, it simply forwards
invalidations to the root complex. Doing a sync on the SMMU command queue
waits for all completions of outstanding ATS invalidations, but it is up
to the driver to limit ATS invalidations according to queue depth.
Thanks,
Jean
next prev parent reply other threads:[~2017-05-30 10:58 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-24 18:01 [PATCH 0/7] Add PCI ATS support to SMMUv3 Jean-Philippe Brucker
2017-05-24 18:01 ` [PATCH 1/7] PCI: Move ATS declarations outside of CONFIG_PCI Jean-Philippe Brucker
2017-05-24 18:01 ` [PATCH 3/7] iommu/of: Check ATS capability in root complex nodes Jean-Philippe Brucker
[not found] ` <20170524180143.19855-1-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2017-05-24 18:01 ` [PATCH 2/7] dt-bindings: PCI: Describe ATS property for " Jean-Philippe Brucker
2017-05-30 10:01 ` Joerg Roedel
2017-05-30 10:58 ` Jean-Philippe Brucker
[not found] ` <035be7ba-e850-a5a9-08fa-802a04feb600-5wv7dgnIgG8@public.gmane.org>
2017-05-31 17:17 ` Rob Herring
[not found] ` <20170524180143.19855-3-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2017-05-31 17:23 ` Rob Herring
2017-06-01 12:28 ` Jean-Philippe Brucker
2017-06-05 17:20 ` Rob Herring
2017-06-06 11:11 ` Jean-Philippe Brucker
[not found] ` <65aea93f-d516-f045-f216-3f56e96bdeb6-5wv7dgnIgG8@public.gmane.org>
2017-06-20 11:38 ` Jean-Philippe Brucker
2017-05-24 18:01 ` [PATCH 4/7] ACPI/IORT: Check ATS capability in " Jean-Philippe Brucker
2017-05-24 18:01 ` [PATCH 5/7] iommu/arm-smmu-v3: Link domains and devices Jean-Philippe Brucker
2017-05-24 18:01 ` [PATCH 6/7] iommu/arm-smmu-v3: Add support for PCI ATS Jean-Philippe Brucker
[not found] ` <20170524180143.19855-7-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2017-05-30 10:28 ` Joerg Roedel
2017-05-30 10:58 ` Jean-Philippe Brucker [this message]
2017-05-24 18:01 ` [PATCH 7/7] iommu/arm-smmu-v3: Disable tagged pointers Jean-Philippe Brucker
2017-05-31 15:27 ` [PATCH 0/7] Add PCI ATS support to SMMUv3 Nate Watterson
2017-06-01 12:23 ` Jean-Philippe Brucker
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