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Mon, 10 Feb 2025 03:48:01 -0800 (PST) Message-ID: Subject: Re: [PATCH 08/10] riscv/arm64: dts: cv18xx: Add sysctl and reset nodes From: Alexander Sverdlin To: Inochi Amaoto , soc@lists.linux.dev Cc: Chen Wang , Inochi Amaoto , linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Sebastian Reichel , Arnd Bergmann , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones Date: Mon, 10 Feb 2025 12:47:59 +0100 In-Reply-To: References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> <20250209220646.1090868-9-alexander.sverdlin@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Thanks for quick feedback Inochi! On Mon, 2025-02-10 at 13:13 +0800, Inochi Amaoto wrote: > On Sun, Feb 09, 2025 at 11:06:33PM +0100, Alexander Sverdlin wrote: > > Add reset controller node and required sysctl nodes. > >=20 > > Signed-off-by: Alexander Sverdlin > > --- > > =C2=A0 arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi | 16 +++++++++++++= +++ > > =C2=A0 1 file changed, 16 insertions(+) > >=20 > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi b/arch/riscv= /boot/dts/sophgo/cv18xx-periph.dtsi > > index 53834b0658b2..d793b6db4ed1 100644 > > --- a/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-periph.dtsi > > @@ -309,5 +309,21 @@ dmac: dma-controller@4330000 { > > =C2=A0=C2=A0 snps,data-width =3D <4>; > > =C2=A0=C2=A0 status =3D "disabled"; > > =C2=A0=C2=A0 }; > > + >=20 > > + rtcsys_ctrl: syscon@5025000 { > > + compatible =3D "sophgo,cv1800-rtcsys-ctrl", "syscon"; > > + reg =3D <0x05025000 0x1000>; > > + }; > > + > > + rtcsys_core: syscon@5026000 { > > + compatible =3D "sophgo,cv1800-rtcsys-core", "syscon"; > > + reg =3D <0x05026000 0x1000>; > > + }; > > + > > + soc-reset { > > + compatible =3D "sophgo,cv1800-reset"; > > + sophgo,rtcsys-ctrl =3D <&rtcsys_ctrl>; > > + sophgo,rtcsys-core =3D <&rtcsys_core>; > > + }; >=20 > I think these node is not suitable for riscv. It should use SBI SRST > extension to restart. Independent from the particular form, or its correctness, this is still HW description, right? It would be a "policy" for the kernel configuration, if the particular build would rely on the FW or a kernel driver to reboot. In other words, the HW block remains in place, no matter if it's controlled by a kernel module or a FW. What the point in hiding it from the RiscV part of DT, keeping on ARM64 side only? --=20 Alexander Sverdlin.