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Tue, 31 Mar 2026 06:12:20 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: ABMmOHXEXk43 Date: Tue, 31 Mar 2026 12:11:40 +0200 From: "Arnd Bergmann" To: "Khristine Andreea Barbulescu" , "Krzysztof Kozlowski" , "Ghennadi Procopciuc" Cc: "Linus Walleij" , "Bartosz Golaszewski" , "Krzysztof Kozlowski" , "Conor Dooley" , "Chester Lin" , "Matthias Brugger" , "Ghennadi Procopciuc" , "Larisa Grigore" , "Lee Jones" , "Shawn Guo" , "Sascha Hauer" , "Fabio Estevam" , "Aisheng Dong" , "Jacky Bai" , "Greg Kroah-Hartman" , "Rafael J . Wysocki" , "Alberto Ruiz" , "Christophe Lizzi" , devicetree@vger.kernel.org, "Enric Balletbo" , "Eric Chanudet" , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, "open list:GPIO SUBSYSTEM" , linux-kernel@vger.kernel.org, "NXP S32 Linux Team" , "Pengutronix Kernel Team" , "Vincent Guittot" , "Rob Herring" Message-Id: In-Reply-To: <4c46909d-641b-4389-bc4a-29394cb1d46d@oss.nxp.com> References: <20260120115923.3463866-1-khristineandreea.barbulescu@oss.nxp.com> <20260120115923.3463866-2-khristineandreea.barbulescu@oss.nxp.com> <20260121021913.GA1704619-robh@kernel.org> <7d200097-51bc-4404-be8b-f536d0ecfc25@oss.nxp.com> <21531cdd-5ab9-493e-a722-61b98117e2c4@kernel.org> <22a5a072-847e-4cfd-8abd-e37163f73265@oss.nxp.com> <3c454da1-d949-4258-87ce-8b545000bf01@app.fastmail.com> <5f1b651b-1064-4280-a7e0-b7d66c396cde@oss.nxp.com> <4c46909d-641b-4389-bc4a-29394cb1d46d@oss.nxp.com> Subject: Re: [PATCH v8 01/10] dt-bindings: mfd: add support for the NXP SIUL2 module Content-Type: text/plain Content-Transfer-Encoding: 7bit On Tue, Mar 31, 2026, at 09:48, Khristine Andreea Barbulescu wrote: > > With the current layout, the SIUL2 node itself now contains the two > MMIO ranges directly, while the remaining child node is only the > pinctrl/GPIO function. The thread started by saying this is an MFD "It can export information about the SoC, configure the pinmux&pinconf for pins and it is also a GPIO controller with interrupt capability." Having a combined pinctrl/gpio/irqchip driver is normal, but can you clarify what you plan to do with the "information about the SoC" part? Was this a "soc_device" driver, or something else? Have you concluded now that this is not going to be needed at all? In that case, I guess having a monolithic driver is indeed simpler than an MFD. What I wonder about then is whether the binding needs to be changed at all. With the current nxp,s32g2-siul2-pinctrl.yaml binding and pinctrl-s32g2.c implementation, you seem to have a monolithic device already, though missing the gpio functionality. Rather than completely replacing this, I assume the easiest way then would be to add the PGPD registers into this device node, right? It is still a bit weird to list the individual register areas inside of the larger device here, but that still seems better than an incompatible binding change. Arnd