From: claudiu beznea <claudiu.beznea@tuxon.dev>
To: Sergei Shtylyov <sergei.shtylyov@gmail.com>,
geert+renesas@glider.be, magnus.damm@gmail.com,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org
Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH 1/6] clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
Date: Wed, 11 Oct 2023 10:36:56 +0300 [thread overview]
Message-ID: <e1c9c2ca-144c-49fe-940c-9ca8ad40e377@tuxon.dev> (raw)
In-Reply-To: <8226bd48-4297-0b32-c733-2e569114a934@gmail.com>
Hi, Sergei,
On 10.10.2023 17:52, Sergei Shtylyov wrote:
> Hello!
>
> On 10/10/23 4:26 PM, Claudiu wrote:
>
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Use %x format specifier to print CLK_ON_R(). This is easier when
>> debugging as the value printed will be hexadecimal like in the hardware
>> manual. Along with it "0x" has been added in front of the printed value.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>> drivers/clk/renesas/rzg2l-cpg.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
>> index d62f1bc1f60e..764bd72cf059 100644
>> --- a/drivers/clk/renesas/rzg2l-cpg.c
>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
>> @@ -1213,7 +1213,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
>> return 0;
>> }
>>
>> - dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk,
>> + dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", CLK_ON_R(reg), hw->clk,
>
> Perhaps "%#x" instead of "0x%x"?
Yes, better, thanks!
>
> [...]
>
> MBR, Sergey
next prev parent reply other threads:[~2023-10-11 7:37 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-10 13:26 [PATCH 0/6] arm64: dts: renesas: Add SDHI1 and SDHI2 for RZ/G3S Claudiu
2023-10-10 13:26 ` [PATCH 1/6] clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() Claudiu
2023-10-10 14:52 ` Sergei Shtylyov
2023-10-11 7:36 ` claudiu beznea [this message]
2023-10-11 7:43 ` Geert Uytterhoeven
2023-10-11 15:55 ` claudiu beznea
2023-10-12 12:37 ` Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 2/6] clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 Claudiu
2023-10-12 13:22 ` Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 3/6] arm64: dts: renesas: r9a08g045: Add nodes " Claudiu
2023-10-12 13:35 ` Geert Uytterhoeven
2023-10-10 13:26 ` [PATCH 4/6] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Claudiu
2023-10-12 14:36 ` Geert Uytterhoeven
2023-10-13 5:45 ` claudiu beznea
2023-10-10 13:27 ` [PATCH 5/6] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 Claudiu
2023-10-12 14:44 ` Geert Uytterhoeven
2023-10-13 5:51 ` claudiu beznea
2023-10-10 13:27 ` [PATCH 6/6] arm64: dts: renesas: rzg3s: Fix dtbs_check Claudiu
2023-10-12 14:49 ` Geert Uytterhoeven
2023-10-13 5:55 ` claudiu beznea
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