From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52217C4332F for ; Sun, 25 Dec 2022 14:32:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229489AbiLYOcD (ORCPT ); Sun, 25 Dec 2022 09:32:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229445AbiLYOcD (ORCPT ); Sun, 25 Dec 2022 09:32:03 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23535C04; Sun, 25 Dec 2022 06:31:53 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id C1C7424DFCE; Sun, 25 Dec 2022 22:31:44 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Sun, 25 Dec 2022 22:31:44 +0800 Received: from [192.168.2.237] (113.72.145.114) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Sun, 25 Dec 2022 22:31:43 +0800 Message-ID: Date: Sun, 25 Dec 2022 22:31:41 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 From: Hal Feng Subject: Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree To: Conor Dooley CC: , , "Palmer Dabbelt" , Rob Herring , "Krzysztof Kozlowski" , Paul Walmsley , Albert Ou , Ben Dooks , Daniel Lezcano , "Thomas Gleixner" , Marc Zyngier , Stephen Boyd , Michael Turquette , "Philipp Zabel" , Linus Walleij , Emil Renner Berthing , References: <20221220011247.35560-1-hal.feng@starfivetech.com> <20221220011247.35560-7-hal.feng@starfivetech.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [113.72.145.114] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, 20 Dec 2022 21:31:43 +0000, Conor Dooley wrote: > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote: > > From: Emil Renner Berthing > > > > Add initial device tree for the JH7110 RISC-V SoC by StarFive > > Technology Ltd. > > > > Signed-off-by: Emil Renner Berthing > > Co-developed-by: Jianlong Huang > > Signed-off-by: Jianlong Huang > > Co-developed-by: Hal Feng > > Signed-off-by: Hal Feng > > --- > > FWIW, this cpu-map is now the default in linux, so you no longer *need* > to add it for that purpose - but there's obviously no harm in being > explicit for other operating systems etc. (IOW, don't remove it!) > > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&S76_0>; > > + }; > > + > > + core1 { > > + cpu = <&U74_1>; > > + }; > > + > > + core2 { > > + cpu = <&U74_2>; > > + }; > > + > > + core3 { > > + cpu = <&U74_3>; > > + }; > > + > > + core4 { > > + cpu = <&U74_4>; > > + }; > > + }; > > + }; > > + }; > > > + syscrg: clock-controller@13020000 { > > For obvious reasons, I cannot apply this until both the clock & pinctrl > bindings are in my tree - but you know that already. > > > + compatible = "starfive,jh7110-syscrg"; > > + reg = <0x0 0x13020000 0x0 0x10000>; > > + clocks = <&osc>, <&gmac1_rmii_refin>, > > + <&gmac1_rgmii_rxin>, > > + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, > > + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, > > + <&tdm_ext>, <&mclk_ext>; > > As Krzk asked - are these clocks really all inputs to the SoC? Yes, they are all external clock sources inputted to the SoC. They are used as root clocks or optional parent clocks in clock tree. > > > + clock-names = "osc", "gmac1_rmii_refin", > > + "gmac1_rgmii_rxin", > > + "i2stx_bclk_ext", "i2stx_lrck_ext", > > + "i2srx_bclk_ext", "i2srx_lrck_ext", > > + "tdm_ext", "mclk_ext"; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > + }; > > + > > + gpio: gpio@13040000 { > > > + gpioa: gpio@17020000 { > > Out of curiousity, why gpio & gpioa? Oh, is it easier to read if I change "gpio" and "gpioa" to "sysgpio" and "aongpio"? Thanks. Best regards, Hal