From: Stephen Boyd <sboyd@kernel.org>
To: Conor Dooley <conor@kernel.org>, Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: Emil Renner Berthing <kernel@esmil.dk>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 00/11] Add new partial clock and reset drivers for StarFive JH7110
Date: Wed, 15 Mar 2023 15:40:00 -0700 [thread overview]
Message-ID: <e24f9d404c5f9830c9606e4635dc6431.sboyd@kernel.org> (raw)
In-Reply-To: <e895fea6-e13b-450f-97e8-34ecfe075691@spud>
Quoting Conor Dooley (2023-03-15 01:14:06)
> Hey Stephen,
>
> On Wed, Mar 15, 2023 at 11:44:00AM +0800, Xingyu Wu wrote:
> > On 2023/3/15 8:30, Stephen Boyd wrote:
> > > Quoting Xingyu Wu (2023-03-14 05:43:53)
> > >> This patch serises are to add new partial clock drivers and reset
> > >> supports about System-Top-Group(STG), Image-Signal-Process(ISP)
> > >> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC.
> > >
> > > What is your merge plan for this series? Did you intend for clk tree to
> > > take the majority of patches? We won't take the dts changes through the
> > > clk tree.
>
> FWIW, I've been waiting for the "main" clock/reset series [1] to be ready
> to go, before suggesting that I take it (the main series) via the soc
> tree. This one is kinda in the same boat, with defines in the dt-binding
> headers that are used by both drivers and dts, so splitting the two
> doesn't make all that much sense.
>
> As Xingyu points out below, this series depends on the main one, so if I
> was to take that via soc, this one would need to go on top, or be
> delayed.
> At what point does that become too much to go via soc and some sort of
> shared tag become needed?
>
Platform/SoC maintainers either base their DTS file branch on some
branch made in clk repo that has the bindings and drivers they need
(clk-starfive probably), or they send a pull request to clk maintainers
with the bindings and clk drivers. Or they don't use the #defines in the
header files and use raw numbers in the DTS, or they simply apply the
patch that just has the #defines in it to their SoC tree and we
duplicate the commit in the history by also applying it to the clk tree.
Let's try to keep things simple and not use raw numbers.
BTW, clk driver code doesn't typically go via soc. Not sure if that's
happening but please don't do that.
next prev parent reply other threads:[~2023-03-15 22:40 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-14 12:43 [PATCH v3 00/11] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
2023-03-14 12:43 ` [PATCH v3 01/11] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator Xingyu Wu
2023-03-15 7:55 ` Krzysztof Kozlowski
2023-03-14 12:43 ` [PATCH v3 02/11] reset: starfive: jh7110: Add StarFive System-Top-Group reset support Xingyu Wu
2023-03-14 12:43 ` [PATCH v3 03/11] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu
2023-03-14 12:43 ` [PATCH v3 04/11] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator Xingyu Wu
2023-03-14 12:43 ` [PATCH v3 05/11] reset: starfive: jh7110: Add StarFive Image-Signal-Process reset support Xingyu Wu
2023-03-14 12:43 ` [PATCH v3 06/11] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver Xingyu Wu
2023-03-14 12:44 ` [PATCH v3 07/11] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator Xingyu Wu
2023-03-14 12:44 ` [PATCH v3 08/11] reset: starfive: jh7110: Add StarFive Video-Output reset support Xingyu Wu
2023-03-14 12:44 ` [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu
2023-03-14 12:44 ` [PATCH v3 10/11] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Xingyu Wu
2023-03-14 12:44 ` [PATCH v3 11/11] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Xingyu Wu
2023-03-15 0:30 ` [PATCH v3 00/11] Add new partial clock and reset drivers for StarFive JH7110 Stephen Boyd
2023-03-15 3:44 ` Xingyu Wu
2023-03-15 8:14 ` Conor Dooley
2023-03-15 22:40 ` Stephen Boyd [this message]
2023-03-15 22:48 ` Conor Dooley
2023-03-15 22:48 ` Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e24f9d404c5f9830c9606e4635dc6431.sboyd@kernel.org \
--to=sboyd@kernel.org \
--cc=aou@eecs.berkeley.edu \
--cc=conor@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=hal.feng@starfivetech.com \
--cc=kernel@esmil.dk \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=xingyu.wu@starfivetech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).