From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C34EFA3741 for ; Mon, 31 Oct 2022 21:12:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230160AbiJaVMO (ORCPT ); Mon, 31 Oct 2022 17:12:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbiJaVMM (ORCPT ); Mon, 31 Oct 2022 17:12:12 -0400 Received: from relay08.th.seeweb.it (relay08.th.seeweb.it [5.144.164.169]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DBD714020 for ; Mon, 31 Oct 2022 14:12:11 -0700 (PDT) Received: from [192.168.1.101] (95.49.29.156.neoplus.adsl.tpnet.pl [95.49.29.156]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id DA59E3EBDD; Mon, 31 Oct 2022 22:12:08 +0100 (CET) Message-ID: Date: Mon, 31 Oct 2022 22:12:08 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCH 01/10] arm64: dts: qcom: sm6350: Add resets for SDHCI 1/2 Content-Language: en-US To: Marijn Suijten , phone-devel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Martin Botka , Jami Kettunen , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Luca Weiss , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221030073232.22726-1-marijn.suijten@somainline.org> <20221030073232.22726-2-marijn.suijten@somainline.org> From: Konrad Dybcio In-Reply-To: <20221030073232.22726-2-marijn.suijten@somainline.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 30.10.2022 08:32, Marijn Suijten wrote: > Make sure the SDHCI hardware is properly reset before interacting with > it, to protect against any possibly indeterminate state left by the > bootloader. > > Suggested-by: Konrad Dybcio > Signed-off-by: Marijn Suijten > --- Reviewed-by: Konrad Dybcio Konrad > arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index c39de7d3ace0..a3ae765d9781 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -490,6 +490,7 @@ sdhc_1: mmc@7c4000 { > <&gcc GCC_SDCC1_APPS_CLK>, > <&rpmhcc RPMH_CXO_CLK>; > clock-names = "iface", "core", "xo"; > + resets = <&gcc GCC_SDCC1_BCR>; > qcom,dll-config = <0x000f642c>; > qcom,ddr-config = <0x80040868>; > power-domains = <&rpmhpd SM6350_CX>; > @@ -1068,6 +1069,7 @@ sdhc_2: mmc@8804000 { > <&gcc GCC_SDCC2_APPS_CLK>, > <&rpmhcc RPMH_CXO_CLK>; > clock-names = "iface", "core", "xo"; > + resets = <&gcc GCC_SDCC2_BCR>; > interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, > <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; > interconnect-names = "sdhc-ddr", "cpu-sdhc";