* [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to limit frquency
@ 2024-09-12 2:55 WangYuli
2024-09-13 12:42 ` Greg KH
2024-09-13 14:56 ` Christophe JAILLET
0 siblings, 2 replies; 5+ messages in thread
From: WangYuli @ 2024-09-12 2:55 UTC (permalink / raw)
To: stable, gregkh, sashal, william.qiu, emil.renner.berthing,
conor.dooley, wangyuli, xingyu.wu, walker.chen, robh, hal.feng
Cc: kernel, robh+dt, krzysztof.kozlowski+dt, conor+dt, paul.walmsley,
palmer, aou, devicetree, linux-riscv, linux-kernel,
richardcochran, netdev
From: William Qiu <william.qiu@starfivetech.com>
[ Upstream commit af571133f7ae028ec9b5fdab78f483af13bf28d3 ]
In JH7110 SoC, we need to go by-pass mode, so we need add the
assigned-clock* properties to limit clock frquency.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: WangYuli <wangyuli@uniontech.com>
---
.../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 062b97c6e7df..4874e3bb42ab 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -204,6 +204,8 @@ &i2c6 {
&mmc0 {
max-frequency = <100000000>;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+ assigned-clock-rates = <50000000>;
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
@@ -220,6 +222,8 @@ &mmc0 {
&mmc1 {
max-frequency = <100000000>;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+ assigned-clock-rates = <50000000>;
bus-width = <4>;
no-sdio;
no-mmc;
--
2.43.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to limit frquency
2024-09-12 2:55 [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to limit frquency WangYuli
@ 2024-09-13 12:42 ` Greg KH
2024-09-16 3:49 ` WangYuli
2024-09-13 14:56 ` Christophe JAILLET
1 sibling, 1 reply; 5+ messages in thread
From: Greg KH @ 2024-09-13 12:42 UTC (permalink / raw)
To: WangYuli
Cc: stable, sashal, william.qiu, emil.renner.berthing, conor.dooley,
xingyu.wu, walker.chen, robh, hal.feng, kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, paul.walmsley, palmer, aou,
devicetree, linux-riscv, linux-kernel, richardcochran, netdev
On Thu, Sep 12, 2024 at 10:55:05AM +0800, WangYuli wrote:
> From: William Qiu <william.qiu@starfivetech.com>
>
> [ Upstream commit af571133f7ae028ec9b5fdab78f483af13bf28d3 ]
>
> In JH7110 SoC, we need to go by-pass mode, so we need add the
> assigned-clock* properties to limit clock frquency.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: WangYuli <wangyuli@uniontech.com>
> ---
> .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
Please rework this series and send only what is needed here.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to limit frquency
2024-09-12 2:55 [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to limit frquency WangYuli
2024-09-13 12:42 ` Greg KH
@ 2024-09-13 14:56 ` Christophe JAILLET
2024-09-16 3:56 ` WangYuli
1 sibling, 1 reply; 5+ messages in thread
From: Christophe JAILLET @ 2024-09-13 14:56 UTC (permalink / raw)
To: WangYuli, stable, gregkh, sashal, william.qiu,
emil.renner.berthing, conor.dooley, xingyu.wu, walker.chen, robh,
hal.feng
Cc: kernel, robh+dt, krzysztof.kozlowski+dt, conor+dt, paul.walmsley,
palmer, aou, devicetree, linux-riscv, linux-kernel,
richardcochran, netdev
Le 12/09/2024 à 04:55, WangYuli a écrit :
> From: William Qiu <william.qiu@starfivetech.com>
>
> [ Upstream commit af571133f7ae028ec9b5fdab78f483af13bf28d3 ]
>
> In JH7110 SoC, we need to go by-pass mode, so we need add the
> assigned-clock* properties to limit clock frquency.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: WangYuli <wangyuli@uniontech.com>
> ---
Hi,
if/when resent, there is a typo in the subject: s/frquency/frequency/
CJ
> .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 062b97c6e7df..4874e3bb42ab 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -204,6 +204,8 @@ &i2c6 {
>
> &mmc0 {
> max-frequency = <100000000>;
> + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> + assigned-clock-rates = <50000000>;
> bus-width = <8>;
> cap-mmc-highspeed;
> mmc-ddr-1_8v;
> @@ -220,6 +222,8 @@ &mmc0 {
>
> &mmc1 {
> max-frequency = <100000000>;
> + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> + assigned-clock-rates = <50000000>;
> bus-width = <4>;
> no-sdio;
> no-mmc;
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to limit frquency
2024-09-13 12:42 ` Greg KH
@ 2024-09-16 3:49 ` WangYuli
0 siblings, 0 replies; 5+ messages in thread
From: WangYuli @ 2024-09-16 3:49 UTC (permalink / raw)
To: Greg KH
Cc: stable, sashal, william.qiu, emil.renner.berthing, conor.dooley,
xingyu.wu, walker.chen, robh, hal.feng, kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, paul.walmsley, palmer, aou,
devicetree, linux-riscv, linux-kernel, richardcochran, netdev
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On 2024/9/13 20:42, Greg KH wrote:
> Please rework this series and send only what is needed here.
OK, just one.
Link:https://lore.kernel.org/all/247345579659D8F7+20240916034603.59120-1-wangyuli@uniontech.com/
Thanks,
--
WangYuli
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to limit frquency
2024-09-13 14:56 ` Christophe JAILLET
@ 2024-09-16 3:56 ` WangYuli
0 siblings, 0 replies; 5+ messages in thread
From: WangYuli @ 2024-09-16 3:56 UTC (permalink / raw)
To: christophe.jaillet
Cc: aou, conor+dt, conor.dooley, devicetree, emil.renner.berthing,
gregkh, hal.feng, kernel, krzysztof.kozlowski+dt, linux-kernel,
linux-riscv, netdev, palmer, paul.walmsley, richardcochran,
robh+dt, robh, sashal, stable, walker.chen, wangyuli, william.qiu,
xingyu.wu
Since this commit is already in 'linux/master', changing its title for the backport might just make things more confusing.
Thanks,
--
WangYuli
^ permalink raw reply [flat|nested] 5+ messages in thread
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2024-09-12 2:55 [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to limit frquency WangYuli
2024-09-13 12:42 ` Greg KH
2024-09-16 3:49 ` WangYuli
2024-09-13 14:56 ` Christophe JAILLET
2024-09-16 3:56 ` WangYuli
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