From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29D432EC54A; Thu, 9 Apr 2026 18:47:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775760435; cv=none; b=loCVsvJ6VWHtRZ1dY3rly5T0l7OefN3tJfAV66eqjSfKu8H2WCqvbbjgLTfCIko422M6h7/7MiJonow5q9RA1/cHirtmhClOOrhcn9GhVr+KLL9KKH9zKvJnlNYJrVwHXRPsueb6kB+ZVRERhU1jOuF0/mMiXEkuzmiRCaMs/Ds= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775760435; c=relaxed/simple; bh=1PcBfpln8hnkL7gfSAcGhDK1XkUt8OcEqry2ZyF2N+0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Wtk9q6ACaXZakcSP81EpBAUzLifAIjh5N9oGxJanQZZJTvfmNIlglUlQEvO+AUxoz825fnB6j1TD+oZLWMew6jev5g24bU+M3ztUABQ2hFK14fV0YlsK5CEemyD/Vx0rFaIN22Us23SE2a+fD8yoGGqsk0qZ9fYly5WY7GVr5Kg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K35JxDfO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K35JxDfO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9B510C116C6; Thu, 9 Apr 2026 18:47:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775760434; bh=1PcBfpln8hnkL7gfSAcGhDK1XkUt8OcEqry2ZyF2N+0=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=K35JxDfOYh1XUFxotvzpXIipv6GLfMHNfllOVugqhIH8qt4HB/CXq2UxKSHakq654 hUF93Cze7HmAxj23Qx2rOQd8WFr+ONfM1/x1QcQxwyX7HpDpQM3RAvjQ1f66TNoi3q Bw5CqwxLi0Gl06Y3UcqZ9EUiI1Yuyw32kC90BwsWhbfVm0nQFP4sfyK6DMe8yY/TMW mMr5mwCvD9iotOgLFHTKlpfcc3oNa1hQovi5tJcU7lh69AeihNc050G7pb+wBnIFlk fCRCCvgsaHrJVav7K+Rbxtbf8rcV3s+lFbpnX8VtPBiNMx6NhsX9Om9LDK+NWmqnhH zEk38XFh9JHzw== Message-ID: Date: Thu, 9 Apr 2026 19:47:10 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: x1e80100-microsoft-romulus: enable OV02C10 webcam To: Oliver White , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260409083609.75341-1-oliverjwhite07@gmail.com> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20260409083609.75341-1-oliverjwhite07@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 09/04/2026 09:36, Oliver White wrote: > Wire up the front-facing OV02C10 camera on Microsoft Romulus by enabling > CAMSS, CCI1 and CSIPHY4, adding the sensor node and its endpoint, and > describing the PM8010 regulator rails and pinctrl states required by the > camera module. > > With these DT nodes in place the webcam can be probed and used through > the upstream OV02C10 driver. Technically its a MIPI CSI2 camera not a webcam... > Signed-off-by: Oliver White > --- > .../dts/qcom/x1e80100-microsoft-romulus.dtsi | 127 ++++++++++++++++++ > 1 file changed, 127 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi > index 14b5663a4d48..9e910813fa48 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi > @@ -857,6 +857,57 @@ vreg_l3j: ldo3 { > regulator-initial-mode = ; > }; > }; > + > + regulators-8 { > + compatible = "qcom,pm8010-rpmh-regulators"; > + qcom,pmic-id = "m"; > + > + vdd-l1-l2-supply = <&vreg_s5j>; > + vdd-l3-l4-supply = <&vreg_s4c>; > + vdd-l7-supply = <&vreg_bob1>; > + > + vreg_l1m_1p2: ldo1 { > + regulator-name = "vreg_l1m_1p2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1260000>; > + regulator-initial-mode = ; > + }; > + > + vreg_l2m_1p2: ldo2 { > + regulator-name = "vreg_l2m_1p2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1260000>; > + regulator-initial-mode = ; > + }; > + > + vreg_l3m_1p8: ldo3 { > + regulator-name = "vreg_l3m_1p8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1900000>; > + regulator-initial-mode = ; > + }; > + > + vreg_l4m_1p8: ldo4 { > + regulator-name = "vreg_l4m_1p8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1900000>; > + regulator-initial-mode = ; > + }; > + > + vreg_l5m_2p8: ldo5 { > + regulator-name = "vreg_l5m_2p8"; > + regulator-min-microvolt = <2800000>; > + regulator-max-microvolt = <3072000>; > + regulator-initial-mode = ; > + }; > + > + vreg_l7m_2p8: ldo7 { > + regulator-name = "vreg_l7m_2p8"; > + regulator-min-microvolt = <2800000>; > + regulator-max-microvolt = <3072000>; > + regulator-initial-mode = ; > + }; > + }; I would recommend breaking this patch into two parts. One adding the regulators the other adding the camera enablement. > }; > > &gpu { > @@ -867,6 +918,66 @@ &gpu_zap_shader { > firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; > }; > > +&camss { > + status = "okay"; > + > + ports { > + /* > + * port0 => csiphy0 > + * port1 => csiphy1 > + * port2 => csiphy2 > + * port3 => csiphy4 > + */ > + port@3 { > + camss_csiphy4_inep0: endpoint@0 { > + clock-lanes = <7>; > + data-lanes = <0 1>; > + remote-endpoint = <&ov02c10_ep>; > + }; > + }; > + }; > +}; > + > +&cci1 { > + status = "okay"; > +}; > + > +&cci1_i2c1 { > + camera@36 { > + compatible = "ovti,ov02c10"; > + reg = <0x36>; > + > + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; > + pinctrl-names = "default"; > + pinctrl-0 = <&cam_rgb_default>; > + > + clocks = <&camcc CAM_CC_MCLK4_CLK>; > + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; > + assigned-clock-rates = <19200000>; > + > + orientation = <0>; /* front facing */ > + > + avdd-supply = <&vreg_l5m_2p8>; > + dvdd-supply = <&vreg_l1m_1p2>; > + dovdd-supply = <&vreg_l3m_1p8>; > + > + port { > + ov02c10_ep: endpoint { > + data-lanes = <1 2>; > + link-frequencies = /bits/ 64 <400000000>; > + remote-endpoint = <&camss_csiphy4_inep0>; > + }; > + }; > + }; > +}; > + > +&csiphy4 { > + vdda-0p8-supply = <&vreg_l2c>; > + vdda-1p2-supply = <&vreg_l1c>; > + > + status = "okay"; > +}; > + +1 for using the new style but, you should make clear in your cover letter that there is a depends on the style change. > &i2c0 { > clock-frequency = <100000>; > > @@ -1441,6 +1552,22 @@ wcn_sw_en: wcn-sw-en-state { > bias-disable; > }; > > + cam_rgb_default: cam-rgb-default-state { > + mclk-pins { > + pins = "gpio100"; > + function = "cam_aon"; > + drive-strength = <16>; > + bias-disable; > + }; > + > + reset-n-pins { > + pins = "gpio237"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + }; > + > cam_indicator_en: cam-indicator-en-state { > pins = "gpio225"; > function = "gpio"; > -- > 2.51.0 > Please cc me on V2 as I'd like to give RB for this. --- bod