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From: Vincent Mailhol <mailhol@kernel.org>
To: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>,
	Marc Kleine-Budde <mkl@pengutronix.de>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>,
	linux-can@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, imx@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org,
	NXP S32 Linux Team <s32@nxp.com>,
	Christophe Lizzi <clizzi@redhat.com>,
	Alberto Ruiz <aruizrui@redhat.com>,
	Enric Balletbo <eballetb@redhat.com>,
	Eric Chanudet <echanude@redhat.com>,
	Haibo Chen <haibo.chen@nxp.com>
Subject: Re: [PATCH v5 1/8] can: flexcan: use dedicated IRQ handlers for multi-IRQ platforms
Date: Tue, 9 Jun 2026 21:35:17 +0200	[thread overview]
Message-ID: <e2dc8425-fdcd-4a3d-9d00-1416395aea82@kernel.org> (raw)
In-Reply-To: <20260609142954.1807421-2-ciprianmarian.costea@oss.nxp.com>

On 09/06/2026 at 16:29, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> 
> On platforms with multiple IRQ lines (S32G2, MCF5441X), all lines are
> registered to the same flexcan_irq() handler. Since these are distinct IRQ
> numbers, they can be dispatched concurrently on different CPUs. Both
> instances then read the same iflag and ESR registers unconditionally,
> leading to duplicate frame processing.
> 
> Fix this by splitting the monolithic handler into focused parts:
> - flexcan_do_mb(): processes mailbox events
> - flexcan_do_state(): processes device state change events
> - flexcan_do_berr(): processes bus error events
> 
> Introduce dedicated IRQ handlers for multi-IRQ platforms:
> - flexcan_irq_mb(): mailbox-only, used for mb-0, mb-1 IRQ lines
> - flexcan_irq_boff(): state-change-only, used for boff/state IRQ line
> - flexcan_irq_berr(): bus-error-only, used for berr IRQ line
> 
> The combined flexcan_irq() handler is preserved for single-IRQ
> platforms with no functional change.
> 
> Fixes: d9cead75b1c6 ("can: flexcan: add mcf5441x support")
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> Reviewed-and-tested-by: Haibo Chen <haibo.chen@nxp.com>
> Tested-by: Enric Balletbo i Serra <eballetb@redhat.com>

Reviewed-by: Vincent Mailhol <mailhol@kernel.org>


Yours sincerely,
Vincent Mailhol


  parent reply	other threads:[~2026-06-09 19:35 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-09 14:29 [PATCH v5 0/8] can: flexcan: Add NXP S32N79 SoC support Ciprian Costea
2026-06-09 14:29 ` [PATCH v5 1/8] can: flexcan: use dedicated IRQ handlers for multi-IRQ platforms Ciprian Costea
2026-06-09 14:47   ` sashiko-bot
2026-06-09 19:35   ` Vincent Mailhol [this message]
2026-06-09 14:29 ` [PATCH v5 2/8] can: flexcan: disable all IRQ lines in flexcan_chip_interrupts_enable() Ciprian Costea
2026-06-09 14:42   ` sashiko-bot
2026-06-09 19:38   ` Vincent Mailhol
2026-06-09 14:29 ` [PATCH v5 3/8] can: flexcan: split rx/tx masks per mailbox IRQ line Ciprian Costea
2026-06-09 14:43   ` sashiko-bot
2026-06-09 19:42   ` Vincent Mailhol
2026-06-09 14:29 ` [PATCH v5 4/8] dt-bindings: can: fsl,flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-06-09 14:29 ` [PATCH v5 5/8] can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk Ciprian Costea
2026-06-09 14:43   ` sashiko-bot
2026-06-09 19:51   ` Vincent Mailhol
2026-06-09 14:29 ` [PATCH v5 6/8] can: flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-06-09 14:41   ` sashiko-bot
2026-06-09 19:52   ` Vincent Mailhol
2026-06-09 14:29 ` [PATCH v5 7/8] arm64: dts: s32n79: add FlexCAN nodes Ciprian Costea
2026-06-09 14:29 ` [PATCH v5 8/8] arm64: dts: s32n79: enable FlexCAN devices Ciprian Costea

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