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([2001:818:ea8e:7f00:2575:914:eedd:620e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4409d2aab65sm179544845e9.17.2025.04.29.01.26.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 01:26:29 -0700 (PDT) Message-ID: Subject: Re: [PATCH v3 09/11] iio: adc: adi-axi-adc: add num lanes support From: Nuno =?ISO-8859-1?Q?S=E1?= To: Antoniu Miclaus , jic23@kernel.org, robh@kernel.org, conor+dt@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Tue, 29 Apr 2025 09:26:34 +0100 In-Reply-To: <20250425112538.59792-10-antoniu.miclaus@analog.com> References: <20250425112538.59792-1-antoniu.miclaus@analog.com> <20250425112538.59792-10-antoniu.miclaus@analog.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2025-04-25 at 14:25 +0300, Antoniu Miclaus wrote: > Add support for setting the number of lanes enabled. >=20 > Signed-off-by: Antoniu Miclaus > --- Just one small comment below... With that addressed: Reviewed-by: Nuno S=C3=A1 > no changes in v3. > =C2=A0drivers/iio/adc/adi-axi-adc.c | 16 ++++++++++++++++ > =C2=A01 file changed, 16 insertions(+) >=20 > diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.= c > index bf0155830d87..8ff781ab5ec3 100644 > --- a/drivers/iio/adc/adi-axi-adc.c > +++ b/drivers/iio/adc/adi-axi-adc.c > @@ -44,6 +44,7 @@ > =C2=A0#define=C2=A0=C2=A0 ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) > =C2=A0 > =C2=A0#define ADI_AXI_ADC_REG_CTRL 0x0044 > +#define=C2=A0=C2=A0=C2=A0 AXI_AD408X_CTRL_NUM_LANES_MSK GENMASK(12, 8) > =C2=A0#define=C2=A0=C2=A0=C2=A0 AXI_AD408X_CTRL_SYNC_MSK BIT(3) > =C2=A0#define=C2=A0=C2=A0=C2=A0 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) > =C2=A0 > @@ -451,6 +452,19 @@ static int axi_adc_sync_status_get(struct iio_backen= d > *back, bool *sync_en) > =C2=A0 return 0; > =C2=A0} > =C2=A0 > +static int axi_adc_num_lanes_set(struct iio_backend *back, > + unsigned int num_lanes) > +{ > + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); > + > + if (!num_lanes) > + return -EINVAL; > + > + return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, > + =C2=A0 AXI_AD408X_CTRL_NUM_LANES_MSK, > + =C2=A0 FIELD_PREP(AXI_AD408X_CTRL_NUM_LANES_MSK, > num_lanes)); > +} > + > =C2=A0static struct iio_buffer *axi_adc_request_buffer(struct iio_backend= *back, > =C2=A0 struct iio_dev *indio_dev) > =C2=A0{ > @@ -601,6 +615,7 @@ static const struct iio_backend_ops adi_axi_adc_ops = =3D { > =C2=A0 .chan_status =3D axi_adc_chan_status, > =C2=A0 .interface_type_get =3D axi_adc_interface_type_get, > =C2=A0 .sync_status_get =3D axi_adc_sync_status_get, > + .num_lanes_set =3D axi_adc_num_lanes_set, Not sure if we should set this. Although it might be in the regular/default register map, I suppose that this not a generic feature all axi-adc backend= s inherit from the base design... So, if wrongly used, I guess it would resul= t in a no-op on the backend side. > =C2=A0 .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_adc_reg_access= ), > =C2=A0 .debugfs_print_chan_status =3D > iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), > =C2=A0}; > @@ -646,6 +661,7 @@ static const struct iio_backend_ops adi_ad408x_ops = =3D { > =C2=A0 .data_alignment_enable =3D axi_adc_sync_enable, > =C2=A0 .data_alignment_disable =3D axi_adc_sync_disable, > =C2=A0 .sync_status_get =3D axi_adc_sync_status_get, > + .num_lanes_set =3D axi_adc_num_lanes_set, > =C2=A0 .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_adc_reg_access= ), > =C2=A0 .debugfs_print_chan_status =3D > iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), > =C2=A0};