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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.3-1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Rob, On Thu, 2024-07-11 at 09:51 -0600, Rob Herring wrote: > On Wed, Jul 10, 2024 at 7:29=E2=80=AFAM Andr=C3=A9 Draszik wrote: > > --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml > > +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml > > @@ -145,6 +145,20 @@ allOf: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - samsung,uart-fifosiz= e > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 properties: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 reg-io-width: false >=20 > blank line between properties Do mean before clocks: below and before clock-names: below? We don't do tha= t normally, at least none of the bindings I looked at do that. Or did I misunderstand? > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clocks: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 description: | > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Not= e that for earlycon to work, the respective ipclk and pclk need > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 to = be running! The bootloader normally leaves them enabled, but the > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ser= ial driver will start handling those clocks before the console > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dri= ver takes over from earlycon, breaking earlycon. If earlycon is > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 req= uired, please revert the patch "clk: samsung: gs101: don't mark > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 non= -essential (UART) clocks critical" locally first to mark them > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CLK= _IS_CRITICAL and avoid this problem. >=20 > That's a whole bunch of details that are Linux specific which have > little to do with the binding. You're right - I had been asked to add this to the binding and didn't consi= der that. I think I found a much better alternative in the meantime and this description can go away. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 maxItems: 2 > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clock-names: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 items: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - c= onst: uart > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - c= onst: clk_uart_baud0 >=20 > Which clock is pclk and ipclk? uart is pclk, clk_uart_baud0 is ipclk. > 'baud' would be sufficient for the > name. 'clk_' and 'uart' are redundant because it's all clocks and they > are all for the uart. TBH, this patch is just following the existing style & names as already exi= st for various other SoCs in this same file. Furthermore, up until this patch the = default from this file applies, which is: clock-names: description: N =3D 0 is allowed for SoCs without internal baud clock mu= x. minItems: 2 items: - const: uart - pattern: '^clk_uart_baud[0-3]$' - pattern: '^clk_uart_baud[0-3]$' - pattern: '^clk_uart_baud[0-3]$' - pattern: '^clk_uart_baud[0-3]$' so of course the existing gs101 DTs had followed this scheme. Other SoCs th= at are described in this same binding also keep the name as per the default in cas= e they limit the maximum number like this patch does. Changing the name now would be a bit disruptive and make gs101 differ from = other Exynos SoCs in this respect, I'd rather not :-) Cheers, Andre'