[PATCH v2 0/8] soc: qcom: Add uart console support for SM4450

[PATCH v2 0/8] soc: qcom: Add uart console support for SM4450

[Tengfei Fan]

This series add base description of UART, TLMM, interconnect, TCSRCC
RPMHCC, GCC, RPMh PD and SMMU nodes which helps SM4450 boot to shell
with console on boards with this SoC.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
This patch series depends on below patch series:
"[PATCH v2 0/4] clk: qcom: Add support for GCC and RPMHCC on SM4450"
https://lore.kernel.org/linux-arm-msm/20230909123431.1725728-1-quic_ajipan@quicinc.com/
"[PATCH v2 0/2] pinctl: qcom: Add SM4450 pinctrl driver"
https://lore.kernel.org/linux-arm-msm/20230915015808.18296-1-quic_tengfan@quicinc.com/
"[PATCH v2 0/2] interconnect: qcom: Add SM4450 interconnect"
https://lore.kernel.org/linux-arm-msm/20230915020129.19611-1-quic_tengfan@quicinc.com/

v1 -> v2:
  - setting "qcom,rpmh-rsc" compatible to the first property
  - keep order by unit address
  - move tlmm node into soc node
  - update arm,smmu.yaml
  - add enable pinctrl and interconnect defconfig patches
  - remove blank line
  - redo dtbs_check check

previous discussion here:
[1]
https://lore.kernel.org/linux-arm-msm/20230908065847.28382-1-quic_tengfan@quicinc.com

Ajit Pandey (2):
  arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node
  arm64: dts: qcom: sm4450: Add RPMH and Global clock controller

Tengfei Fan (6):
  dt-bindings: firmware: document Qualcomm SM4450 SCM
  dt-bindings: mfd: qcom,tcsr: Add compatible for sm4450
  dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm4450-pdc
  dt-bindings: arm-smmu: Add compatible for SM4450 SoC
  arm64: dts: qcom: add uart console support for SM4450
  arm64: defconfig: enable interconnect and pinctrl for SM4450

 .../bindings/firmware/qcom,scm.yaml           |   3 +
 .../interrupt-controller/qcom,pdc.yaml        |   1 +
 .../devicetree/bindings/iommu/arm,smmu.yaml   |   3 +
 .../devicetree/bindings/mfd/qcom,tcsr.yaml    |   1 +
 arch/arm64/boot/dts/qcom/sm4450-qrd.dts       |  18 +-
 arch/arm64/boot/dts/qcom/sm4450.dtsi          | 309 ++++++++++++++++++
 arch/arm64/configs/defconfig                  |   2 +
 7 files changed, 335 insertions(+), 2 deletions(-)


base-commit: 98897dc735cf6635f0966f76eb0108354168fb15
-- 
2.17.1

[PATCH v2 1/8] dt-bindings: firmware: document Qualcomm SM4450 SCM

[Tengfei Fan]

Document the compatible for Qualcomm SM4450 SCM.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index 4233ea839bfc..1cff4e11f732 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -52,6 +52,7 @@ properties:
           - qcom,scm-sdx55
           - qcom,scm-sdx65
           - qcom,scm-sdx75
+          - qcom,scm-sm4450
           - qcom,scm-sm6115
           - qcom,scm-sm6125
           - qcom,scm-sm6350
@@ -177,6 +178,7 @@ allOf:
               enum:
                 - qcom,scm-qdu1000
                 - qcom,scm-sc8280xp
+                - qcom,scm-sm4450
                 - qcom,scm-sm8450
                 - qcom,scm-sm8550
     then:
@@ -190,6 +192,7 @@ allOf:
           compatible:
             contains:
               enum:
+                - qcom,scm-sm4450
                 - qcom,scm-sm8450
                 - qcom,scm-sm8550
     then:
-- 
2.17.1

[PATCH v2 4/8] dt-bindings: arm-smmu: Add compatible for SM4450 SoC

[Tengfei Fan]

Add the SoC specific compatible for SM4450 implementing arm,mmu-500.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index cf29ab10501c..b57751c8ad90 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -47,6 +47,7 @@ properties:
               - qcom,sdx55-smmu-500
               - qcom,sdx65-smmu-500
               - qcom,sdx75-smmu-500
+              - qcom,sm4450-smmu-500
               - qcom,sm6115-smmu-500
               - qcom,sm6125-smmu-500
               - qcom,sm6350-smmu-500
@@ -70,6 +71,7 @@ properties:
               - qcom,sc8180x-smmu-500
               - qcom,sc8280xp-smmu-500
               - qcom,sdm845-smmu-500
+              - qcom,sm4450-smmu-500
               - qcom,sm6115-smmu-500
               - qcom,sm6350-smmu-500
               - qcom,sm6375-smmu-500
@@ -468,6 +470,7 @@ allOf:
               - qcom,sdm845-smmu-500
               - qcom,sdx55-smmu-500
               - qcom,sdx65-smmu-500
+              - qcom,sm4450-smmu-500
               - qcom,sm6350-smmu-500
               - qcom,sm6375-smmu-500
               - qcom,sm8350-smmu-500
-- 
2.17.1

Re: [PATCH v2 4/8] dt-bindings: arm-smmu: Add compatible for SM4450 SoC

[Krzysztof Kozlowski]

On 15/09/2023 04:15, Tengfei Fan wrote:
> Add the SoC specific compatible for SM4450 implementing arm,mmu-500.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index cf29ab10501c..b57751c8ad90 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -47,6 +47,7 @@ properties:
>                - qcom,sdx55-smmu-500
>                - qcom,sdx65-smmu-500
>                - qcom,sdx75-smmu-500
> +              - qcom,sm4450-smmu-500
>                - qcom,sm6115-smmu-500
>                - qcom,sm6125-smmu-500
>                - qcom,sm6350-smmu-500
> @@ -70,6 +71,7 @@ properties:
>                - qcom,sc8180x-smmu-500
>                - qcom,sc8280xp-smmu-500
>                - qcom,sdm845-smmu-500
> +              - qcom,sm4450-smmu-500

Isn't there comment just few lines above your edit? Comment saying DON'T?


Best regards,
Krzysztof

Re: [PATCH v2 4/8] dt-bindings: arm-smmu: Add compatible for SM4450 SoC

[Tengfei Fan]

在 9/15/2023 3:11 PM, Krzysztof Kozlowski 写道:
> On 15/09/2023 04:15, Tengfei Fan wrote:
>> Add the SoC specific compatible for SM4450 implementing arm,mmu-500.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> index cf29ab10501c..b57751c8ad90 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> @@ -47,6 +47,7 @@ properties:
>>                 - qcom,sdx55-smmu-500
>>                 - qcom,sdx65-smmu-500
>>                 - qcom,sdx75-smmu-500
>> +              - qcom,sm4450-smmu-500
>>                 - qcom,sm6115-smmu-500
>>                 - qcom,sm6125-smmu-500
>>                 - qcom,sm6350-smmu-500
>> @@ -70,6 +71,7 @@ properties:
>>                 - qcom,sc8180x-smmu-500
>>                 - qcom,sc8280xp-smmu-500
>>                 - qcom,sdm845-smmu-500
>> +              - qcom,sm4450-smmu-500
> 
> Isn't there comment just few lines above your edit? Comment saying DON'T?
yes, I saw this "DON'T" comment, but if I remove "qcom,sm4450-smmu-500" 
from sm4450.dtsi and this arm,smmu.yaml, will get DT check warning about 
this, this warning cannot be find after add "qcom,sm4450-smmu-500" from 
sm4450.dtsi and this arm,smmu.yaml, so update this patch again.
> 
> 
> Best regards,
> Krzysztof
> 

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH v2 4/8] dt-bindings: arm-smmu: Add compatible for SM4450 SoC

[Krzysztof Kozlowski]

On 15/09/2023 09:15, Tengfei Fan wrote:
> 
> 
> 在 9/15/2023 3:11 PM, Krzysztof Kozlowski 写道:
>> On 15/09/2023 04:15, Tengfei Fan wrote:
>>> Add the SoC specific compatible for SM4450 implementing arm,mmu-500.
>>>
>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>> ---
>>>   Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
>>>   1 file changed, 3 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>>> index cf29ab10501c..b57751c8ad90 100644
>>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>>> @@ -47,6 +47,7 @@ properties:
>>>                 - qcom,sdx55-smmu-500
>>>                 - qcom,sdx65-smmu-500
>>>                 - qcom,sdx75-smmu-500
>>> +              - qcom,sm4450-smmu-500
>>>                 - qcom,sm6115-smmu-500
>>>                 - qcom,sm6125-smmu-500
>>>                 - qcom,sm6350-smmu-500
>>> @@ -70,6 +71,7 @@ properties:
>>>                 - qcom,sc8180x-smmu-500
>>>                 - qcom,sc8280xp-smmu-500
>>>                 - qcom,sdm845-smmu-500
>>> +              - qcom,sm4450-smmu-500
>>
>> Isn't there comment just few lines above your edit? Comment saying DON'T?
> yes, I saw this "DON'T" comment, but if I remove "qcom,sm4450-smmu-500" 
> from sm4450.dtsi and this arm,smmu.yaml, will get DT check warning about 

Why would you remove it?

> this, this warning cannot be find after add "qcom,sm4450-smmu-500" from 
> sm4450.dtsi and this arm,smmu.yaml, so update this patch again.

What does the comment say? Why are you adding it to the enum which asks
- do not add to this enum, but add to other above and below?


Best regards,
Krzysztof

Re: [PATCH v2 4/8] dt-bindings: arm-smmu: Add compatible for SM4450 SoC

[Tengfei Fan]

在 9/15/2023 3:11 PM, Krzysztof Kozlowski 写道:
> On 15/09/2023 04:15, Tengfei Fan wrote:
>> Add the SoC specific compatible for SM4450 implementing arm,mmu-500.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> index cf29ab10501c..b57751c8ad90 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> @@ -47,6 +47,7 @@ properties:
>>                 - qcom,sdx55-smmu-500
>>                 - qcom,sdx65-smmu-500
>>                 - qcom,sdx75-smmu-500
>> +              - qcom,sm4450-smmu-500
>>                 - qcom,sm6115-smmu-500
>>                 - qcom,sm6125-smmu-500
>>                 - qcom,sm6350-smmu-500
>> @@ -70,6 +71,7 @@ properties:
>>                 - qcom,sc8180x-smmu-500
>>                 - qcom,sc8280xp-smmu-500
>>                 - qcom,sdm845-smmu-500
>> +              - qcom,sm4450-smmu-500
> 
> Isn't there comment just few lines above your edit? Comment saying DON'T?
> 
> 
> Best regards,
> Krzysztof
> 
Hi Kraysztof
I seems haven't understand your comments totaly.
I want to confirm that if you think only need "qcom,smmu-500" and 
"arm,mmu-500" compitbale name, needn't specific compitable name for each 
platform?

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH v2 4/8] dt-bindings: arm-smmu: Add compatible for SM4450 SoC

[Krzysztof Kozlowski]

On 15/09/2023 10:52, Tengfei Fan wrote:
> 
> 
> 在 9/15/2023 3:11 PM, Krzysztof Kozlowski 写道:
>> On 15/09/2023 04:15, Tengfei Fan wrote:
>>> Add the SoC specific compatible for SM4450 implementing arm,mmu-500.
>>>
>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>> ---
>>>   Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
>>>   1 file changed, 3 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>>> index cf29ab10501c..b57751c8ad90 100644
>>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>>> @@ -47,6 +47,7 @@ properties:
>>>                 - qcom,sdx55-smmu-500
>>>                 - qcom,sdx65-smmu-500
>>>                 - qcom,sdx75-smmu-500
>>> +              - qcom,sm4450-smmu-500
>>>                 - qcom,sm6115-smmu-500
>>>                 - qcom,sm6125-smmu-500
>>>                 - qcom,sm6350-smmu-500
>>> @@ -70,6 +71,7 @@ properties:
>>>                 - qcom,sc8180x-smmu-500
>>>                 - qcom,sc8280xp-smmu-500
>>>                 - qcom,sdm845-smmu-500
>>> +              - qcom,sm4450-smmu-500
>>
>> Isn't there comment just few lines above your edit? Comment saying DON'T?
>>
>>
>> Best regards,
>> Krzysztof
>>
> Hi Kraysztof
> I seems haven't understand your comments totaly.
> I want to confirm that if you think only need "qcom,smmu-500" and 
> "arm,mmu-500" compitbale name, needn't specific compitable name for each 
> platform?


No, please read the comment. It tells you explicitly what to do - which
compatible add where.

Best regards,
Krzysztof

[PATCH v2 2/8] dt-bindings: mfd: qcom,tcsr: Add compatible for sm4450

[Tengfei Fan]

Document the qcom,sm4450-tcsr compatible.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
index 5ad9d5deaaf8..33c3d023a106 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
@@ -27,6 +27,7 @@ properties:
           - qcom,sdm845-tcsr
           - qcom,sdx55-tcsr
           - qcom,sdx65-tcsr
+          - qcom,sm4450-tcsr
           - qcom,sm8150-tcsr
           - qcom,sm8450-tcsr
           - qcom,tcsr-apq8064
-- 
2.17.1

[PATCH v2 3/8] dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm4450-pdc

[Tengfei Fan]

Add SM4450 PDC, which will used in SM4450 DTS.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
index 4847b04be1a1..86d61896f591 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
@@ -35,6 +35,7 @@ properties:
           - qcom,sdm845-pdc
           - qcom,sdx55-pdc
           - qcom,sdx65-pdc
+          - qcom,sm4450-pdc
           - qcom,sm6350-pdc
           - qcom,sm8150-pdc
           - qcom,sm8250-pdc
-- 
2.17.1

[PATCH v2 4/8] dt-bindings: arm-smmu: Add compatible for SM4450 SoC

[Tengfei Fan]

Add the SoC specific compatible for SM4450 implementing arm,mmu-500.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index cf29ab10501c..b57751c8ad90 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -47,6 +47,7 @@ properties:
               - qcom,sdx55-smmu-500
               - qcom,sdx65-smmu-500
               - qcom,sdx75-smmu-500
+              - qcom,sm4450-smmu-500
               - qcom,sm6115-smmu-500
               - qcom,sm6125-smmu-500
               - qcom,sm6350-smmu-500
@@ -70,6 +71,7 @@ properties:
               - qcom,sc8180x-smmu-500
               - qcom,sc8280xp-smmu-500
               - qcom,sdm845-smmu-500
+              - qcom,sm4450-smmu-500
               - qcom,sm6115-smmu-500
               - qcom,sm6350-smmu-500
               - qcom,sm6375-smmu-500
@@ -468,6 +470,7 @@ allOf:
               - qcom,sdm845-smmu-500
               - qcom,sdx55-smmu-500
               - qcom,sdx65-smmu-500
+              - qcom,sm4450-smmu-500
               - qcom,sm6350-smmu-500
               - qcom,sm6375-smmu-500
               - qcom,sm8350-smmu-500
-- 
2.17.1

Re: [PATCH v2 4/8] dt-bindings: arm-smmu: Add compatible for SM4450 SoC

[Krzysztof Kozlowski]

On 15/09/2023 04:15, Tengfei Fan wrote:
> Add the SoC specific compatible for SM4450 implementing arm,mmu-500.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index cf29ab10501c..b57751c8ad90 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -47,6 +47,7 @@ properties:
>                - qcom,sdx55-smmu-500
>                - qcom,sdx65-smmu-500
>                - qcom,sdx75-smmu-500
> +              - qcom,sm4450-smmu-500
>                - qcom,sm6115-smmu-500
>                - qcom,sm6125-smmu-500
>                - qcom,sm6350-smmu-500
> @@ -70,6 +71,7 @@ properties:
>                - qcom,sc8180x-smmu-500
>                - qcom,sc8280xp-smmu-500
>                - qcom,sdm845-smmu-500
> +              - qcom,sm4450-smmu-500

Duplicated patch. Same problem.

Best regards,
Krzysztof

[PATCH v2 5/8] arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node

[Tengfei Fan]

From: Ajit Pandey <quic_ajipan@quicinc.com>

Add apps_rsc node and cmd_db memory region for sm4450.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm4450.dtsi | 34 ++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index c4e5b33f5169..0d1d39197d77 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -328,6 +329,18 @@
 		};
 	};
 
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		aop_cmd_db_mem: cmd-db@80860000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x80860000 0x0 0x20000>;
+			no-map;
+		};
+	};
+
 	soc: soc@0 {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -335,6 +348,27 @@
 		dma-ranges = <0 0 0 0 0x10 0>;
 		compatible = "simple-bus";
 
+		apps_rsc: rsc@17a00000 {
+			compatible = "qcom,rpmh-rsc";
+			reg = <0 0x17a00000 0 0x10000>,
+			      <0 0x17a10000 0 0x10000>,
+			      <0 0x17a20000 0 0x10000>;
+			reg-names = "drv-0", "drv-1", "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			label = "apps_rsc";
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS    2>, <SLEEP_TCS     3>,
+					  <WAKE_TCS      3>, <CONTROL_TCS   0>;
+			power-domains = <&CLUSTER_PD>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x0 0x01f40000 0x0 0x40000>;
-- 
2.17.1

Re: [PATCH v2 5/8] arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node

[Bjorn Andersson]

On Fri, Sep 15, 2023 at 10:15:06AM +0800, Tengfei Fan wrote:
> From: Ajit Pandey <quic_ajipan@quicinc.com>
> 
> Add apps_rsc node and cmd_db memory region for sm4450.
> 
> Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm4450.dtsi | 34 ++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> index c4e5b33f5169..0d1d39197d77 100644
> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> @@ -5,6 +5,7 @@
>  
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  
>  / {
>  	interrupt-parent = <&intc>;
> @@ -328,6 +329,18 @@
>  		};
>  	};
>  
> +	reserved_memory: reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		aop_cmd_db_mem: cmd-db@80860000 {
> +			compatible = "qcom,cmd-db";
> +			reg = <0x0 0x80860000 0x0 0x20000>;
> +			no-map;
> +		};
> +	};
> +
>  	soc: soc@0 {
>  		#address-cells = <2>;
>  		#size-cells = <2>;
> @@ -335,6 +348,27 @@
>  		dma-ranges = <0 0 0 0 0x10 0>;
>  		compatible = "simple-bus";
>  
> +		apps_rsc: rsc@17a00000 {
> +			compatible = "qcom,rpmh-rsc";
> +			reg = <0 0x17a00000 0 0x10000>,

As your later patch shows, and Krzysztof pointed out, the sort order is
wrong here (sort nodes under /soc by address).

> +			      <0 0x17a10000 0 0x10000>,
> +			      <0 0x17a20000 0 0x10000>;
> +			reg-names = "drv-0", "drv-1", "drv-2";
> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +			label = "apps_rsc";
> +			qcom,tcs-offset = <0xd00>;
> +			qcom,drv-id = <2>;
> +			qcom,tcs-config = <ACTIVE_TCS    2>, <SLEEP_TCS     3>,
> +					  <WAKE_TCS      3>, <CONTROL_TCS   0>;

Please confirm that you indeed want 0 CONTROL_TCSs.

Thanks,
Bjorn

> +			power-domains = <&CLUSTER_PD>;
> +
> +			apps_bcm_voter: bcm-voter {
> +				compatible = "qcom,bcm-voter";
> +			};
> +		};
> +
>  		tcsr_mutex: hwlock@1f40000 {
>  			compatible = "qcom,tcsr-mutex";
>  			reg = <0x0 0x01f40000 0x0 0x40000>;
> -- 
> 2.17.1
> 

Re: [PATCH v2 5/8] arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node

[Tengfei Fan]

在 9/20/2023 11:49 AM, Bjorn Andersson 写道:
> On Fri, Sep 15, 2023 at 10:15:06AM +0800, Tengfei Fan wrote:
>> From: Ajit Pandey <quic_ajipan@quicinc.com>
>>
>> Add apps_rsc node and cmd_db memory region for sm4450.
>>
>> Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm4450.dtsi | 34 ++++++++++++++++++++++++++++
>>   1 file changed, 34 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> index c4e5b33f5169..0d1d39197d77 100644
>> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> @@ -5,6 +5,7 @@
>>   
>>   #include <dt-bindings/gpio/gpio.h>
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>>   
>>   / {
>>   	interrupt-parent = <&intc>;
>> @@ -328,6 +329,18 @@
>>   		};
>>   	};
>>   
>> +	reserved_memory: reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		aop_cmd_db_mem: cmd-db@80860000 {
>> +			compatible = "qcom,cmd-db";
>> +			reg = <0x0 0x80860000 0x0 0x20000>;
>> +			no-map;
>> +		};
>> +	};
>> +
>>   	soc: soc@0 {
>>   		#address-cells = <2>;
>>   		#size-cells = <2>;
>> @@ -335,6 +348,27 @@
>>   		dma-ranges = <0 0 0 0 0x10 0>;
>>   		compatible = "simple-bus";
>>   
>> +		apps_rsc: rsc@17a00000 {
>> +			compatible = "qcom,rpmh-rsc";
>> +			reg = <0 0x17a00000 0 0x10000>,
> 
> As your later patch shows, and Krzysztof pointed out, the sort order is
> wrong here (sort nodes under /soc by address).
I will ajdust this sort order.
> 
>> +			      <0 0x17a10000 0 0x10000>,
>> +			      <0 0x17a20000 0 0x10000>;
>> +			reg-names = "drv-0", "drv-1", "drv-2";
>> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>> +			label = "apps_rsc";
>> +			qcom,tcs-offset = <0xd00>;
>> +			qcom,drv-id = <2>;
>> +			qcom,tcs-config = <ACTIVE_TCS    2>, <SLEEP_TCS     3>,
>> +					  <WAKE_TCS      3>, <CONTROL_TCS   0>;
> 
> Please confirm that you indeed want 0 CONTROL_TCSs.
> 
> Thanks,
> Bjorn
Hi Bjorn,
yes, I confirmed this from internal power team, CONTROL_TCS with 0 is ok.
> 
>> +			power-domains = <&CLUSTER_PD>;
>> +
>> +			apps_bcm_voter: bcm-voter {
>> +				compatible = "qcom,bcm-voter";
>> +			};
>> +		};
>> +
>>   		tcsr_mutex: hwlock@1f40000 {
>>   			compatible = "qcom,tcsr-mutex";
>>   			reg = <0x0 0x01f40000 0x0 0x40000>;
>> -- 
>> 2.17.1
>>

-- 
Thx and BRs,
Tengfei Fan

[PATCH v2 6/8] arm64: dts: qcom: sm4450: Add RPMH and Global clock controller

[Tengfei Fan]

From: Ajit Pandey <quic_ajipan@quicinc.com>

Add device node for RPMH and Global clock controller on Qualcomm
SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm4450.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index 0d1d39197d77..df59027a2f93 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -3,6 +3,8 @@
  * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm4450-gcc.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -367,6 +369,22 @@
 			apps_bcm_voter: bcm-voter {
 				compatible = "qcom,bcm-voter";
 			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sm4450-rpmh-clk";
+				#clock-cells = <1>;
+				clock-names = "xo";
+				clocks = <&xo_board>;
+			};
+		};
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,sm4450-gcc";
+			reg = <0x0 0x00100000 0x0 0x1f4200>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
 		};
 
 		tcsr_mutex: hwlock@1f40000 {
-- 
2.17.1

Re: [PATCH v2 6/8] arm64: dts: qcom: sm4450: Add RPMH and Global clock controller

[Krzysztof Kozlowski]

On 15/09/2023 04:15, Tengfei Fan wrote:
> From: Ajit Pandey <quic_ajipan@quicinc.com>
> 
> Add device node for RPMH and Global clock controller on Qualcomm
> SM4450 platform.
> 
> Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>

Warnings in your code:
sm4450-qrd.dtb: clock-controller@100000: clocks: [[28, 0], [29]] is too
short



Best regards,
Krzysztof

Re: [PATCH v2 6/8] arm64: dts: qcom: sm4450: Add RPMH and Global clock controller

[Tengfei Fan]

在 9/15/2023 3:22 PM, Krzysztof Kozlowski 写道:
> On 15/09/2023 04:15, Tengfei Fan wrote:
>> From: Ajit Pandey <quic_ajipan@quicinc.com>
>>
>> Add device node for RPMH and Global clock controller on Qualcomm
>> SM4450 platform.
>>
>> Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> 
> Warnings in your code:
> sm4450-qrd.dtb: clock-controller@100000: clocks: [[28, 0], [29]] is too
> short
> 
> 
> 
> Best regards,
> Krzysztof
> 
Hi Krzyszrof,
Want to know how did you find this warning?
I cannot find this warning when I do dt check(make ARCH=arm64 
DT_CHECKER_FLAGS=-m dtbs_check) or kernel compile(make -j8 ARCH=arm64 
CROSS_COMPILE=aarch64-linux-gnu- Image.gz dtbs modules).

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH v2 6/8] arm64: dts: qcom: sm4450: Add RPMH and Global clock controller

[Krzysztof Kozlowski]

On 18/09/2023 12:34, Tengfei Fan wrote:
> 
> 
> 在 9/15/2023 3:22 PM, Krzysztof Kozlowski 写道:
>> On 15/09/2023 04:15, Tengfei Fan wrote:
>>> From: Ajit Pandey <quic_ajipan@quicinc.com>
>>>
>>> Add device node for RPMH and Global clock controller on Qualcomm
>>> SM4450 platform.
>>>
>>> Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>
>> Warnings in your code:
>> sm4450-qrd.dtb: clock-controller@100000: clocks: [[28, 0], [29]] is too
>> short
>>
>>
>>
>> Best regards,
>> Krzysztof
>>
> Hi Krzyszrof,
> Want to know how did you find this warning?
> I cannot find this warning when I do dt check(make ARCH=arm64 
> DT_CHECKER_FLAGS=-m dtbs_check) or kernel compile(make -j8 ARCH=arm64 
> CROSS_COMPILE=aarch64-linux-gnu- Image.gz dtbs modules).
> 

I just applied dependencies and these patches, and run dtbs_check.

Best regards,
Krzysztof

[PATCH v2 7/8] arm64: dts: qcom: add uart console support for SM4450

[Tengfei Fan]

Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes
which helps SM4450 boot to shell with console on boards with this SoC.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm4450-qrd.dts |  18 +-
 arch/arm64/boot/dts/qcom/sm4450.dtsi    | 313 +++++++++++++++++++++---
 2 files changed, 301 insertions(+), 30 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
index 00a1c81ca397..0f253a2ba170 100644
--- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
@@ -10,9 +10,23 @@
 	model = "Qualcomm Technologies, Inc. SM4450 QRD";
 	compatible = "qcom,sm4450-qrd", "qcom,sm4450";
 
-	aliases { };
+	aliases {
+		serial0 = &uart7;
+	};
 
 	chosen {
-		bootargs = "console=hvc0";
+		stdout-path = "serial0:115200n8";
 	};
 };
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&tlmm {
+	gpio-reserved-ranges = <0 4>, <136 1>;
+};
+
+&uart7 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index df59027a2f93..3af976478d0d 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -7,6 +7,8 @@
 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sm4450.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
@@ -262,6 +264,26 @@
 		};
 	};
 
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-sm4450", "qcom,scm";
+			interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
+			#reset-cells = <1>;
+		};
+	};
+
+	clk_virt: interconnect-0 {
+		compatible = "qcom,sm4450-clk-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect-1 {
+		compatible = "qcom,sm4450-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
 	memory@a0000000 {
 		device_type = "memory";
 		/* We expect the bootloader to fill in the size */
@@ -350,34 +372,6 @@
 		dma-ranges = <0 0 0 0 0x10 0>;
 		compatible = "simple-bus";
 
-		apps_rsc: rsc@17a00000 {
-			compatible = "qcom,rpmh-rsc";
-			reg = <0 0x17a00000 0 0x10000>,
-			      <0 0x17a10000 0 0x10000>,
-			      <0 0x17a20000 0 0x10000>;
-			reg-names = "drv-0", "drv-1", "drv-2";
-			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-			label = "apps_rsc";
-			qcom,tcs-offset = <0xd00>;
-			qcom,drv-id = <2>;
-			qcom,tcs-config = <ACTIVE_TCS    2>, <SLEEP_TCS     3>,
-					  <WAKE_TCS      3>, <CONTROL_TCS   0>;
-			power-domains = <&CLUSTER_PD>;
-
-			apps_bcm_voter: bcm-voter {
-				compatible = "qcom,bcm-voter";
-			};
-
-			rpmhcc: clock-controller {
-				compatible = "qcom,sm4450-rpmh-clk";
-				#clock-cells = <1>;
-				clock-names = "xo";
-				clocks = <&xo_board>;
-			};
-		};
-
 		gcc: clock-controller@100000 {
 			compatible = "qcom,sm4450-gcc";
 			reg = <0x0 0x00100000 0x0 0x1f4200>;
@@ -387,12 +381,111 @@
 			clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
 		};
 
+		qupv3_id_0: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x00ac0000 0x0 0x2000>;
+			ranges;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			iommus = <&apps_smmu 0x163 0x0>;
+			interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
+			interconnect-names = "qup-core";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			uart7: serial@a88000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
+				status = "disabled";
+			};
+		};
+
+		cnoc2: interconnect@1500000 {
+			compatible = "qcom,sm4450-cnoc2";
+			reg = <0 0x1500000 0 0x6200>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		cnoc3: interconnect@1510000 {
+			compatible = "qcom,sm4450-cnoc3";
+			reg = <0 0x01510000 0 0xF200>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		system_noc: interconnect@1680000 {
+			compatible = "qcom,sm4450-system-noc";
+			reg = <0 0x1680000 0 0x19080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		pcie_anoc: interconnect@16c0000 {
+			compatible = "qcom,sm4450-pcie-anoc";
+			reg = <0 0x16C0000 0 0x7080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
+				 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+		};
+
+		aggre1_noc: interconnect@16e0000 {
+			tible = "qcom,sm4450-aggre1-noc";
+			reg = <0 0x016e0000 0 0x1c080>;
+			#interconnect-cells = <2>;
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre2_noc: interconnect@1700000 {
+			compatible = "qcom,sm4450-aggre2-noc";
+			reg = <0 0x01700000 0 0x31080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			clocks = <&rpmhcc RPMH_IPA_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+		};
+
+		mmss_noc: interconnect@1740000 {
+			compatible = "qcom,sm4450-mmss-noc";
+			reg = <0 0x1740000 0 0x19080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		video_aggre_noc: interconnect@1760000 {
+			compatible = "qcom,sm4450-video-aggre-noc";
+			reg = <0 0x1760000 0 0x1100>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x0 0x01f40000 0x0 0x40000>;
 			#hwlock-cells = <1>;
 		};
 
+		tcsr: syscon@1fc0000 {
+			compatible = "qcom,sm4450-tcsr", "syscon";
+			reg = <0x0 0x1fc0000 0x0 0x30000>;
+		};
+
+		lpass_ag_noc: interconnect@3c40000 {
+			compatible = "qcom,sm4450-lpass-ag-noc";
+			reg = <0 0x3C40000 0 0x17200>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,sm4450-pdc", "qcom,pdc";
 			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
@@ -403,6 +496,135 @@
 			interrupt-controller;
 		};
 
+		tlmm: pinctrl@f100000 {
+			compatible = "qcom,sm4450-tlmm";
+			reg = <0 0x0f100000 0 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 137>;
+			wakeup-parent = <&pdc>;
+
+			qup_uart7_rx: qup-uart7-rx-state {
+				pins = "gpio22";
+				function = "qup1_se2_l2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_uart7_tx: qup-uart7-tx-state {
+				pins = "gpio22";
+				function = "qup1_se2_l2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sm4450-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0 0x15000000 0 0x100000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		intc: interrupt-controller@17200000 {
 			compatible = "arm,gic-v3";
 			reg = <0x0 0x17200000 0x0 0x10000>,     /* GICD */
@@ -471,6 +693,41 @@
 				status = "disabled";
 			};
 		};
+
+		apps_rsc: rsc@17a00000 {
+			compatible = "qcom,rpmh-rsc";
+			reg = <0 0x17a00000 0 0x10000>,
+			      <0 0x17a10000 0 0x10000>,
+			      <0 0x17a20000 0 0x10000>;
+			reg-names = "drv-0", "drv-1", "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			label = "apps_rsc";
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS    2>, <SLEEP_TCS     3>,
+					  <WAKE_TCS      3>, <CONTROL_TCS   0>;
+			power-domains = <&CLUSTER_PD>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sm4450-rpmh-clk";
+				#clock-cells = <1>;
+				clock-names = "xo";
+				clocks = <&xo_board>;
+			};
+		};
+
+		gem_noc: interconnect@19100000 {
+			compatible = "qcom,sm4450-gem-noc";
+			reg = <0 0x19100000 0 0xBC080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
 	};
 
 	timer {
-- 
2.17.1

Re: [PATCH v2 7/8] arm64: dts: qcom: add uart console support for SM4450

[Krzysztof Kozlowski]

On 15/09/2023 04:15, Tengfei Fan wrote:
> Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes
> which helps SM4450 boot to shell with console on boards with this SoC.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm4450-qrd.dts |  18 +-
>  arch/arm64/boot/dts/qcom/sm4450.dtsi    | 313 +++++++++++++++++++++---
>  2 files changed, 301 insertions(+), 30 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> index 00a1c81ca397..0f253a2ba170 100644
> --- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> @@ -10,9 +10,23 @@
>  	model = "Qualcomm Technologies, Inc. SM4450 QRD";
>  	compatible = "qcom,sm4450-qrd", "qcom,sm4450";
>  
> -	aliases { };
> +	aliases {
> +		serial0 = &uart7;
> +	};
>  
>  	chosen {
> -		bootargs = "console=hvc0";
> +		stdout-path = "serial0:115200n8";
>  	};
>  };
> +
> +&qupv3_id_0 {
> +	status = "okay";
> +};
> +
> +&tlmm {
> +	gpio-reserved-ranges = <0 4>, <136 1>;
> +};
> +
> +&uart7 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> index df59027a2f93..3af976478d0d 100644
> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> @@ -7,6 +7,8 @@
>  #include <dt-bindings/clock/qcom,sm4450-gcc.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,sm4450.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  
>  / {
> @@ -262,6 +264,26 @@
>  		};
>  	};
>  
> +	firmware {
> +		scm: scm {
> +			compatible = "qcom,scm-sm4450", "qcom,scm";
> +			interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
> +			#reset-cells = <1>;
> +		};
> +	};
> +
> +	clk_virt: interconnect-0 {
> +		compatible = "qcom,sm4450-clk-virt";
> +		#interconnect-cells = <2>;
> +		qcom,bcm-voters = <&apps_bcm_voter>;
> +	};
> +
> +	mc_virt: interconnect-1 {
> +		compatible = "qcom,sm4450-mc-virt";
> +		#interconnect-cells = <2>;
> +		qcom,bcm-voters = <&apps_bcm_voter>;
> +	};
> +
>  	memory@a0000000 {
>  		device_type = "memory";
>  		/* We expect the bootloader to fill in the size */
> @@ -350,34 +372,6 @@
>  		dma-ranges = <0 0 0 0 0x10 0>;
>  		compatible = "simple-bus";
>  
> -		apps_rsc: rsc@17a00000 {
> -			compatible = "qcom,rpmh-rsc";

You just added this entire node few patches ago. This does not make any
sense.

> -			reg = <0 0x17a00000 0 0x10000>,
> -			      <0 0x17a10000 0 0x10000>,
> -			      <0 0x17a20000 0 0x10000>;
> -			reg-names = "drv-0", "drv-1", "drv-2";
> -			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> -			label = "apps_rsc";
> -			qcom,tcs-offset = <0xd00>;
> -			qcom,drv-id = <2>;
> -			qcom,tcs-config = <ACTIVE_TCS    2>, <SLEEP_TCS     3>,
> -					  <WAKE_TCS      3>, <CONTROL_TCS   0>;
> -			power-domains = <&CLUSTER_PD>;
> -
> -			apps_bcm_voter: bcm-voter {
> -				compatible = "qcom,bcm-voter";
> -			};
> -
> -			rpmhcc: clock-controller {
> -				compatible = "qcom,sm4450-rpmh-clk";
> -				#clock-cells = <1>;
> -				clock-names = "xo";
> -				clocks = <&xo_board>;
> -			};
> -		};
> -
>  		gcc: clock-controller@100000 {
>  			compatible = "qcom,sm4450-gcc";
>  			reg = <0x0 0x00100000 0x0 0x1f4200>;
> @@ -387,12 +381,111 @@
>  			clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>  		};
>  
> +		qupv3_id_0: geniqup@ac0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x0 0x00ac0000 0x0 0x2000>;
> +			ranges;
> +			clock-names = "m-ahb", "s-ahb";
> +			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> +			iommus = <&apps_smmu 0x163 0x0>;
> +			interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
> +			interconnect-names = "qup-core";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			status = "disabled";
> +
> +			uart7: serial@a88000 {
> +				compatible = "qcom,geni-debug-uart";
> +				reg = <0 0x00a88000 0 0x4000>;
> +				clock-names = "se";
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> +				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		cnoc2: interconnect@1500000 {
> +			compatible = "qcom,sm4450-cnoc2";
> +			reg = <0 0x1500000 0 0x6200>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		cnoc3: interconnect@1510000 {
> +			compatible = "qcom,sm4450-cnoc3";
> +			reg = <0 0x01510000 0 0xF200>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		system_noc: interconnect@1680000 {
> +			compatible = "qcom,sm4450-system-noc";
> +			reg = <0 0x1680000 0 0x19080>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		pcie_anoc: interconnect@16c0000 {
> +			compatible = "qcom,sm4450-pcie-anoc";
> +			reg = <0 0x16C0000 0 0x7080>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +			clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
> +				 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
> +		};
> +
> +		aggre1_noc: interconnect@16e0000 {
> +			tible = "qcom,sm4450-aggre1-noc";
> +			reg = <0 0x016e0000 0 0x1c080>;
> +			#interconnect-cells = <2>;
> +			clocks = <&gcc GCC_SDCC2_AHB_CLK>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		aggre2_noc: interconnect@1700000 {
> +			compatible = "qcom,sm4450-aggre2-noc";
> +			reg = <0 0x01700000 0 0x31080>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +			clocks = <&rpmhcc RPMH_IPA_CLK>,
> +				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
> +		};
> +
> +		mmss_noc: interconnect@1740000 {
> +			compatible = "qcom,sm4450-mmss-noc";
> +			reg = <0 0x1740000 0 0x19080>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		video_aggre_noc: interconnect@1760000 {
> +			compatible = "qcom,sm4450-video-aggre-noc";
> +			reg = <0 0x1760000 0 0x1100>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>  		tcsr_mutex: hwlock@1f40000 {
>  			compatible = "qcom,tcsr-mutex";
>  			reg = <0x0 0x01f40000 0x0 0x40000>;
>  			#hwlock-cells = <1>;
>  		};
>  
> +		tcsr: syscon@1fc0000 {
> +			compatible = "qcom,sm4450-tcsr", "syscon";
> +			reg = <0x0 0x1fc0000 0x0 0x30000>;
> +		};
> +
> +		lpass_ag_noc: interconnect@3c40000 {
> +			compatible = "qcom,sm4450-lpass-ag-noc";
> +			reg = <0 0x3C40000 0 0x17200>;
> +			#interconnect-cells = <2>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>  		pdc: interrupt-controller@b220000 {
>  			compatible = "qcom,sm4450-pdc", "qcom,pdc";
>  			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
> @@ -403,6 +496,135 @@
>  			interrupt-controller;
>  		};
>  
> +		tlmm: pinctrl@f100000 {
> +			compatible = "qcom,sm4450-tlmm";
> +			reg = <0 0x0f100000 0 0x300000>;
> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			gpio-ranges = <&tlmm 0 0 137>;
> +			wakeup-parent = <&pdc>;
> +
> +			qup_uart7_rx: qup-uart7-rx-state {
> +				pins = "gpio22";
> +				function = "qup1_se2_l2";
> +				drive-strength = <2>;
> +				bias-disable;
> +			};
> +
> +			qup_uart7_tx: qup-uart7-tx-state {
> +				pins = "gpio22";
> +				function = "qup1_se2_l2";
> +				drive-strength = <2>;
> +				bias-disable;
> +			};
> +		};
> +
> +		apps_smmu: iommu@15000000 {
> +			compatible = "qcom,sm4450-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> +			reg = <0 0x15000000 0 0x100000>;
> +			#iommu-cells = <2>;
> +			#global-interrupts = <1>;
> +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>  		intc: interrupt-controller@17200000 {
>  			compatible = "arm,gic-v3";
>  			reg = <0x0 0x17200000 0x0 0x10000>,     /* GICD */
> @@ -471,6 +693,41 @@
>  				status = "disabled";
>  			};
>  		};
> +
> +		apps_rsc: rsc@17a00000 {
> +			compatible = "qcom,rpmh-rsc";
> +			reg = <0 0x17a00000 0 0x10000>,

No, you added it already in previous patch.


Best regards,
Krzysztof

Re: [PATCH v2 7/8] arm64: dts: qcom: add uart console support for SM4450

[Konrad Dybcio]

On 15.09.2023 04:15, Tengfei Fan wrote:
> Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes
> which helps SM4450 boot to shell with console on boards with this SoC.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
You're adding multiple independent hardware blocks at once.
This is impossible to bisect if anyone ever encounters an
issue with one of them.

Konrad

Re: [PATCH v2 7/8] arm64: dts: qcom: add uart console support for SM4450

[Tengfei Fan]

在 9/15/2023 8:12 PM, Konrad Dybcio 写道:
> On 15.09.2023 04:15, Tengfei Fan wrote:
>> Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes
>> which helps SM4450 boot to shell with console on boards with this SoC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
> You're adding multiple independent hardware blocks at once.
> This is impossible to bisect if anyone ever encounters an
> issue with one of them.
> 
> Konrad

Hi Konrad,

Because all these DT nodes are for support enable uart console. Put all 
these DT nodes in one patch to form a complete funcitonal body, so add 
multiple independent hardware blocks in one patch.

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH v2 7/8] arm64: dts: qcom: add uart console support for SM4450

[Bjorn Andersson]

On Fri, Sep 15, 2023 at 10:15:08AM +0800, Tengfei Fan wrote:
> Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes
> which helps SM4450 boot to shell with console on boards with this SoC.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm4450-qrd.dts |  18 +-
>  arch/arm64/boot/dts/qcom/sm4450.dtsi    | 313 +++++++++++++++++++++---
>  2 files changed, 301 insertions(+), 30 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> index 00a1c81ca397..0f253a2ba170 100644
> --- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
> @@ -10,9 +10,23 @@
>  	model = "Qualcomm Technologies, Inc. SM4450 QRD";
>  	compatible = "qcom,sm4450-qrd", "qcom,sm4450";
>  
> -	aliases { };
> +	aliases {
> +		serial0 = &uart7;
> +	};
>  
>  	chosen {
> -		bootargs = "console=hvc0";
> +		stdout-path = "serial0:115200n8";
>  	};
>  };
> +
> +&qupv3_id_0 {
> +	status = "okay";
> +};
> +
> +&tlmm {
> +	gpio-reserved-ranges = <0 4>, <136 1>;
> +};
> +
> +&uart7 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
[..]
> +		qupv3_id_0: geniqup@ac0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x0 0x00ac0000 0x0 0x2000>;
> +			ranges;
> +			clock-names = "m-ahb", "s-ahb";
> +			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> +			iommus = <&apps_smmu 0x163 0x0>;
> +			interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
> +			interconnect-names = "qup-core";

The patch ends up adding a smorgasbord of different things, some of
which do relate to giving you a console and others mostly not related at
all, because of the iommus and interconnects here.

If you omit these three properties from this, you can add the
console, then add iommu and interconnect nodes in three clear patches.


PS. Commit message says this is all needed for boot-to-shell, but I
don't think you need scm, nor tcsr nodes to achieve that.

Regards,
Bjorn

Re: [PATCH v2 7/8] arm64: dts: qcom: add uart console support for SM4450

[Tengfei Fan]

在 9/20/2023 11:47 AM, Bjorn Andersson 写道:
> On Fri, Sep 15, 2023 at 10:15:08AM +0800, Tengfei Fan wrote:
>> Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes
>> which helps SM4450 boot to shell with console on boards with this SoC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm4450-qrd.dts |  18 +-
>>   arch/arm64/boot/dts/qcom/sm4450.dtsi    | 313 +++++++++++++++++++++---
>>   2 files changed, 301 insertions(+), 30 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>> index 00a1c81ca397..0f253a2ba170 100644
>> --- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
>> @@ -10,9 +10,23 @@
>>   	model = "Qualcomm Technologies, Inc. SM4450 QRD";
>>   	compatible = "qcom,sm4450-qrd", "qcom,sm4450";
>>   
>> -	aliases { };
>> +	aliases {
>> +		serial0 = &uart7;
>> +	};
>>   
>>   	chosen {
>> -		bootargs = "console=hvc0";
>> +		stdout-path = "serial0:115200n8";
>>   	};
>>   };
>> +
>> +&qupv3_id_0 {
>> +	status = "okay";
>> +};
>> +
>> +&tlmm {
>> +	gpio-reserved-ranges = <0 4>, <136 1>;
>> +};
>> +
>> +&uart7 {
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> [..]
>> +		qupv3_id_0: geniqup@ac0000 {
>> +			compatible = "qcom,geni-se-qup";
>> +			reg = <0x0 0x00ac0000 0x0 0x2000>;
>> +			ranges;
>> +			clock-names = "m-ahb", "s-ahb";
>> +			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
>> +				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
>> +			iommus = <&apps_smmu 0x163 0x0>;
>> +			interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
>> +			interconnect-names = "qup-core";
> 
> The patch ends up adding a smorgasbord of different things, some of
> which do relate to giving you a console and others mostly not related at
> all, because of the iommus and interconnects here.
> 
> If you omit these three properties from this, you can add the
> console, then add iommu and interconnect nodes in three clear patches.
> 
> 
> PS. Commit message says this is all needed for boot-to-shell, but I
> don't think you need scm, nor tcsr nodes to achieve that.
> 
> Regards,
> Bjorn

Hi Bjorn,
checked and confirmed your comments, you are right, will remove not 
related code.

-- 
Thx and BRs,
Tengfei Fan

[PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Tengfei Fan]

Add the SM4450 interconnect and pinctrl drivers as built-in for
support the Qualcomm SM4450 platform to boot to uart shell.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ec59174b14db..e91993de865e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y
 CONFIG_PINCTRL_SDM660=y
 CONFIG_PINCTRL_SDM670=y
 CONFIG_PINCTRL_SDM845=y
+CONFIG_PINCTRL_SM4450=y
 CONFIG_PINCTRL_SM6115=y
 CONFIG_PINCTRL_SM6125=y
 CONFIG_PINCTRL_SM6350=y
@@ -1500,6 +1501,7 @@ CONFIG_INTERCONNECT_QCOM_SC7280=y
 CONFIG_INTERCONNECT_QCOM_SC8180X=y
 CONFIG_INTERCONNECT_QCOM_SC8280XP=y
 CONFIG_INTERCONNECT_QCOM_SDM845=y
+CONFIG_INTERCONNECT_QCOM_SM4450=y
 CONFIG_INTERCONNECT_QCOM_SM8150=m
 CONFIG_INTERCONNECT_QCOM_SM8250=m
 CONFIG_INTERCONNECT_QCOM_SM8350=m
-- 
2.17.1

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Krzysztof Kozlowski]

On 15/09/2023 04:15, Tengfei Fan wrote:
> Add the SM4450 interconnect and pinctrl drivers as built-in for
> support the Qualcomm SM4450 platform to boot to uart shell.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  arch/arm64/configs/defconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index ec59174b14db..e91993de865e 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y
>  CONFIG_PINCTRL_SDM660=y
>  CONFIG_PINCTRL_SDM670=y
>  CONFIG_PINCTRL_SDM845=y
> +CONFIG_PINCTRL_SM4450=y
>  CONFIG_PINCTRL_SM6115=y
>  CONFIG_PINCTRL_SM6125=y
>  CONFIG_PINCTRL_SM6350=y
> @@ -1500,6 +1501,7 @@ CONFIG_INTERCONNECT_QCOM_SC7280=y
>  CONFIG_INTERCONNECT_QCOM_SC8180X=y
>  CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>  CONFIG_INTERCONNECT_QCOM_SDM845=y
> +CONFIG_INTERCONNECT_QCOM_SM4450=y

Why it cannot be =m?

Best regards,
Krzysztof

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Tengfei Fan]

在 9/15/2023 3:21 PM, Krzysztof Kozlowski 写道:
> On 15/09/2023 04:15, Tengfei Fan wrote:
>> Add the SM4450 interconnect and pinctrl drivers as built-in for
>> support the Qualcomm SM4450 platform to boot to uart shell.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/configs/defconfig | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>> index ec59174b14db..e91993de865e 100644
>> --- a/arch/arm64/configs/defconfig
>> +++ b/arch/arm64/configs/defconfig
>> @@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y
>>   CONFIG_PINCTRL_SDM660=y
>>   CONFIG_PINCTRL_SDM670=y
>>   CONFIG_PINCTRL_SDM845=y
>> +CONFIG_PINCTRL_SM4450=y
>>   CONFIG_PINCTRL_SM6115=y
>>   CONFIG_PINCTRL_SM6125=y
>>   CONFIG_PINCTRL_SM6350=y
>> @@ -1500,6 +1501,7 @@ CONFIG_INTERCONNECT_QCOM_SC7280=y
>>   CONFIG_INTERCONNECT_QCOM_SC8180X=y
>>   CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>>   CONFIG_INTERCONNECT_QCOM_SDM845=y
>> +CONFIG_INTERCONNECT_QCOM_SM4450=y
> 
> Why it cannot be =m?
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
Because system haven't capacity of loading ko files at this time on 
SM4450 platform, so setting to "Y".

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Krzysztof Kozlowski]

On 15/09/2023 11:12, Tengfei Fan wrote:
> 
> 
> 在 9/15/2023 3:21 PM, Krzysztof Kozlowski 写道:
>> On 15/09/2023 04:15, Tengfei Fan wrote:
>>> Add the SM4450 interconnect and pinctrl drivers as built-in for
>>> support the Qualcomm SM4450 platform to boot to uart shell.
>>>
>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>> ---
>>>   arch/arm64/configs/defconfig | 2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>>> index ec59174b14db..e91993de865e 100644
>>> --- a/arch/arm64/configs/defconfig
>>> +++ b/arch/arm64/configs/defconfig
>>> @@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y
>>>   CONFIG_PINCTRL_SDM660=y
>>>   CONFIG_PINCTRL_SDM670=y
>>>   CONFIG_PINCTRL_SDM845=y
>>> +CONFIG_PINCTRL_SM4450=y
>>>   CONFIG_PINCTRL_SM6115=y
>>>   CONFIG_PINCTRL_SM6125=y
>>>   CONFIG_PINCTRL_SM6350=y
>>> @@ -1500,6 +1501,7 @@ CONFIG_INTERCONNECT_QCOM_SC7280=y
>>>   CONFIG_INTERCONNECT_QCOM_SC8180X=y
>>>   CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>>>   CONFIG_INTERCONNECT_QCOM_SDM845=y
>>> +CONFIG_INTERCONNECT_QCOM_SM4450=y
>>
>> Why it cannot be =m?
>>
>> Best regards,
>> Krzysztof
>>
> 
> Hi Krzysztof,
> Because system haven't capacity of loading ko files at this time on 
> SM4450 platform, so setting to "Y".

Hm? System has this capability. All systems have. What is so different
on SM4450 comparing to everything else we have here?

No, this should be =m and you need to fix your system.

Best regards,
Krzysztof

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Tengfei Fan]

在 9/15/2023 5:16 PM, Krzysztof Kozlowski 写道:
> On 15/09/2023 11:12, Tengfei Fan wrote:
>>
>>
>> 在 9/15/2023 3:21 PM, Krzysztof Kozlowski 写道:
>>> On 15/09/2023 04:15, Tengfei Fan wrote:
>>>> Add the SM4450 interconnect and pinctrl drivers as built-in for
>>>> support the Qualcomm SM4450 platform to boot to uart shell.
>>>>
>>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>>> ---
>>>>    arch/arm64/configs/defconfig | 2 ++
>>>>    1 file changed, 2 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>>>> index ec59174b14db..e91993de865e 100644
>>>> --- a/arch/arm64/configs/defconfig
>>>> +++ b/arch/arm64/configs/defconfig
>>>> @@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y
>>>>    CONFIG_PINCTRL_SDM660=y
>>>>    CONFIG_PINCTRL_SDM670=y
>>>>    CONFIG_PINCTRL_SDM845=y
>>>> +CONFIG_PINCTRL_SM4450=y
>>>>    CONFIG_PINCTRL_SM6115=y
>>>>    CONFIG_PINCTRL_SM6125=y
>>>>    CONFIG_PINCTRL_SM6350=y
>>>> @@ -1500,6 +1501,7 @@ CONFIG_INTERCONNECT_QCOM_SC7280=y
>>>>    CONFIG_INTERCONNECT_QCOM_SC8180X=y
>>>>    CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>>>>    CONFIG_INTERCONNECT_QCOM_SDM845=y
>>>> +CONFIG_INTERCONNECT_QCOM_SM4450=y
>>>
>>> Why it cannot be =m?
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>> Hi Krzysztof,
>> Because system haven't capacity of loading ko files at this time on
>> SM4450 platform, so setting to "Y".
> 
> Hm? System has this capability. All systems have. What is so different
> on SM4450 comparing to everything else we have here?
> 
> No, this should be =m and you need to fix your system.
> 
> Best regards,
> Krzysztof
> 
Hi Krzysztof,
Find new way which can load ko files on SM4450 platform, still need use 
"Y", because of some other modules have dependence to these two config, 
like scm, smmu module drivers, uart shell console cannot be got if set 
to "m".

Also do test for setting these two config to "m" on SM8450 platform, get 
uart shell consle failed if so setting.

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Krzysztof Kozlowski]

On 15/09/2023 13:18, Tengfei Fan wrote:
> 
> 
> 在 9/15/2023 5:16 PM, Krzysztof Kozlowski 写道:
>> On 15/09/2023 11:12, Tengfei Fan wrote:
>>>
>>>
>>> 在 9/15/2023 3:21 PM, Krzysztof Kozlowski 写道:
>>>> On 15/09/2023 04:15, Tengfei Fan wrote:
>>>>> Add the SM4450 interconnect and pinctrl drivers as built-in for
>>>>> support the Qualcomm SM4450 platform to boot to uart shell.
>>>>>
>>>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>>>> ---
>>>>>    arch/arm64/configs/defconfig | 2 ++
>>>>>    1 file changed, 2 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>>>>> index ec59174b14db..e91993de865e 100644
>>>>> --- a/arch/arm64/configs/defconfig
>>>>> +++ b/arch/arm64/configs/defconfig
>>>>> @@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y
>>>>>    CONFIG_PINCTRL_SDM660=y
>>>>>    CONFIG_PINCTRL_SDM670=y
>>>>>    CONFIG_PINCTRL_SDM845=y
>>>>> +CONFIG_PINCTRL_SM4450=y
>>>>>    CONFIG_PINCTRL_SM6115=y
>>>>>    CONFIG_PINCTRL_SM6125=y
>>>>>    CONFIG_PINCTRL_SM6350=y
>>>>> @@ -1500,6 +1501,7 @@ CONFIG_INTERCONNECT_QCOM_SC7280=y
>>>>>    CONFIG_INTERCONNECT_QCOM_SC8180X=y
>>>>>    CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>>>>>    CONFIG_INTERCONNECT_QCOM_SDM845=y
>>>>> +CONFIG_INTERCONNECT_QCOM_SM4450=y
>>>>
>>>> Why it cannot be =m?
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>>
>>> Hi Krzysztof,
>>> Because system haven't capacity of loading ko files at this time on
>>> SM4450 platform, so setting to "Y".
>>
>> Hm? System has this capability. All systems have. What is so different
>> on SM4450 comparing to everything else we have here?
>>
>> No, this should be =m and you need to fix your system.
>>
>> Best regards,
>> Krzysztof
>>
> Hi Krzysztof,
> Find new way which can load ko files on SM4450 platform, still need use 
> "Y", because of some other modules have dependence to these two config, 
> like scm, smmu module drivers, uart shell console cannot be got if set 
> to "m".

That's what I am asking, which device exactly needs it.

> 
> Also do test for setting these two config to "m" on SM8450 platform, get 
> uart shell consle failed if so setting.

Yeah, this we know, I did this. I am asking about SM4450.

Best regards,
Krzysztof

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Trilok Soni]

On 9/15/2023 4:29 AM, Krzysztof Kozlowski wrote:
> On 15/09/2023 13:18, Tengfei Fan wrote:
>>
>>
>> 在 9/15/2023 5:16 PM, Krzysztof Kozlowski 写道:
>>> On 15/09/2023 11:12, Tengfei Fan wrote:
>>>>
>>>>
>>>> 在 9/15/2023 3:21 PM, Krzysztof Kozlowski 写道:
>>>>> On 15/09/2023 04:15, Tengfei Fan wrote:
>>>>>> Add the SM4450 interconnect and pinctrl drivers as built-in for
>>>>>> support the Qualcomm SM4450 platform to boot to uart shell.
>>>>>>
>>>>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>>>>> ---
>>>>>>    arch/arm64/configs/defconfig | 2 ++
>>>>>>    1 file changed, 2 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>>>>>> index ec59174b14db..e91993de865e 100644
>>>>>> --- a/arch/arm64/configs/defconfig
>>>>>> +++ b/arch/arm64/configs/defconfig
>>>>>> @@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y
>>>>>>    CONFIG_PINCTRL_SDM660=y
>>>>>>    CONFIG_PINCTRL_SDM670=y
>>>>>>    CONFIG_PINCTRL_SDM845=y
>>>>>> +CONFIG_PINCTRL_SM4450=y
>>>>>>    CONFIG_PINCTRL_SM6115=y
>>>>>>    CONFIG_PINCTRL_SM6125=y
>>>>>>    CONFIG_PINCTRL_SM6350=y
>>>>>> @@ -1500,6 +1501,7 @@ CONFIG_INTERCONNECT_QCOM_SC7280=y
>>>>>>    CONFIG_INTERCONNECT_QCOM_SC8180X=y
>>>>>>    CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>>>>>>    CONFIG_INTERCONNECT_QCOM_SDM845=y
>>>>>> +CONFIG_INTERCONNECT_QCOM_SM4450=y
>>>>>
>>>>> Why it cannot be =m?
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>>
>>>> Hi Krzysztof,
>>>> Because system haven't capacity of loading ko files at this time on
>>>> SM4450 platform, so setting to "Y".
>>>
>>> Hm? System has this capability. All systems have. What is so different
>>> on SM4450 comparing to everything else we have here?
>>>
>>> No, this should be =m and you need to fix your system.
>>>
>>> Best regards,
>>> Krzysztof
>>>
>> Hi Krzysztof,
>> Find new way which can load ko files on SM4450 platform, still need use 
>> "Y", because of some other modules have dependence to these two config, 
>> like scm, smmu module drivers, uart shell console cannot be got if set 
>> to "m".
> 
> That's what I am asking, which device exactly needs it.
> 
>>
>> Also do test for setting these two config to "m" on SM8450 platform, get 
>> uart shell consle failed if so setting.
> 
> Yeah, this we know, I did this. I am asking about SM4450.

Why we have =m requirement when other drivers above are =Y?. Can we confirm
w/ Georgi? I am not aware that Interconnect drivers needs to be =m only.

CONFIG_INTERCONNECT_QCOM_SC8180X=y
CONFIG_INTERCONNECT_QCOM_SC8280XP=y
CONFIG_INTERCONNECT_QCOM_SDM845=y

-- 
---Trilok Soni

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Trilok Soni]

On 9/15/2023 7:21 PM, Trilok Soni wrote:
> On 9/15/2023 4:29 AM, Krzysztof Kozlowski wrote:
>> On 15/09/2023 13:18, Tengfei Fan wrote:
>>>
>>>
>>> 在 9/15/2023 5:16 PM, Krzysztof Kozlowski 写道:
>>>> On 15/09/2023 11:12, Tengfei Fan wrote:
>>>>>
>>>>>
>>>>> 在 9/15/2023 3:21 PM, Krzysztof Kozlowski 写道:
>>>>>> On 15/09/2023 04:15, Tengfei Fan wrote:
>>>>>>> Add the SM4450 interconnect and pinctrl drivers as built-in for
>>>>>>> support the Qualcomm SM4450 platform to boot to uart shell.
>>>>>>>
>>>>>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>>>>>> ---
>>>>>>>    arch/arm64/configs/defconfig | 2 ++
>>>>>>>    1 file changed, 2 insertions(+)
>>>>>>>
>>>>>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>>>>>>> index ec59174b14db..e91993de865e 100644
>>>>>>> --- a/arch/arm64/configs/defconfig
>>>>>>> +++ b/arch/arm64/configs/defconfig
>>>>>>> @@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y
>>>>>>>    CONFIG_PINCTRL_SDM660=y
>>>>>>>    CONFIG_PINCTRL_SDM670=y
>>>>>>>    CONFIG_PINCTRL_SDM845=y
>>>>>>> +CONFIG_PINCTRL_SM4450=y
>>>>>>>    CONFIG_PINCTRL_SM6115=y
>>>>>>>    CONFIG_PINCTRL_SM6125=y
>>>>>>>    CONFIG_PINCTRL_SM6350=y
>>>>>>> @@ -1500,6 +1501,7 @@ CONFIG_INTERCONNECT_QCOM_SC7280=y
>>>>>>>    CONFIG_INTERCONNECT_QCOM_SC8180X=y
>>>>>>>    CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>>>>>>>    CONFIG_INTERCONNECT_QCOM_SDM845=y
>>>>>>> +CONFIG_INTERCONNECT_QCOM_SM4450=y
>>>>>>
>>>>>> Why it cannot be =m?
>>>>>>
>>>>>> Best regards,
>>>>>> Krzysztof
>>>>>>
>>>>>
>>>>> Hi Krzysztof,
>>>>> Because system haven't capacity of loading ko files at this time on
>>>>> SM4450 platform, so setting to "Y".
>>>>
>>>> Hm? System has this capability. All systems have. What is so different
>>>> on SM4450 comparing to everything else we have here?
>>>>
>>>> No, this should be =m and you need to fix your system.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>> Hi Krzysztof,
>>> Find new way which can load ko files on SM4450 platform, still need use 
>>> "Y", because of some other modules have dependence to these two config, 
>>> like scm, smmu module drivers, uart shell console cannot be got if set 
>>> to "m".
>>
>> That's what I am asking, which device exactly needs it.
>>
>>>
>>> Also do test for setting these two config to "m" on SM8450 platform, get 
>>> uart shell consle failed if so setting.
>>
>> Yeah, this we know, I did this. I am asking about SM4450.
> 
> Why we have =m requirement when other drivers above are =Y?. Can we confirm
> w/ Georgi? I am not aware that Interconnect drivers needs to be =m only.
> 
> CONFIG_INTERCONNECT_QCOM_SC8180X=y
> CONFIG_INTERCONNECT_QCOM_SC8280XP=y
> CONFIG_INTERCONNECT_QCOM_SDM845=y

Complete list here, and it is inconsistent. Latest 8550 is also =y. Do we document
the reasons somewhere on why they are added as =y?

CONFIG_INTERCONNECT_QCOM=y
CONFIG_INTERCONNECT_QCOM_MSM8916=m
CONFIG_INTERCONNECT_QCOM_MSM8996=m
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
CONFIG_INTERCONNECT_QCOM_QCM2290=m
CONFIG_INTERCONNECT_QCOM_QCS404=m
CONFIG_INTERCONNECT_QCOM_SA8775P=y
CONFIG_INTERCONNECT_QCOM_SC7180=y
CONFIG_INTERCONNECT_QCOM_SC7280=y
CONFIG_INTERCONNECT_QCOM_SC8180X=y
CONFIG_INTERCONNECT_QCOM_SC8280XP=y
CONFIG_INTERCONNECT_QCOM_SDM845=y
CONFIG_INTERCONNECT_QCOM_SM8150=m
CONFIG_INTERCONNECT_QCOM_SM8250=m
CONFIG_INTERCONNECT_QCOM_SM8350=m
CONFIG_INTERCONNECT_QCOM_SM8450=y
CONFIG_INTERCONNECT_QCOM_SM8550=y

-- 
---Trilok Soni

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Georgi Djakov]

Hi Trilok,

On 16.09.23 5:25, Trilok Soni wrote:
> On 9/15/2023 7:21 PM, Trilok Soni wrote:
>> On 9/15/2023 4:29 AM, Krzysztof Kozlowski wrote:
>>> On 15/09/2023 13:18, Tengfei Fan wrote:
>>>>
>>>>
>>>> 在 9/15/2023 5:16 PM, Krzysztof Kozlowski 写道:
>>>>> On 15/09/2023 11:12, Tengfei Fan wrote:
>>>>>>
>>>>>>
>>>>>> 在 9/15/2023 3:21 PM, Krzysztof Kozlowski 写道:
>>>>>>> On 15/09/2023 04:15, Tengfei Fan wrote:
>>>>>>>> Add the SM4450 interconnect and pinctrl drivers as built-in for
>>>>>>>> support the Qualcomm SM4450 platform to boot to uart shell.
>>>>>>>>
>>>>>>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>>>>>>> ---
>>>>>>>>     arch/arm64/configs/defconfig | 2 ++
>>>>>>>>     1 file changed, 2 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>>>>>>>> index ec59174b14db..e91993de865e 100644
>>>>>>>> --- a/arch/arm64/configs/defconfig
>>>>>>>> +++ b/arch/arm64/configs/defconfig
>>>>>>>> @@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y
>>>>>>>>     CONFIG_PINCTRL_SDM660=y
>>>>>>>>     CONFIG_PINCTRL_SDM670=y
>>>>>>>>     CONFIG_PINCTRL_SDM845=y
>>>>>>>> +CONFIG_PINCTRL_SM4450=y
>>>>>>>>     CONFIG_PINCTRL_SM6115=y
>>>>>>>>     CONFIG_PINCTRL_SM6125=y
>>>>>>>>     CONFIG_PINCTRL_SM6350=y
>>>>>>>> @@ -1500,6 +1501,7 @@ CONFIG_INTERCONNECT_QCOM_SC7280=y
>>>>>>>>     CONFIG_INTERCONNECT_QCOM_SC8180X=y
>>>>>>>>     CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>>>>>>>>     CONFIG_INTERCONNECT_QCOM_SDM845=y
>>>>>>>> +CONFIG_INTERCONNECT_QCOM_SM4450=y
>>>>>>>
>>>>>>> Why it cannot be =m?
>>>>>>>
>>>>>>> Best regards,
>>>>>>> Krzysztof
>>>>>>>
>>>>>>
>>>>>> Hi Krzysztof,
>>>>>> Because system haven't capacity of loading ko files at this time on
>>>>>> SM4450 platform, so setting to "Y".
>>>>>
>>>>> Hm? System has this capability. All systems have. What is so different
>>>>> on SM4450 comparing to everything else we have here?
>>>>>
>>>>> No, this should be =m and you need to fix your system.
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>> Hi Krzysztof,
>>>> Find new way which can load ko files on SM4450 platform, still need use
>>>> "Y", because of some other modules have dependence to these two config,
>>>> like scm, smmu module drivers, uart shell console cannot be got if set
>>>> to "m".
>>>
>>> That's what I am asking, which device exactly needs it.
>>>
>>>>
>>>> Also do test for setting these two config to "m" on SM8450 platform, get
>>>> uart shell consle failed if so setting.
>>>
>>> Yeah, this we know, I did this. I am asking about SM4450.
>>
>> Why we have =m requirement when other drivers above are =Y?. Can we confirm
>> w/ Georgi? I am not aware that Interconnect drivers needs to be =m only.
>>
>> CONFIG_INTERCONNECT_QCOM_SC8180X=y
>> CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>> CONFIG_INTERCONNECT_QCOM_SDM845=y
> 
> Complete list here, and it is inconsistent. Latest 8550 is also =y. Do we document
> the reasons somewhere on why they are added as =y?
> 
> CONFIG_INTERCONNECT_QCOM=y
> CONFIG_INTERCONNECT_QCOM_MSM8916=m
> CONFIG_INTERCONNECT_QCOM_MSM8996=m
> CONFIG_INTERCONNECT_QCOM_OSM_L3=m
> CONFIG_INTERCONNECT_QCOM_QCM2290=m
> CONFIG_INTERCONNECT_QCOM_QCS404=m
> CONFIG_INTERCONNECT_QCOM_SA8775P=y
> CONFIG_INTERCONNECT_QCOM_SC7180=y
> CONFIG_INTERCONNECT_QCOM_SC7280=y
> CONFIG_INTERCONNECT_QCOM_SC8180X=y
> CONFIG_INTERCONNECT_QCOM_SC8280XP=y
> CONFIG_INTERCONNECT_QCOM_SDM845=y
> CONFIG_INTERCONNECT_QCOM_SM8150=m
> CONFIG_INTERCONNECT_QCOM_SM8250=m
> CONFIG_INTERCONNECT_QCOM_SM8350=m
> CONFIG_INTERCONNECT_QCOM_SM8450=y
> CONFIG_INTERCONNECT_QCOM_SM8550=y

If the device can boot (to console/initramfs) with =m, we go with that.
But if something critical like the UART depends on the interconnect
provider, then we make it built-in.

On SM8550 for example, we have enabled bandwidth scaling support for QUP
and that's why it needs to be =y.

It looks like on SM4450 this should be =y too.

Thanks,
Georgi

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Krzysztof Kozlowski]

On 16/09/2023 17:13, Georgi Djakov wrote:
>
>>
>> Complete list here, and it is inconsistent. Latest 8550 is also =y. Do we document
>> the reasons somewhere on why they are added as =y?
>>
>> CONFIG_INTERCONNECT_QCOM=y
>> CONFIG_INTERCONNECT_QCOM_MSM8916=m
>> CONFIG_INTERCONNECT_QCOM_MSM8996=m
>> CONFIG_INTERCONNECT_QCOM_OSM_L3=m
>> CONFIG_INTERCONNECT_QCOM_QCM2290=m
>> CONFIG_INTERCONNECT_QCOM_QCS404=m
>> CONFIG_INTERCONNECT_QCOM_SA8775P=y
>> CONFIG_INTERCONNECT_QCOM_SC7180=y
>> CONFIG_INTERCONNECT_QCOM_SC7280=y
>> CONFIG_INTERCONNECT_QCOM_SC8180X=y
>> CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>> CONFIG_INTERCONNECT_QCOM_SDM845=y
>> CONFIG_INTERCONNECT_QCOM_SM8150=m
>> CONFIG_INTERCONNECT_QCOM_SM8250=m
>> CONFIG_INTERCONNECT_QCOM_SM8350=m
>> CONFIG_INTERCONNECT_QCOM_SM8450=y
>> CONFIG_INTERCONNECT_QCOM_SM8550=y
> 
> If the device can boot (to console/initramfs) with =m, we go with that.
> But if something critical like the UART depends on the interconnect
> provider, then we make it built-in.
> 
> On SM8550 for example, we have enabled bandwidth scaling support for QUP
> and that's why it needs to be =y.
> 
> It looks like on SM4450 this should be =y too.

I asked why SM4450 has to be =y and there was no answer. The argument
that SM8450 is a module, is not applicable.

Best regards,
Krzysztof

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Georgi Djakov]

Hi Krzysztof,

On 16.09.23 23:32, Krzysztof Kozlowski wrote:
> On 16/09/2023 17:13, Georgi Djakov wrote:
>>
>>>
>>> Complete list here, and it is inconsistent. Latest 8550 is also =y. Do we document
>>> the reasons somewhere on why they are added as =y?
>>>
>>> CONFIG_INTERCONNECT_QCOM=y
>>> CONFIG_INTERCONNECT_QCOM_MSM8916=m
>>> CONFIG_INTERCONNECT_QCOM_MSM8996=m
>>> CONFIG_INTERCONNECT_QCOM_OSM_L3=m
>>> CONFIG_INTERCONNECT_QCOM_QCM2290=m
>>> CONFIG_INTERCONNECT_QCOM_QCS404=m
>>> CONFIG_INTERCONNECT_QCOM_SA8775P=y
>>> CONFIG_INTERCONNECT_QCOM_SC7180=y
>>> CONFIG_INTERCONNECT_QCOM_SC7280=y
>>> CONFIG_INTERCONNECT_QCOM_SC8180X=y
>>> CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>>> CONFIG_INTERCONNECT_QCOM_SDM845=y
>>> CONFIG_INTERCONNECT_QCOM_SM8150=m
>>> CONFIG_INTERCONNECT_QCOM_SM8250=m
>>> CONFIG_INTERCONNECT_QCOM_SM8350=m
>>> CONFIG_INTERCONNECT_QCOM_SM8450=y
>>> CONFIG_INTERCONNECT_QCOM_SM8550=y
>>
>> If the device can boot (to console/initramfs) with =m, we go with that.
>> But if something critical like the UART depends on the interconnect
>> provider, then we make it built-in.
>>
>> On SM8550 for example, we have enabled bandwidth scaling support for QUP
>> and that's why it needs to be =y.
>>
>> It looks like on SM4450 this should be =y too.
> 
> I asked why SM4450 has to be =y and there was no answer. The argument
> that SM8450 is a module, is not applicable.

 From the hardware description i see in patch 7, the serial engine depends
on some interconnect provider. But as the serial console driver is only
available as built-in, the interconnect provider also needs be built-in
for the UART device to probe and register the console.

So the answer to your question should be that this is needed by the UART
device (at least).

Such details of course deserve to be mentioned in the commit message of
this patch.

BR,
Georgi

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Krzysztof Kozlowski]

On 17/09/2023 00:55, Georgi Djakov wrote:
> Hi Krzysztof,
> 
> On 16.09.23 23:32, Krzysztof Kozlowski wrote:
>> On 16/09/2023 17:13, Georgi Djakov wrote:
>>>
>>>>
>>>> Complete list here, and it is inconsistent. Latest 8550 is also =y. Do we document
>>>> the reasons somewhere on why they are added as =y?
>>>>
>>>> CONFIG_INTERCONNECT_QCOM=y
>>>> CONFIG_INTERCONNECT_QCOM_MSM8916=m
>>>> CONFIG_INTERCONNECT_QCOM_MSM8996=m
>>>> CONFIG_INTERCONNECT_QCOM_OSM_L3=m
>>>> CONFIG_INTERCONNECT_QCOM_QCM2290=m
>>>> CONFIG_INTERCONNECT_QCOM_QCS404=m
>>>> CONFIG_INTERCONNECT_QCOM_SA8775P=y
>>>> CONFIG_INTERCONNECT_QCOM_SC7180=y
>>>> CONFIG_INTERCONNECT_QCOM_SC7280=y
>>>> CONFIG_INTERCONNECT_QCOM_SC8180X=y
>>>> CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>>>> CONFIG_INTERCONNECT_QCOM_SDM845=y
>>>> CONFIG_INTERCONNECT_QCOM_SM8150=m
>>>> CONFIG_INTERCONNECT_QCOM_SM8250=m
>>>> CONFIG_INTERCONNECT_QCOM_SM8350=m
>>>> CONFIG_INTERCONNECT_QCOM_SM8450=y
>>>> CONFIG_INTERCONNECT_QCOM_SM8550=y
>>>
>>> If the device can boot (to console/initramfs) with =m, we go with that.
>>> But if something critical like the UART depends on the interconnect
>>> provider, then we make it built-in.
>>>
>>> On SM8550 for example, we have enabled bandwidth scaling support for QUP
>>> and that's why it needs to be =y.
>>>
>>> It looks like on SM4450 this should be =y too.
>>
>> I asked why SM4450 has to be =y and there was no answer. The argument
>> that SM8450 is a module, is not applicable.
> 
>  From the hardware description i see in patch 7, the serial engine depends
> on some interconnect provider. But as the serial console driver is only
> available as built-in, the interconnect provider also needs be built-in
> for the UART device to probe and register the console.
> 
> So the answer to your question should be that this is needed by the UART
> device (at least).
> 
> Such details of course deserve to be mentioned in the commit message of
> this patch.

If you mean here the debug UART with console, then it is the same valid
reason as in my change for others. This should be mentioned in commit msg.

Best regards,
Krzysztof

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Tengfei Fan]

在 9/17/2023 3:35 PM, Krzysztof Kozlowski 写道:
> On 17/09/2023 00:55, Georgi Djakov wrote:
>> Hi Krzysztof,
>>
>> On 16.09.23 23:32, Krzysztof Kozlowski wrote:
>>> On 16/09/2023 17:13, Georgi Djakov wrote:
>>>>
>>>>>
>>>>> Complete list here, and it is inconsistent. Latest 8550 is also =y. Do we document
>>>>> the reasons somewhere on why they are added as =y?
>>>>>
>>>>> CONFIG_INTERCONNECT_QCOM=y
>>>>> CONFIG_INTERCONNECT_QCOM_MSM8916=m
>>>>> CONFIG_INTERCONNECT_QCOM_MSM8996=m
>>>>> CONFIG_INTERCONNECT_QCOM_OSM_L3=m
>>>>> CONFIG_INTERCONNECT_QCOM_QCM2290=m
>>>>> CONFIG_INTERCONNECT_QCOM_QCS404=m
>>>>> CONFIG_INTERCONNECT_QCOM_SA8775P=y
>>>>> CONFIG_INTERCONNECT_QCOM_SC7180=y
>>>>> CONFIG_INTERCONNECT_QCOM_SC7280=y
>>>>> CONFIG_INTERCONNECT_QCOM_SC8180X=y
>>>>> CONFIG_INTERCONNECT_QCOM_SC8280XP=y
>>>>> CONFIG_INTERCONNECT_QCOM_SDM845=y
>>>>> CONFIG_INTERCONNECT_QCOM_SM8150=m
>>>>> CONFIG_INTERCONNECT_QCOM_SM8250=m
>>>>> CONFIG_INTERCONNECT_QCOM_SM8350=m
>>>>> CONFIG_INTERCONNECT_QCOM_SM8450=y
>>>>> CONFIG_INTERCONNECT_QCOM_SM8550=y
>>>>
>>>> If the device can boot (to console/initramfs) with =m, we go with that.
>>>> But if something critical like the UART depends on the interconnect
>>>> provider, then we make it built-in.
>>>>
>>>> On SM8550 for example, we have enabled bandwidth scaling support for QUP
>>>> and that's why it needs to be =y.
>>>>
>>>> It looks like on SM4450 this should be =y too.
>>>
>>> I asked why SM4450 has to be =y and there was no answer. The argument
>>> that SM8450 is a module, is not applicable.
>>
>>   From the hardware description i see in patch 7, the serial engine depends
>> on some interconnect provider. But as the serial console driver is only
>> available as built-in, the interconnect provider also needs be built-in
>> for the UART device to probe and register the console.
>>
>> So the answer to your question should be that this is needed by the UART
>> device (at least).
>>
>> Such details of course deserve to be mentioned in the commit message of
>> this patch.
> 
> If you mean here the debug UART with console, then it is the same valid
> reason as in my change for others. This should be mentioned in commit msg.
> 
> Best regards,
> Krzysztof
> 
yes, will mention this valid reason in next patch commit message detailly.

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450

[Krzysztof Kozlowski]

On 16/09/2023 04:21, Trilok Soni wrote:

>>>> No, this should be =m and you need to fix your system.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>> Hi Krzysztof,
>>> Find new way which can load ko files on SM4450 platform, still need use 
>>> "Y", because of some other modules have dependence to these two config, 
>>> like scm, smmu module drivers, uart shell console cannot be got if set 
>>> to "m".
>>
>> That's what I am asking, which device exactly needs it.
>>
>>>
>>> Also do test for setting these two config to "m" on SM8450 platform, get 
>>> uart shell consle failed if so setting.
>>
>> Yeah, this we know, I did this. I am asking about SM4450.
> 
> Why we have =m requirement when other drivers above are =Y?. Can we confirm
> w/ Georgi? I am not aware that Interconnect drivers needs to be =m only.

There is a requirement of all drivers which can be a module, to be a module.

Best regards,
Krzysztof