Re: [PATCHv1] arm64: dts: agilex: add service layer, fpga manager and fpga region

[Dinh Nguyen <dinguyen@kernel.org>]

On 10/17/19 2:34 PM, richard.gong@linux.intel.com wrote:
> From: Richard Gong <richard.gong@intel.com>
> 
> Add service layer, fpga manager and fpga region to the device tree
> on Intel Agilex platform.
> 
> Signed-off-by: Richard Gong <richard.gong@intel.com>
> ---
>  arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 32 +++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> index 36abc25..94090c6 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> @@ -12,6 +12,19 @@
>  	#address-cells = <2>;
>  	#size-cells = <2>;
>  
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		service_reserved: svcbuffer@0 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x0 0x0 0x0 0x1000000>;
> +			alignment = <0x1000>;
> +			no-map;
> +		};
> +	};
> +
>  	cpus {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> @@ -81,6 +94,13 @@
>  		interrupt-parent = <&intc>;
>  		ranges = <0 0 0 0xffffffff>;
>  
> +		base_fpga_region {
> +			#address-cells = <0x1>;
> +			#size-cells = <0x1>;
> +			compatible = "fpga-region";
> +			fpga-mgr = <&fpga_mgr>;
> +		};
> +
>  		gmac0: ethernet@ff800000 {
>  			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
>  			reg = <0xff800000 0x2000>;
> @@ -442,5 +462,17 @@
>  
>  			status = "disabled";
>  		};
> +
> +		firmware {
> +			svc {
> +				compatible = "intel,stratix10-svc";
> +				method = "smc";
> +				memory-region = <&service_reserved>;
> +
> +				fpga_mgr: fpga-mgr {
> +					compatible = "intel,stratix10-soc-fpga-mgr";
> +				};
> +			};
> +		};
>  	};
>  };
> 

Applied.

Dinh