* [PATCH v3 1/5] dt-bindings: i2c: qcom-cci: Document SDM670 compatible
2024-08-19 22:10 [PATCH v3 0/5] Add SDM670 camera subsystem Richard Acayan
@ 2024-08-19 22:10 ` Richard Acayan
2024-08-20 6:23 ` Krzysztof Kozlowski
2024-08-20 8:40 ` Vladimir Zapolskiy
2024-08-19 22:10 ` [PATCH v3 2/5] dt-bindings: media: camss: Add qcom,sdm670-camss Richard Acayan
` (3 subsequent siblings)
4 siblings, 2 replies; 22+ messages in thread
From: Richard Acayan @ 2024-08-19 22:10 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Richard Acayan, linux-arm-msm, linux-i2c,
devicetree, linux-media
The CCI on the Snapdragon 670 is the interface for controlling camera
hardware over I2C. Add the compatible so it can be added to the SDM670
device tree.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
.../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index c33ae7b63b84..af6dd9a34fd4 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -27,6 +27,7 @@ properties:
- enum:
- qcom,sc7280-cci
- qcom,sc8280xp-cci
+ - qcom,sdm670-cci
- qcom,sdm845-cci
- qcom,sm6350-cci
- qcom,sm8250-cci
@@ -138,6 +139,23 @@ allOf:
- const: cci
- const: camss_ahb
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm670-cci
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: soc_ahb
+ - const: cpas_ahb
+ - const: cci
+
- if:
properties:
compatible:
--
2.46.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 1/5] dt-bindings: i2c: qcom-cci: Document SDM670 compatible
2024-08-19 22:10 ` [PATCH v3 1/5] dt-bindings: i2c: qcom-cci: Document SDM670 compatible Richard Acayan
@ 2024-08-20 6:23 ` Krzysztof Kozlowski
2024-08-20 8:40 ` Vladimir Zapolskiy
1 sibling, 0 replies; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-08-20 6:23 UTC (permalink / raw)
To: Richard Acayan
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, linux-arm-msm, linux-i2c, devicetree, linux-media
On Mon, Aug 19, 2024 at 06:10:53PM -0400, Richard Acayan wrote:
> The CCI on the Snapdragon 670 is the interface for controlling camera
> hardware over I2C. Add the compatible so it can be added to the SDM670
> device tree.
>
> @@ -138,6 +139,23 @@ allOf:
> - const: cci
> - const: camss_ahb
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdm670-cci
> + then:
> + properties:
> + clocks:
> + minItems: 4
maxItems: 4
> + clock-names:
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: i2c: qcom-cci: Document SDM670 compatible
2024-08-19 22:10 ` [PATCH v3 1/5] dt-bindings: i2c: qcom-cci: Document SDM670 compatible Richard Acayan
2024-08-20 6:23 ` Krzysztof Kozlowski
@ 2024-08-20 8:40 ` Vladimir Zapolskiy
1 sibling, 0 replies; 22+ messages in thread
From: Vladimir Zapolskiy @ 2024-08-20 8:40 UTC (permalink / raw)
To: Richard Acayan, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, linux-arm-msm, linux-i2c, devicetree, linux-media
On 8/20/24 01:10, Richard Acayan wrote:
> The CCI on the Snapdragon 670 is the interface for controlling camera
> hardware over I2C. Add the compatible so it can be added to the SDM670
> device tree.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> index c33ae7b63b84..af6dd9a34fd4 100644
> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> @@ -27,6 +27,7 @@ properties:
> - enum:
> - qcom,sc7280-cci
> - qcom,sc8280xp-cci
> + - qcom,sdm670-cci
> - qcom,sdm845-cci
> - qcom,sm6350-cci
> - qcom,sm8250-cci
> @@ -138,6 +139,23 @@ allOf:
> - const: cci
> - const: camss_ahb
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdm670-cci
> + then:
> + properties:
> + clocks:
> + minItems: 4
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: soc_ahb
> + - const: cpas_ahb
> + - const: cci
> +
> - if:
> properties:
> compatible:
After fixing a review comment by Krzysztof,
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 2/5] dt-bindings: media: camss: Add qcom,sdm670-camss
2024-08-19 22:10 [PATCH v3 0/5] Add SDM670 camera subsystem Richard Acayan
2024-08-19 22:10 ` [PATCH v3 1/5] dt-bindings: i2c: qcom-cci: Document SDM670 compatible Richard Acayan
@ 2024-08-19 22:10 ` Richard Acayan
2024-08-20 7:31 ` Krzysztof Kozlowski
2024-08-20 9:15 ` Vladimir Zapolskiy
2024-08-19 22:10 ` [PATCH v3 3/5] media: qcom: camss: add support for SDM670 camss Richard Acayan
` (2 subsequent siblings)
4 siblings, 2 replies; 22+ messages in thread
From: Richard Acayan @ 2024-08-19 22:10 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Richard Acayan, linux-arm-msm, linux-i2c,
devicetree, linux-media
As found in the Pixel 3a, the Snapdragon 670 has a camera subsystem with
3 CSIDs and 3 VFEs (including 1 VFE lite). Add this camera subsystem to
the bindings.
Adapted from SC8280XP camera subsystem.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
.../bindings/media/qcom,sdm670-camss.yaml | 319 ++++++++++++++++++
1 file changed, 319 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
diff --git a/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
new file mode 100644
index 000000000000..5789cf66a516
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
@@ -0,0 +1,319 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sdm670-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SDM670 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Richard Acayan <mailingradian@gmail.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sdm670-camss
+
+ clocks:
+ maxItems: 22
+
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: cpas_ahb
+ - const: csi0
+ - const: csi1
+ - const: csi2
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: gcc_camera_ahb
+ - const: gcc_camera_axi
+ - const: soc_ahb
+ - const: vfe0_axi
+ - const: vfe0
+ - const: vfe0_cphy_rx
+ - const: vfe1_axi
+ - const: vfe1
+ - const: vfe1_cphy_rx
+ - const: vfe_lite
+ - const: vfe_lite_cphy_rx
+
+ interrupts:
+ maxItems: 9
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite
+
+ iommus:
+ maxItems: 4
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data from CSIPHY0.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data from CSIPHY1.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data from CSIPHY2.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ reg:
+ maxItems: 9
+
+ reg-names:
+ items:
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: vfe0
+ - const: csid0
+ - const: vfe1
+ - const: csid1
+ - const: vfe_lite
+ - const: csid2
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+required:
+ - clock-names
+ - clocks
+ - compatible
+ - interrupts
+ - interrupt-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - reg
+ - reg-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,camcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss@ac65000 {
+ compatible = "qcom,sdm670-camss";
+
+ reg = <0 0x0ac65000 0 0x1000>,
+ <0 0x0ac66000 0 0x1000>,
+ <0 0x0ac67000 0 0x1000>,
+ <0 0x0acaf000 0 0x4000>,
+ <0 0x0acb3000 0 0x1000>,
+ <0 0x0acb6000 0 0x4000>,
+ <0 0x0acba000 0 0x1000>,
+ <0 0x0acc4000 0 0x4000>,
+ <0 0x0acc8000 0 0x1000>;
+ reg-names = "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "vfe0",
+ "csid0",
+ "vfe1",
+ "csid1",
+ "vfe_lite",
+ "csid2";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_AXI_CLK>,
+ <&camcc CAM_CC_SOC_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "csi0",
+ "csi1",
+ "csi2",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "gcc_camera_ahb",
+ "gcc_camera_axi",
+ "soc_ahb",
+ "vfe0_axi",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe1_axi",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "vfe_lite",
+ "vfe_lite_cphy_rx";
+
+ iommus = <&apps_smmu 0x808 0x0>,
+ <&apps_smmu 0x810 0x8>,
+ <&apps_smmu 0xc08 0x0>,
+ <&apps_smmu 0xc10 0x8>;
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "top";
+
+ vdda-phy-supply = <&vreg_l1a_1p225>;
+ vdda-pll-supply = <&vreg_l8a_1p8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy_ep0: endpoint {
+ clock-lanes = <7>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&front_sensor_ep>;
+ };
+ };
+ };
+ };
+ };
--
2.46.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 2/5] dt-bindings: media: camss: Add qcom,sdm670-camss
2024-08-19 22:10 ` [PATCH v3 2/5] dt-bindings: media: camss: Add qcom,sdm670-camss Richard Acayan
@ 2024-08-20 7:31 ` Krzysztof Kozlowski
2024-08-20 9:15 ` Vladimir Zapolskiy
1 sibling, 0 replies; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-08-20 7:31 UTC (permalink / raw)
To: Richard Acayan
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, linux-arm-msm, linux-i2c, devicetree, linux-media
On Mon, Aug 19, 2024 at 06:10:54PM -0400, Richard Acayan wrote:
> As found in the Pixel 3a, the Snapdragon 670 has a camera subsystem with
> 3 CSIDs and 3 VFEs (including 1 VFE lite). Add this camera subsystem to
> the bindings.
>
> Adapted from SC8280XP camera subsystem.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> .../bindings/media/qcom,sdm670-camss.yaml | 319 ++++++++++++++++++
> 1 file changed, 319 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
> new file mode 100644
> index 000000000000..5789cf66a516
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
> @@ -0,0 +1,319 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
No blank line here.
> +%YAML 1.2
With above:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: media: camss: Add qcom,sdm670-camss
2024-08-19 22:10 ` [PATCH v3 2/5] dt-bindings: media: camss: Add qcom,sdm670-camss Richard Acayan
2024-08-20 7:31 ` Krzysztof Kozlowski
@ 2024-08-20 9:15 ` Vladimir Zapolskiy
2024-08-20 9:56 ` Krzysztof Kozlowski
1 sibling, 1 reply; 22+ messages in thread
From: Vladimir Zapolskiy @ 2024-08-20 9:15 UTC (permalink / raw)
To: Richard Acayan, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, linux-arm-msm, linux-i2c, devicetree, linux-media
Hi Richard,
On 8/20/24 01:10, Richard Acayan wrote:
> As found in the Pixel 3a, the Snapdragon 670 has a camera subsystem with
> 3 CSIDs and 3 VFEs (including 1 VFE lite). Add this camera subsystem to
> the bindings.
>
> Adapted from SC8280XP camera subsystem.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> .../bindings/media/qcom,sdm670-camss.yaml | 319 ++++++++++++++++++
> 1 file changed, 319 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
> new file mode 100644
> index 000000000000..5789cf66a516
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml
> @@ -0,0 +1,319 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sdm670-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SDM670 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Richard Acayan <mailingradian@gmail.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,sdm670-camss
> +
> + clocks:
Please add
minItems: 22
> + maxItems: 22> +
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: cpas_ahb
> + - const: csi0
> + - const: csi1
> + - const: csi2
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: gcc_camera_ahb
> + - const: gcc_camera_axi
> + - const: soc_ahb
> + - const: vfe0_axi
> + - const: vfe0
> + - const: vfe0_cphy_rx
> + - const: vfe1_axi
> + - const: vfe1
> + - const: vfe1_cphy_rx
> + - const: vfe_lite
> + - const: vfe_lite_cphy_rx
> +
> + interrupts:
Please add
minItems: 9
> + maxItems: 9
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: vfe0
> + - const: vfe1
> + - const: vfe_lite
> +
> + iommus:
Please add
minItems: 4
> + maxItems: 4
> +
> + power-domains:
> + items:
> + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - const: ife0
> + - const: ife1
> + - const: top
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data from CSIPHY0.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data from CSIPHY1.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data from CSIPHY2.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + reg:
Please add
minItems: 9
> + maxItems: 9
> +
> + reg-names:
> + items:
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: vfe0
> + - const: csid0
> + - const: vfe1
> + - const: csid1
> + - const: vfe_lite
> + - const: csid2
Additionally I would suggest to put descriptions of 'reg' and 'reg-names'
properties right after 'compatible' one, this is in accordance to DTS Coding Style.
> + vdda-phy-supply:
> + description:
> + Phandle to a regulator supply to PHY core block.
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> +required:
> + - clock-names
> + - clocks
> + - compatible
> + - interrupts
> + - interrupt-names
> + - iommus
> + - power-domains
> + - power-domain-names
> + - reg
> + - reg-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,camcc-sdm845.h>
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
Okay.
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss@ac65000 {
> + compatible = "qcom,sdm670-camss";
> +
> + reg = <0 0x0ac65000 0 0x1000>,
> + <0 0x0ac66000 0 0x1000>,
> + <0 0x0ac67000 0 0x1000>,
> + <0 0x0acaf000 0 0x4000>,
> + <0 0x0acb3000 0 0x1000>,
> + <0 0x0acb6000 0 0x4000>,
> + <0 0x0acba000 0 0x1000>,
> + <0 0x0acc4000 0 0x4000>,
> + <0 0x0acc8000 0 0x1000>;
> + reg-names = "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "vfe0",
> + "csid0",
> + "vfe1",
> + "csid1",
> + "vfe_lite",
> + "csid2";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "vfe0",
> + "vfe1",
> + "vfe_lite";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_IFE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_1_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMERA_AXI_CLK>,
> + <&camcc CAM_CC_SOC_AHB_CLK>,
> + <&camcc CAM_CC_IFE_0_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_1_AXI_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "csi0",
> + "csi1",
> + "csi2",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "gcc_camera_ahb",
> + "gcc_camera_axi",
> + "soc_ahb",
> + "vfe0_axi",
> + "vfe0",
> + "vfe0_cphy_rx",
> + "vfe1_axi",
> + "vfe1",
> + "vfe1_cphy_rx",
> + "vfe_lite",
> + "vfe_lite_cphy_rx";
> +
> + iommus = <&apps_smmu 0x808 0x0>,
> + <&apps_smmu 0x810 0x8>,
> + <&apps_smmu 0xc08 0x0>,
> + <&apps_smmu 0xc10 0x8>;
> +
> + power-domains = <&camcc IFE_0_GDSC>,
> + <&camcc IFE_1_GDSC>,
> + <&camcc TITAN_TOP_GDSC>;
> + power-domain-names = "ife0",
> + "ife1",
> + "top";
> +
> + vdda-phy-supply = <&vreg_l1a_1p225>;
> + vdda-pll-supply = <&vreg_l8a_1p8>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + csiphy_ep0: endpoint {
> + clock-lanes = <7>;
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&front_sensor_ep>;
> + };
> + };
> + };
> + };
> + };
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 2/5] dt-bindings: media: camss: Add qcom,sdm670-camss
2024-08-20 9:15 ` Vladimir Zapolskiy
@ 2024-08-20 9:56 ` Krzysztof Kozlowski
2024-08-20 11:37 ` Vladimir Zapolskiy
0 siblings, 1 reply; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-08-20 9:56 UTC (permalink / raw)
To: Vladimir Zapolskiy, Richard Acayan, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Bryan O'Donoghue, Mauro Carvalho Chehab,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, linux-i2c,
devicetree, linux-media
On 20/08/2024 11:15, Vladimir Zapolskiy wrote:
> Hi Richard,
>
...
>> +
>> + clocks:
>
> Please add
>
> minItems: 22
>
>> + maxItems: 22> +
>> + clock-names:
>> + items:
>> + - const: camnoc_axi
>> + - const: cpas_ahb
>> + - const: csi0
>> + - const: csi1
>> + - const: csi2
>> + - const: csiphy0
>> + - const: csiphy0_timer
>> + - const: csiphy1
>> + - const: csiphy1_timer
>> + - const: csiphy2
>> + - const: csiphy2_timer
>> + - const: gcc_camera_ahb
>> + - const: gcc_camera_axi
>> + - const: soc_ahb
>> + - const: vfe0_axi
>> + - const: vfe0
>> + - const: vfe0_cphy_rx
>> + - const: vfe1_axi
>> + - const: vfe1
>> + - const: vfe1_cphy_rx
>> + - const: vfe_lite
>> + - const: vfe_lite_cphy_rx
>> +
>> + interrupts:
>
> Please add
>
> minItems: 9
>
>> + maxItems: 9
>> +
>> + interrupt-names:
>> + items:
>> + - const: csid0
>> + - const: csid1
>> + - const: csid2
>> + - const: csiphy0
>> + - const: csiphy1
>> + - const: csiphy2
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe_lite
>> +
>> + iommus:
>
> Please add
>
> minItems: 4>
>> + maxItems: 4
>> +
>> + power-domains:
>> + items:
>> + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
>> + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
>> + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
>> +
>> + power-domain-names:
>> + items:
>> + - const: ife0
>> + - const: ife1
>> + - const: top
>> +
>> + ports:
>> + $ref: /schemas/graph.yaml#/properties/ports
>> +
>> + description:
>> + CSI input ports.
>> +
>> + properties:
>> + port@0:
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>> + unevaluatedProperties: false
>> + description:
>> + Input port for receiving CSI data from CSIPHY0.
>> +
>> + properties:
>> + endpoint:
>> + $ref: video-interfaces.yaml#
>> + unevaluatedProperties: false
>> +
>> + properties:
>> + clock-lanes:
>> + maxItems: 1
>> +
>> + data-lanes:
>> + minItems: 1
>> + maxItems: 4
>> +
>> + required:
>> + - clock-lanes
>> + - data-lanes
>> +
>> + port@1:
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>> + unevaluatedProperties: false
>> + description:
>> + Input port for receiving CSI data from CSIPHY1.
>> +
>> + properties:
>> + endpoint:
>> + $ref: video-interfaces.yaml#
>> + unevaluatedProperties: false
>> +
>> + properties:
>> + clock-lanes:
>> + maxItems: 1
>> +
>> + data-lanes:
>> + minItems: 1
>> + maxItems: 4
>> +
>> + required:
>> + - clock-lanes
>> + - data-lanes
>> +
>> + port@2:
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>> + unevaluatedProperties: false
>> + description:
>> + Input port for receiving CSI data from CSIPHY2.
>> +
>> + properties:
>> + endpoint:
>> + $ref: video-interfaces.yaml#
>> + unevaluatedProperties: false
>> +
>> + properties:
>> + clock-lanes:
>> + maxItems: 1
>> +
>> + data-lanes:
>> + minItems: 1
>> + maxItems: 4
>> +
>> + required:
>> + - clock-lanes
>> + - data-lanes
>> +
>> + reg:
>
> Please add
>
> minItems: 9
None of above are necessary and this contradicts review we give to drop
these...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: media: camss: Add qcom,sdm670-camss
2024-08-20 9:56 ` Krzysztof Kozlowski
@ 2024-08-20 11:37 ` Vladimir Zapolskiy
0 siblings, 0 replies; 22+ messages in thread
From: Vladimir Zapolskiy @ 2024-08-20 11:37 UTC (permalink / raw)
To: Krzysztof Kozlowski, Richard Acayan, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Bryan O'Donoghue, Mauro Carvalho Chehab,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, linux-i2c,
devicetree, linux-media
Hi Krzysztof,
On 8/20/24 12:56, Krzysztof Kozlowski wrote:
> On 20/08/2024 11:15, Vladimir Zapolskiy wrote:
>> Hi Richard,
>>
>
> ...
>
>>> +
>>> + clocks:
>>
>> Please add
>>
>> minItems: 22
>>
>>> + maxItems: 22> +
>>> + clock-names:
>>> + items:
>>> + - const: camnoc_axi
>>> + - const: cpas_ahb
>>> + - const: csi0
>>> + - const: csi1
>>> + - const: csi2
>>> + - const: csiphy0
>>> + - const: csiphy0_timer
>>> + - const: csiphy1
>>> + - const: csiphy1_timer
>>> + - const: csiphy2
>>> + - const: csiphy2_timer
>>> + - const: gcc_camera_ahb
>>> + - const: gcc_camera_axi
>>> + - const: soc_ahb
>>> + - const: vfe0_axi
>>> + - const: vfe0
>>> + - const: vfe0_cphy_rx
>>> + - const: vfe1_axi
>>> + - const: vfe1
>>> + - const: vfe1_cphy_rx
>>> + - const: vfe_lite
>>> + - const: vfe_lite_cphy_rx
>>> +
>>> + interrupts:
>>
>> Please add
>>
>> minItems: 9
>>
>>> + maxItems: 9
>>> +
>>> + interrupt-names:
>>> + items:
>>> + - const: csid0
>>> + - const: csid1
>>> + - const: csid2
>>> + - const: csiphy0
>>> + - const: csiphy1
>>> + - const: csiphy2
>>> + - const: vfe0
>>> + - const: vfe1
>>> + - const: vfe_lite
>>> +
>>> + iommus:
>>
>> Please add
>>
>> minItems: 4>
>>> + maxItems: 4
>>> +
>>> + power-domains:
>>> + items:
>>> + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
>>> + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
>>> + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
>>> +
>>> + power-domain-names:
>>> + items:
>>> + - const: ife0
>>> + - const: ife1
>>> + - const: top
>>> +
>>> + ports:
>>> + $ref: /schemas/graph.yaml#/properties/ports
>>> +
>>> + description:
>>> + CSI input ports.
>>> +
>>> + properties:
>>> + port@0:
>>> + $ref: /schemas/graph.yaml#/$defs/port-base
>>> + unevaluatedProperties: false
>>> + description:
>>> + Input port for receiving CSI data from CSIPHY0.
>>> +
>>> + properties:
>>> + endpoint:
>>> + $ref: video-interfaces.yaml#
>>> + unevaluatedProperties: false
>>> +
>>> + properties:
>>> + clock-lanes:
>>> + maxItems: 1
>>> +
>>> + data-lanes:
>>> + minItems: 1
>>> + maxItems: 4
>>> +
>>> + required:
>>> + - clock-lanes
>>> + - data-lanes
>>> +
>>> + port@1:
>>> + $ref: /schemas/graph.yaml#/$defs/port-base
>>> + unevaluatedProperties: false
>>> + description:
>>> + Input port for receiving CSI data from CSIPHY1.
>>> +
>>> + properties:
>>> + endpoint:
>>> + $ref: video-interfaces.yaml#
>>> + unevaluatedProperties: false
>>> +
>>> + properties:
>>> + clock-lanes:
>>> + maxItems: 1
>>> +
>>> + data-lanes:
>>> + minItems: 1
>>> + maxItems: 4
>>> +
>>> + required:
>>> + - clock-lanes
>>> + - data-lanes
>>> +
>>> + port@2:
>>> + $ref: /schemas/graph.yaml#/$defs/port-base
>>> + unevaluatedProperties: false
>>> + description:
>>> + Input port for receiving CSI data from CSIPHY2.
>>> +
>>> + properties:
>>> + endpoint:
>>> + $ref: video-interfaces.yaml#
>>> + unevaluatedProperties: false
>>> +
>>> + properties:
>>> + clock-lanes:
>>> + maxItems: 1
>>> +
>>> + data-lanes:
>>> + minItems: 1
>>> + maxItems: 4
>>> +
>>> + required:
>>> + - clock-lanes
>>> + - data-lanes
>>> +
>>> + reg:
>>
>> Please add
>>
>> minItems: 9
>
>
> None of above are necessary and this contradicts review we give to drop
> these...
Thank you for the correction, I will memorize it.
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 3/5] media: qcom: camss: add support for SDM670 camss
2024-08-19 22:10 [PATCH v3 0/5] Add SDM670 camera subsystem Richard Acayan
2024-08-19 22:10 ` [PATCH v3 1/5] dt-bindings: i2c: qcom-cci: Document SDM670 compatible Richard Acayan
2024-08-19 22:10 ` [PATCH v3 2/5] dt-bindings: media: camss: Add qcom,sdm670-camss Richard Acayan
@ 2024-08-19 22:10 ` Richard Acayan
2024-08-20 9:45 ` Bryan O'Donoghue
2024-08-21 8:15 ` Vladimir Zapolskiy
2024-08-19 22:10 ` [PATCH v3 4/5] arm64: dts: qcom: sdm670: add camcc Richard Acayan
2024-08-19 22:10 ` [PATCH v3 5/5] arm64: dts: qcom: sdm670: add camss and cci Richard Acayan
4 siblings, 2 replies; 22+ messages in thread
From: Richard Acayan @ 2024-08-19 22:10 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Richard Acayan, linux-arm-msm, linux-i2c,
devicetree, linux-media
The camera subsystem for the SDM670 the same as on SDM845 except with
3 CSIPHY ports instead of 4. Add support for the SDM670 camera
subsystem.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
drivers/media/platform/qcom/camss/camss.c | 191 ++++++++++++++++++++++
1 file changed, 191 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 51b1d3550421..b2f22bfd8692 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -584,6 +584,185 @@ static const struct camss_subdev_resources vfe_res_660[] = {
}
};
+static const struct camss_subdev_resources csiphy_res_670[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = {},
+ .clock = { "soc_ahb", "cpas_ahb",
+ "csiphy0", "csiphy0_timer" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 240000000, 269333333 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+
+ /* CSIPHY1 */
+ {
+ .regulators = {},
+ .clock = { "soc_ahb", "cpas_ahb",
+ "csiphy1", "csiphy1_timer" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 240000000, 269333333 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+
+ /* CSIPHY2 */
+ {
+ .regulators = {},
+ .clock = { "soc_ahb", "cpas_ahb",
+ "csiphy2", "csiphy2_timer" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 240000000, 269333333 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ }
+};
+
+static const struct camss_subdev_resources csid_res_670[] = {
+ /* CSID0 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+ .clock = { "cpas_ahb", "soc_ahb", "vfe0",
+ "vfe0_cphy_rx", "csi0" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 100000000, 320000000, 404000000, 480000000, 600000000 },
+ { 384000000 },
+ { 19200000, 75000000, 384000000, 538666667 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+
+ /* CSID1 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+ .clock = { "cpas_ahb", "soc_ahb", "vfe1",
+ "vfe1_cphy_rx", "csi1" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 100000000, 320000000, 404000000, 480000000, 600000000 },
+ { 384000000 },
+ { 19200000, 75000000, 384000000, 538666667 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+
+ /* CSID2 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+ .clock = { "cpas_ahb", "soc_ahb", "vfe_lite",
+ "vfe_lite_cphy_rx", "csi2" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 100000000, 320000000, 404000000, 480000000, 600000000 },
+ { 384000000 },
+ { 19200000, 75000000, 384000000, 538666667 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
+static const struct camss_subdev_resources vfe_res_670[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+ .clock = { "camnoc_axi", "cpas_ahb", "soc_ahb",
+ "vfe0", "vfe0_axi" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 100000000, 320000000, 404000000, 480000000, 600000000 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 4,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+
+ /* VFE1 */
+ {
+ .regulators = {},
+ .clock = { "camnoc_axi", "cpas_ahb", "soc_ahb",
+ "vfe1", "vfe1_axi" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 100000000, 320000000, 404000000, 480000000, 600000000 },
+ { 0 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 4,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+
+ /* VFE-lite */
+ {
+ .regulators = {},
+ .clock = { "camnoc_axi", "cpas_ahb", "soc_ahb",
+ "vfe_lite" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 100000000, 320000000, 404000000, 480000000, 600000000 } },
+ .reg = { "vfe_lite" },
+ .interrupt = { "vfe_lite" },
+ .vfe = {
+ .is_lite = true,
+ .line_num = 4,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ }
+};
+
static const struct camss_subdev_resources csiphy_res_845[] = {
/* CSIPHY0 */
{
@@ -2403,6 +2582,17 @@ static const struct camss_resources sdm660_resources = {
.link_entities = camss_link_entities
};
+static const struct camss_resources sdm670_resources = {
+ .version = CAMSS_845,
+ .csiphy_res = csiphy_res_670,
+ .csid_res = csid_res_670,
+ .vfe_res = vfe_res_670,
+ .csiphy_num = ARRAY_SIZE(csiphy_res_670),
+ .csid_num = ARRAY_SIZE(csid_res_670),
+ .vfe_num = ARRAY_SIZE(vfe_res_670),
+ .link_entities = camss_link_entities
+};
+
static const struct camss_resources sdm845_resources = {
.version = CAMSS_845,
.csiphy_res = csiphy_res_845,
@@ -2447,6 +2637,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
+ { .compatible = "qcom,sdm670-camss", .data = &sdm670_resources },
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
--
2.46.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 3/5] media: qcom: camss: add support for SDM670 camss
2024-08-19 22:10 ` [PATCH v3 3/5] media: qcom: camss: add support for SDM670 camss Richard Acayan
@ 2024-08-20 9:45 ` Bryan O'Donoghue
2024-08-21 8:15 ` Vladimir Zapolskiy
1 sibling, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2024-08-20 9:45 UTC (permalink / raw)
To: Richard Acayan, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-i2c, devicetree, linux-media
On 19/08/2024 23:10, Richard Acayan wrote:
> The camera subsystem for the SDM670 the same as on SDM845 except with
> 3 CSIPHY ports instead of 4. Add support for the SDM670 camera
> subsystem.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> drivers/media/platform/qcom/camss/camss.c | 191 ++++++++++++++++++++++
> 1 file changed, 191 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 51b1d3550421..b2f22bfd8692 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 3/5] media: qcom: camss: add support for SDM670 camss
2024-08-19 22:10 ` [PATCH v3 3/5] media: qcom: camss: add support for SDM670 camss Richard Acayan
2024-08-20 9:45 ` Bryan O'Donoghue
@ 2024-08-21 8:15 ` Vladimir Zapolskiy
1 sibling, 0 replies; 22+ messages in thread
From: Vladimir Zapolskiy @ 2024-08-21 8:15 UTC (permalink / raw)
To: Richard Acayan, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, linux-arm-msm, linux-i2c, devicetree, linux-media
On 8/20/24 01:10, Richard Acayan wrote:
> The camera subsystem for the SDM670 the same as on SDM845 except with
> 3 CSIPHY ports instead of 4. Add support for the SDM670 camera
> subsystem.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 4/5] arm64: dts: qcom: sdm670: add camcc
2024-08-19 22:10 [PATCH v3 0/5] Add SDM670 camera subsystem Richard Acayan
` (2 preceding siblings ...)
2024-08-19 22:10 ` [PATCH v3 3/5] media: qcom: camss: add support for SDM670 camss Richard Acayan
@ 2024-08-19 22:10 ` Richard Acayan
2024-08-20 9:23 ` Vladimir Zapolskiy
2024-08-19 22:10 ` [PATCH v3 5/5] arm64: dts: qcom: sdm670: add camss and cci Richard Acayan
4 siblings, 1 reply; 22+ messages in thread
From: Richard Acayan @ 2024-08-19 22:10 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Richard Acayan, linux-arm-msm, linux-i2c,
devicetree, linux-media
The camera clock controller on SDM670 controls the clocks that drive the
camera subsystem. The clocks are the same as on SDM845. Add the camera
clock controller for SDM670.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 187c6698835d..ba93cef33dbb 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1400,6 +1400,16 @@ spmi_bus: spmi@c440000 {
#interrupt-cells = <4>;
};
+ camcc: clock-controller@ad00000 {
+ compatible = "qcom,sdm845-camcc";
+ reg = <0 0x0ad00000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "bi_tcxo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,sdm670-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.46.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 4/5] arm64: dts: qcom: sdm670: add camcc
2024-08-19 22:10 ` [PATCH v3 4/5] arm64: dts: qcom: sdm670: add camcc Richard Acayan
@ 2024-08-20 9:23 ` Vladimir Zapolskiy
2024-08-20 9:26 ` Konrad Dybcio
0 siblings, 1 reply; 22+ messages in thread
From: Vladimir Zapolskiy @ 2024-08-20 9:23 UTC (permalink / raw)
To: Richard Acayan, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, linux-arm-msm, linux-i2c, devicetree, linux-media
On 8/20/24 01:10, Richard Acayan wrote:
> The camera clock controller on SDM670 controls the clocks that drive the
> camera subsystem. The clocks are the same as on SDM845. Add the camera
> clock controller for SDM670.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sdm670.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> index 187c6698835d..ba93cef33dbb 100644
> --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> @@ -1400,6 +1400,16 @@ spmi_bus: spmi@c440000 {
> #interrupt-cells = <4>;
> };
>
> + camcc: clock-controller@ad00000 {
> + compatible = "qcom,sdm845-camcc";
Here it's wrong, and the compatible property value shall contain
"qcom,sdm670-camcc", probably it could contain both values though.
It may require to add a new compatible to dt documentation and,
if needed, to the corresponding clock driver.
> + reg = <0 0x0ad00000 0 0x10000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "bi_tcxo";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> mdss: display-subsystem@ae00000 {
> compatible = "qcom,sdm670-mdss";
> reg = <0 0x0ae00000 0 0x1000>;
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 4/5] arm64: dts: qcom: sdm670: add camcc
2024-08-20 9:23 ` Vladimir Zapolskiy
@ 2024-08-20 9:26 ` Konrad Dybcio
0 siblings, 0 replies; 22+ messages in thread
From: Konrad Dybcio @ 2024-08-20 9:26 UTC (permalink / raw)
To: Vladimir Zapolskiy, Richard Acayan, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Bryan O'Donoghue, Mauro Carvalho Chehab,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, linux-i2c,
devicetree, linux-media
On 20.08.2024 11:23 AM, Vladimir Zapolskiy wrote:
> On 8/20/24 01:10, Richard Acayan wrote:
>> The camera clock controller on SDM670 controls the clocks that drive the
>> camera subsystem. The clocks are the same as on SDM845. Add the camera
>> clock controller for SDM670.
>>
>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
>> ---
>> arch/arm64/boot/dts/qcom/sdm670.dtsi | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
>> index 187c6698835d..ba93cef33dbb 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
>> @@ -1400,6 +1400,16 @@ spmi_bus: spmi@c440000 {
>> #interrupt-cells = <4>;
>> };
>> + camcc: clock-controller@ad00000 {
>> + compatible = "qcom,sdm845-camcc";
>
> Here it's wrong, and the compatible property value shall contain
> "qcom,sdm670-camcc", probably it could contain both values though.
>
> It may require to add a new compatible to dt documentation and,
> if needed, to the corresponding clock driver.
+1, even if the blocks are physically the same, please add a SoC-specific
compatible (with a fallback to 845 if that's the case) just in case there
are some implementation problems only concerning this instance
Konrad
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 5/5] arm64: dts: qcom: sdm670: add camss and cci
2024-08-19 22:10 [PATCH v3 0/5] Add SDM670 camera subsystem Richard Acayan
` (3 preceding siblings ...)
2024-08-19 22:10 ` [PATCH v3 4/5] arm64: dts: qcom: sdm670: add camcc Richard Acayan
@ 2024-08-19 22:10 ` Richard Acayan
2024-08-20 9:40 ` Bryan O'Donoghue
2024-08-21 10:40 ` Vladimir Zapolskiy
4 siblings, 2 replies; 22+ messages in thread
From: Richard Acayan @ 2024-08-19 22:10 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Richard Acayan, linux-arm-msm, linux-i2c,
devicetree, linux-media
Add the camera subsystem and CCI used to interface with cameras on the
Snapdragon 670.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 188 +++++++++++++++++++++++++++
1 file changed, 188 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index ba93cef33dbb..37bc4fa04286 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -6,6 +6,7 @@
* Copyright (c) 2022, Richard Acayan. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
@@ -1168,6 +1169,34 @@ tlmm: pinctrl@3400000 {
gpio-ranges = <&tlmm 0 0 151>;
wakeup-parent = <&pdc>;
+ cci0_default: cci0-default-state {
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_default: cci1-default-state {
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
qup_i2c0_default: qup-i2c0-default-state {
pins = "gpio0", "gpio1";
function = "qup0";
@@ -1400,6 +1429,165 @@ spmi_bus: spmi@c440000 {
#interrupt-cells = <4>;
};
+ cci: cci@ac4a000 {
+ compatible = "qcom,sdm670-cci", "qcom,msm8996-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0x0ac4a000 0 0x4000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SOC_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_CLK>;
+ clock-names = "camnoc_axi",
+ "soc_ahb",
+ "cpas_ahb",
+ "cci";
+
+ assigned-clocks = <&camcc CAM_CC_CCI_CLK>;
+ assigned-clock-rates = <37500000>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ camss: camera-controller@ac65000 {
+ compatible = "qcom,sdm670-camss";
+ reg = <0 0x0ac65000 0 0x1000>,
+ <0 0x0ac66000 0 0x1000>,
+ <0 0x0ac67000 0 0x1000>,
+ <0 0x0acaf000 0 0x4000>,
+ <0 0x0acb3000 0 0x1000>,
+ <0 0x0acb6000 0 0x4000>,
+ <0 0x0acba000 0 0x1000>,
+ <0 0x0acc4000 0 0x4000>,
+ <0 0x0acc8000 0 0x1000>;
+ reg-names = "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "vfe0",
+ "csid0",
+ "vfe1",
+ "csid1",
+ "vfe_lite",
+ "csid2";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_AXI_CLK>,
+ <&camcc CAM_CC_SOC_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "csi0",
+ "csi1",
+ "csi2",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "gcc_camera_ahb",
+ "gcc_camera_axi",
+ "soc_ahb",
+ "vfe0_axi",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe1_axi",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "vfe_lite",
+ "vfe_lite_cphy_rx";
+
+ iommus = <&apps_smmu 0x808 0x0>,
+ <&apps_smmu 0x810 0x8>,
+ <&apps_smmu 0xc08 0x0>,
+ <&apps_smmu 0xc10 0x8>;
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camss_port0: port@0 {
+ reg = <0>;
+ };
+
+ camss_port1: port@1 {
+ reg = <1>;
+ };
+
+ camss_port2: port@2 {
+ reg = <2>;
+ };
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sdm845-camcc";
reg = <0 0x0ad00000 0 0x10000>;
--
2.46.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 5/5] arm64: dts: qcom: sdm670: add camss and cci
2024-08-19 22:10 ` [PATCH v3 5/5] arm64: dts: qcom: sdm670: add camss and cci Richard Acayan
@ 2024-08-20 9:40 ` Bryan O'Donoghue
2024-08-21 10:40 ` Vladimir Zapolskiy
1 sibling, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2024-08-20 9:40 UTC (permalink / raw)
To: Richard Acayan, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-i2c, devicetree, linux-media
On 19/08/2024 23:10, Richard Acayan wrote:
> Add the camera subsystem and CCI used to interface with cameras on the
> Snapdragon 670.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sdm670.dtsi | 188 +++++++++++++++++++++++++++
> 1 file changed, 188 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> index ba93cef33dbb..37bc4fa04286 100644
> --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
This looks neater - better indentation for example than what we have for
845 upstream.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 5/5] arm64: dts: qcom: sdm670: add camss and cci
2024-08-19 22:10 ` [PATCH v3 5/5] arm64: dts: qcom: sdm670: add camss and cci Richard Acayan
2024-08-20 9:40 ` Bryan O'Donoghue
@ 2024-08-21 10:40 ` Vladimir Zapolskiy
2024-08-23 23:44 ` Richard Acayan
1 sibling, 1 reply; 22+ messages in thread
From: Vladimir Zapolskiy @ 2024-08-21 10:40 UTC (permalink / raw)
To: Richard Acayan, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, linux-arm-msm, linux-i2c, devicetree, linux-media
On 8/20/24 01:10, Richard Acayan wrote:
> Add the camera subsystem and CCI used to interface with cameras on the
> Snapdragon 670.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sdm670.dtsi | 188 +++++++++++++++++++++++++++
> 1 file changed, 188 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> index ba93cef33dbb..37bc4fa04286 100644
> --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> @@ -6,6 +6,7 @@
> * Copyright (c) 2022, Richard Acayan. All rights reserved.
> */
>
> +#include <dt-bindings/clock/qcom,camcc-sdm845.h>
> #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> @@ -1168,6 +1169,34 @@ tlmm: pinctrl@3400000 {
> gpio-ranges = <&tlmm 0 0 151>;
> wakeup-parent = <&pdc>;
>
> + cci0_default: cci0-default-state {
> + pins = "gpio17", "gpio18";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + cci0_sleep: cci0-sleep-state {
> + pins = "gpio17", "gpio18";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci1_default: cci1-default-state {
> + pins = "gpio19", "gpio20";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + cci1_sleep: cci1-sleep-state {
> + pins = "gpio19", "gpio20";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> qup_i2c0_default: qup-i2c0-default-state {
> pins = "gpio0", "gpio1";
> function = "qup0";
> @@ -1400,6 +1429,165 @@ spmi_bus: spmi@c440000 {
> #interrupt-cells = <4>;
> };
>
> + cci: cci@ac4a000 {
> + compatible = "qcom,sdm670-cci", "qcom,msm8996-cci";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <0 0x0ac4a000 0 0x4000>;
> + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc TITAN_TOP_GDSC>;
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_SOC_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_CLK>;
> + clock-names = "camnoc_axi",
> + "soc_ahb",
> + "cpas_ahb",
> + "cci";
> +
> + assigned-clocks = <&camcc CAM_CC_CCI_CLK>;
> + assigned-clock-rates = <37500000>;
Please remove assigned-clocks and assigned-clock-rates properties.
> +
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&cci0_default &cci1_default>;
> + pinctrl-1 = <&cci0_sleep &cci1_sleep>;
> +
> + status = "disabled";
> +
> + cci_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + camss: camera-controller@ac65000 {
> + compatible = "qcom,sdm670-camss";
> + reg = <0 0x0ac65000 0 0x1000>,
> + <0 0x0ac66000 0 0x1000>,
> + <0 0x0ac67000 0 0x1000>,
> + <0 0x0acaf000 0 0x4000>,
> + <0 0x0acb3000 0 0x1000>,
> + <0 0x0acb6000 0 0x4000>,
> + <0 0x0acba000 0 0x1000>,
> + <0 0x0acc4000 0 0x4000>,
> + <0 0x0acc8000 0 0x1000>;
> + reg-names = "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "vfe0",
> + "csid0",
> + "vfe1",
> + "csid1",
> + "vfe_lite",
> + "csid2";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "vfe0",
> + "vfe1",
> + "vfe_lite";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_IFE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_1_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMERA_AXI_CLK>,
> + <&camcc CAM_CC_SOC_AHB_CLK>,
Please put two &gcc and "soc_ahb" clock sources on top, it will
require a change in dt bindings documentation also.
> + <&camcc CAM_CC_IFE_0_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_1_AXI_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "csi0",
> + "csi1",
> + "csi2",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "gcc_camera_ahb",
> + "gcc_camera_axi",
> + "soc_ahb",
> + "vfe0_axi",
> + "vfe0",
> + "vfe0_cphy_rx",
> + "vfe1_axi",
> + "vfe1",
> + "vfe1_cphy_rx",
> + "vfe_lite",
> + "vfe_lite_cphy_rx";
> +
> + iommus = <&apps_smmu 0x808 0x0>,
> + <&apps_smmu 0x810 0x8>,
> + <&apps_smmu 0xc08 0x0>,
> + <&apps_smmu 0xc10 0x8>;
> +
> + power-domains = <&camcc IFE_0_GDSC>,
> + <&camcc IFE_1_GDSC>,
> + <&camcc TITAN_TOP_GDSC>;
> + power-domain-names = "ife0",
> + "ife1",
> + "top";
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + camss_port0: port@0 {
> + reg = <0>;
> + };
> +
> + camss_port1: port@1 {
> + reg = <1>;
> + };
> +
> + camss_port2: port@2 {
> + reg = <2>;
> + };
> + };
> + };
> +
> camcc: clock-controller@ad00000 {
> compatible = "qcom,sdm845-camcc";
> reg = <0 0x0ad00000 0 0x10000>;
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 5/5] arm64: dts: qcom: sdm670: add camss and cci
2024-08-21 10:40 ` Vladimir Zapolskiy
@ 2024-08-23 23:44 ` Richard Acayan
2024-08-24 11:56 ` Bryan O'Donoghue
2024-08-24 11:59 ` [PATCH] i2c: qcom-cci: Stop complaining about DT set clock rate Bryan O'Donoghue
0 siblings, 2 replies; 22+ messages in thread
From: Richard Acayan @ 2024-08-23 23:44 UTC (permalink / raw)
To: Vladimir Zapolskiy
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, linux-arm-msm, linux-i2c, devicetree, linux-media
On Wed, Aug 21, 2024 at 01:40:14PM +0300, Vladimir Zapolskiy wrote:
> On 8/20/24 01:10, Richard Acayan wrote:
> > Add the camera subsystem and CCI used to interface with cameras on the
> > Snapdragon 670.
> >
> > Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> > ---
> > arch/arm64/boot/dts/qcom/sdm670.dtsi | 188 +++++++++++++++++++++++++++
> > 1 file changed, 188 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> > index ba93cef33dbb..37bc4fa04286 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> > @@ -6,6 +6,7 @@
> > * Copyright (c) 2022, Richard Acayan. All rights reserved.
> > */
> > +#include <dt-bindings/clock/qcom,camcc-sdm845.h>
> > #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> > #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> > #include <dt-bindings/clock/qcom,rpmh.h>
> > @@ -1168,6 +1169,34 @@ tlmm: pinctrl@3400000 {
> > gpio-ranges = <&tlmm 0 0 151>;
> > wakeup-parent = <&pdc>;
> > + cci0_default: cci0-default-state {
> > + pins = "gpio17", "gpio18";
> > + function = "cci_i2c";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + cci0_sleep: cci0-sleep-state {
> > + pins = "gpio17", "gpio18";
> > + function = "cci_i2c";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > + cci1_default: cci1-default-state {
> > + pins = "gpio19", "gpio20";
> > + function = "cci_i2c";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + cci1_sleep: cci1-sleep-state {
> > + pins = "gpio19", "gpio20";
> > + function = "cci_i2c";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > qup_i2c0_default: qup-i2c0-default-state {
> > pins = "gpio0", "gpio1";
> > function = "qup0";
> > @@ -1400,6 +1429,165 @@ spmi_bus: spmi@c440000 {
> > #interrupt-cells = <4>;
> > };
> > + cci: cci@ac4a000 {
> > + compatible = "qcom,sdm670-cci", "qcom,msm8996-cci";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + reg = <0 0x0ac4a000 0 0x4000>;
> > + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
> > + power-domains = <&camcc TITAN_TOP_GDSC>;
> > +
> > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> > + <&camcc CAM_CC_SOC_AHB_CLK>,
> > + <&camcc CAM_CC_CPAS_AHB_CLK>,
> > + <&camcc CAM_CC_CCI_CLK>;
> > + clock-names = "camnoc_axi",
> > + "soc_ahb",
> > + "cpas_ahb",
> > + "cci";
> > +
> > + assigned-clocks = <&camcc CAM_CC_CCI_CLK>;
> > + assigned-clock-rates = <37500000>;
>
> Please remove assigned-clocks and assigned-clock-rates properties.
Doing this adds a warning to dmesg, where the clock rate is set to 19.2
MHz by default.
> > +
> > + pinctrl-names = "default", "sleep";
> > + pinctrl-0 = <&cci0_default &cci1_default>;
> > + pinctrl-1 = <&cci0_sleep &cci1_sleep>;
> > +
> > + status = "disabled";
> > +
> > + cci_i2c0: i2c-bus@0 {
> > + reg = <0>;
> > + clock-frequency = <1000000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + cci_i2c1: i2c-bus@1 {
> > + reg = <1>;
> > + clock-frequency = <1000000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > +
> > + camss: camera-controller@ac65000 {
> > + compatible = "qcom,sdm670-camss";
> > + reg = <0 0x0ac65000 0 0x1000>,
> > + <0 0x0ac66000 0 0x1000>,
> > + <0 0x0ac67000 0 0x1000>,
> > + <0 0x0acaf000 0 0x4000>,
> > + <0 0x0acb3000 0 0x1000>,
> > + <0 0x0acb6000 0 0x4000>,
> > + <0 0x0acba000 0 0x1000>,
> > + <0 0x0acc4000 0 0x4000>,
> > + <0 0x0acc8000 0 0x1000>;
> > + reg-names = "csiphy0",
> > + "csiphy1",
> > + "csiphy2",
> > + "vfe0",
> > + "csid0",
> > + "vfe1",
> > + "csid1",
> > + "vfe_lite",
> > + "csid2";
> > +
> > + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "csid0",
> > + "csid1",
> > + "csid2",
> > + "csiphy0",
> > + "csiphy1",
> > + "csiphy2",
> > + "vfe0",
> > + "vfe1",
> > + "vfe_lite";
> > +
> > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> > + <&camcc CAM_CC_CPAS_AHB_CLK>,
> > + <&camcc CAM_CC_IFE_0_CSID_CLK>,
> > + <&camcc CAM_CC_IFE_1_CSID_CLK>,
> > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
> > + <&camcc CAM_CC_CSIPHY0_CLK>,
> > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> > + <&camcc CAM_CC_CSIPHY1_CLK>,
> > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> > + <&camcc CAM_CC_CSIPHY2_CLK>,
> > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> > + <&gcc GCC_CAMERA_AHB_CLK>,
> > + <&gcc GCC_CAMERA_AXI_CLK>,
> > + <&camcc CAM_CC_SOC_AHB_CLK>,
>
> Please put two &gcc and "soc_ahb" clock sources on top, it will
> require a change in dt bindings documentation also.
I'll do this for the clocks themselves because they have no parents (so
no obvious clock sources).
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 5/5] arm64: dts: qcom: sdm670: add camss and cci
2024-08-23 23:44 ` Richard Acayan
@ 2024-08-24 11:56 ` Bryan O'Donoghue
2024-08-24 11:59 ` [PATCH] i2c: qcom-cci: Stop complaining about DT set clock rate Bryan O'Donoghue
1 sibling, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2024-08-24 11:56 UTC (permalink / raw)
To: Richard Acayan, Vladimir Zapolskiy
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-i2c, devicetree, linux-media
On 24/08/2024 00:44, Richard Acayan wrote:
>>> +
>>> + assigned-clocks = <&camcc CAM_CC_CCI_CLK>;
>>> + assigned-clock-rates = <37500000>;
>> Please remove assigned-clocks and assigned-clock-rates properties.
> Doing this adds a warning to dmesg, where the clock rate is set to 19.2
> MHz by default.
I have a patch for this.
Feel free to take into your series and then update the dts here.
---
bod
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH] i2c: qcom-cci: Stop complaining about DT set clock rate
2024-08-23 23:44 ` Richard Acayan
2024-08-24 11:56 ` Bryan O'Donoghue
@ 2024-08-24 11:59 ` Bryan O'Donoghue
2024-08-24 12:39 ` Vladimir Zapolskiy
1 sibling, 1 reply; 22+ messages in thread
From: Bryan O'Donoghue @ 2024-08-24 11:59 UTC (permalink / raw)
To: mailingradian, vladimir.zapolskiy, loic.poulain, rfoss
Cc: andi.shyti, robh, krzk+dt, conor+dt, todor.too, mchehab,
andersson, konradybcio, linux-arm-msm, linux-i2c, devicetree,
linux-media, Bryan O'Donoghue
It is common practice in the downstream and upstream CCI dt to set CCI
clock rates to 19.2 MHz. It appears to be fairly common for initial code to
set the CCI clock rate to 37.5 MHz.
Applying the widely used CCI clock rates from downstream ought not to cause
warning messages in the upstream kernel where our general policy is to
usually copy downstream hardware clock rates across the range of Qualcomm
drivers.
Drop the warning it is pervasive across CAMSS users but doesn't add any
information or warrant any changes to the DT to align the DT clock rate to
the bootloader clock rate.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/i2c/busses/i2c-qcom-cci.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c
index 414882c57d7f4..99e4305a33733 100644
--- a/drivers/i2c/busses/i2c-qcom-cci.c
+++ b/drivers/i2c/busses/i2c-qcom-cci.c
@@ -602,14 +602,6 @@ static int cci_probe(struct platform_device *pdev)
}
}
- if (cci_clk_rate != cci->data->cci_clk_rate) {
- /* cci clock set by the bootloader or via assigned clock rate
- * in DT.
- */
- dev_warn(dev, "Found %lu cci clk rate while %lu was expected\n",
- cci_clk_rate, cci->data->cci_clk_rate);
- }
-
ret = cci_enable_clocks(cci);
if (ret < 0)
return ret;
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH] i2c: qcom-cci: Stop complaining about DT set clock rate
2024-08-24 11:59 ` [PATCH] i2c: qcom-cci: Stop complaining about DT set clock rate Bryan O'Donoghue
@ 2024-08-24 12:39 ` Vladimir Zapolskiy
0 siblings, 0 replies; 22+ messages in thread
From: Vladimir Zapolskiy @ 2024-08-24 12:39 UTC (permalink / raw)
To: Bryan O'Donoghue, mailingradian, loic.poulain, rfoss
Cc: andi.shyti, robh, krzk+dt, conor+dt, todor.too, mchehab,
andersson, konradybcio, linux-arm-msm, linux-i2c, devicetree,
linux-media
On 8/24/24 14:59, Bryan O'Donoghue wrote:
> It is common practice in the downstream and upstream CCI dt to set CCI
> clock rates to 19.2 MHz. It appears to be fairly common for initial code to
> set the CCI clock rate to 37.5 MHz.
>
> Applying the widely used CCI clock rates from downstream ought not to cause
> warning messages in the upstream kernel where our general policy is to
> usually copy downstream hardware clock rates across the range of Qualcomm
> drivers.
>
> Drop the warning it is pervasive across CAMSS users but doesn't add any
> information or warrant any changes to the DT to align the DT clock rate to
> the bootloader clock rate.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 22+ messages in thread