From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5495B1311AC; Mon, 16 Jun 2025 06:15:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750054517; cv=none; b=L6C8NLgB2M8OPG1pIm+04TfH3P2tFsVoOmHwpUkZ81rC3r7bpIUv7NarRaXRY9QuaVa0J/52DHUsZXfH9ap2srDgXlJzSTG5AGbnpPKdzSsFkmRn3NCf6r/qEYeZs/LGP3ep1RyQ8SDQw9Qwy6Vvv35laO44BGvNLlcAlVEuq18= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750054517; c=relaxed/simple; bh=TA8S3CxxR962TjxUcIfFBwyF2MLXElpNJFCjY8feYi8=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=O18b5b/0Imra/+7WCJrfBPk4/vkFOMETEnBpUQXsV05e5TLZiOD1F2ua78EmJND9Vy0SLg9xI88UjHpkWB6vGN3rqOraprwZ8jNsAxL2MUxklzMUK7sC9iSVQ+SCqLzKK0XlgMZfzwbg/zHSg7MjGpUnmgZvtcZjZNjGahVWN94= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QT9UkGPh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QT9UkGPh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1883BC4CEEA; Mon, 16 Jun 2025 06:15:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750054516; bh=TA8S3CxxR962TjxUcIfFBwyF2MLXElpNJFCjY8feYi8=; h=Date:Subject:To:References:From:In-Reply-To:From; b=QT9UkGPhAf95tGrD8BkqGk/F7ZREw4AiEVFwfKly5D0jG/N/qVEZ4tpy4Ji8SOEB7 m7NffmQL6bxk+4YqZdtOjN2EYEQWpvVGNq2wI1RTGaoFM+bGKQSsel7FTjV7FGJ0a/ IfBhbuyBnyUW/iP4AENTUWL7FwIy5+XZ0p0z1qym1iCY8BcA2RXcVE+2GufBR8uB2H bzzVRlEInT5ajVVDXrm1vd+QJOYK5tMt54XRn6njItU7Y3LlDY85UyPOMMzVVHqjZL ka0eBwysrJLaDORW1bBpqa4mydLSyet3YkRWT5S8/SHYTeWQltYP0IpzcOEZDV3oNm VE8VT/20O1Taw== Message-ID: Date: Mon, 16 Jun 2025 08:15:08 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree To: Ryan Chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , "nfraprado@collabora.com" , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "soc@lists.linux.dev" , Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , "wthai@nvidia.com" , "leohu@nvidia.com" , "dkodihalli@nvidia.com" , "spuranik@nvidia.com" References: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> <20250612100933.3007673-4-ryan_chen@aspeedtech.com> <485749d4-b3c4-4965-9714-ad534d37e8c9@kernel.org> <749c581e-cc00-428f-8eb9-222f9d574486@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 16/06/2025 04:24, Ryan Chen wrote: >> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device >> tree >> >> On 13/06/2025 04:29, Ryan Chen wrote: >>>> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 >>>> SoC device tree >>>> >>>> On 12/06/2025 12:09, Ryan Chen wrote: >>>>> This add the initial device tree support for the ASPEED AST2700 SoC. >>>>> >>>>> - Add top-level compatible string "aspeed,ast2700" and set up >>>>> address-cells/size-cells for 64-bit address space. >>>>> - Describe a quad-core ARM Cortex-A35 CPU cluster with L2 cache, >>>>> including cache properties and PSCI enable-method. >>>>> - Add PMU and ARMv8 timer nodes with correct PPI interrupt wiring. >>>>> - Model the dual-SoC architecture with two simple-bus nodes: >>>>> soc0 (@0x10000000) and soc1 (@0x14000000). >>>>> - Add syscon nodes for both SoCs (syscon0, syscon1) with clock/reset >>>>> cell definitions and address mapping. >>>>> - Add GICv3 interrupt controller node under soc0, with full register >>>>> mapping and interrupt properties. >>>>> - Hierarchical interrupt controller structure: >>>>> - intc0 under soc0, with child intc0_11 node. >>>>> - intc1 under soc1, with child intc1_0~intc1_5 nodes. >>>>> - Add serial4 node under soc0, others serial node under soc1. >>>>> >>>>> Signed-off-by: Ryan Chen >>>>> --- >>>>> arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 380 >>>>> ++++++++++++++++++++++ >>>>> 1 file changed, 380 insertions(+) >>>>> create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi >>>>> >>>>> diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi >>>>> b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi >>>>> new file mode 100644 >>>>> index 000000000000..d197187bcf9f >>>>> --- /dev/null >>>>> +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi >>>>> @@ -0,0 +1,380 @@ >>>>> +// SPDX-License-Identifier: GPL-2.0-or-later #include >>>>> + >>>>> +#include >>>>> +#include >>>>> + >>>>> +/ { >>>>> + #address-cells = <2>; >>>>> + #size-cells = <1>; >>>>> + interrupt-parent = <&gic>; >>>>> + >>>>> + cpus { >>>>> + #address-cells = <2>; >>>>> + #size-cells = <0>; >>>>> + >>>>> + cpu0: cpu@0 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,cortex-a35"; >>>>> + reg = <0x0 0x0>; >>>>> + enable-method = "psci"; >>>>> + i-cache-size = <0x8000>; >>>>> + i-cache-line-size = <64>; >>>>> + i-cache-sets = <256>; >>>>> + d-cache-size = <0x8000>; >>>>> + d-cache-line-size = <64>; >>>>> + d-cache-sets = <128>; >>>>> + next-level-cache = <&l2>; >>>>> + }; >>>>> + >>>>> + cpu1: cpu@1 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,cortex-a35"; >>>>> + enable-method = "psci"; >>>>> + reg = <0x0 0x1>; >>>>> + i-cache-size = <0x8000>; >>>>> + i-cache-line-size = <64>; >>>>> + i-cache-sets = <256>; >>>>> + d-cache-size = <0x8000>; >>>>> + d-cache-line-size = <64>; >>>>> + d-cache-sets = <128>; >>>>> + next-level-cache = <&l2>; >>>>> + }; >>>>> + >>>>> + cpu2: cpu@2 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,cortex-a35"; >>>>> + enable-method = "psci"; >>>>> + reg = <0x0 0x2>; >>>>> + i-cache-size = <0x8000>; >>>>> + i-cache-line-size = <64>; >>>>> + i-cache-sets = <256>; >>>>> + d-cache-size = <0x8000>; >>>>> + d-cache-line-size = <64>; >>>>> + d-cache-sets = <128>; >>>>> + next-level-cache = <&l2>; >>>>> + }; >>>>> + >>>>> + cpu3: cpu@3 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,cortex-a35"; >>>>> + enable-method = "psci"; >>>>> + reg = <0x0 0x3>; >>>>> + i-cache-size = <0x8000>; >>>>> + i-cache-line-size = <64>; >>>>> + i-cache-sets = <256>; >>>>> + d-cache-size = <0x8000>; >>>>> + d-cache-line-size = <64>; >>>>> + d-cache-sets = <128>; >>>>> + next-level-cache = <&l2>; >>>>> + }; >>>>> + >>>>> + l2: l2-cache0 { >>>>> + compatible = "cache"; >>>>> + cache-level = <2>; >>>>> + cache-unified; >>>>> + cache-size = <0x80000>; >>>>> + cache-line-size = <64>; >>>>> + cache-sets = <1024>; >>>>> + }; >>>>> + }; >>>>> + >>>>> + arm-pmu { >>>>> + compatible = "arm,cortex-a35-pmu"; >>>>> + interrupts = >>> IRQ_TYPE_LEVEL_HIGH)>; >>>>> + }; >>>>> + >>>>> + psci { >>>>> + compatible = "arm,psci-1.0"; >>>>> + method = "smc"; >>>>> + }; >>>>> + >>>>> + timer { >>>>> + compatible = "arm,armv8-timer"; >>>>> + interrupts = >>> IRQ_TYPE_LEVEL_LOW)>, >>>>> + >>> IRQ_TYPE_LEVEL_LOW)>, >>>>> + >>> IRQ_TYPE_LEVEL_LOW)>, >>>>> + >>> IRQ_TYPE_LEVEL_LOW)>; >>>>> + arm,cpu-registers-not-fw-configured; >>>>> + always-on; >>>>> + }; >>>>> + >>>>> + soc0: soc@10000000 { >>>>> + compatible = "simple-bus"; >>>>> + reg = <0x0 0x10000000 0x10000000>; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <1>; >>>>> + ranges; >>>>> + >>>>> + syscon0: syscon@12c02000 { >>>>> + compatible = "aspeed,ast2700-scu0", "syscon", >> "simple-mfd"; >>>>> + reg = <0x0 0x12c02000 0x1000>; >>>>> + ranges = <0x0 0x0 0 0x12c02000 0x1000>; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <1>; >>>>> + #clock-cells = <1>; >>>>> + #reset-cells = <1>; >>>>> + }; >>>>> + >>>>> + gic: interrupt-controller@12200000 { >>>>> + compatible = "arm,gic-v3"; >>>>> + reg = <0 0x12200000 0x10000>, /* GICD */ >>>>> + <0 0x12280000 0x80000>, /* GICR */ >>>>> + <0 0x40440000 0x1000>; /* GICC */ >>>>> + #interrupt-cells = <3>; >>>>> + interrupt-controller; >>>>> + interrupts = >>> IRQ_TYPE_LEVEL_HIGH)>; >>>>> + interrupt-parent = <&gic>; >>>>> + }; >>>>> + >>>>> + serial4: serial@12c1a000 { >>>>> + compatible = "ns16550a"; >>>>> + reg = <0x0 0x12c1a000 0x1000>; >>>>> + clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>; >>>>> + interrupts = ; >>>>> + reg-shift = <2>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + }; >>>>> + >>>>> + soc1: soc@14000000 { >>>>> + compatible = "simple-bus"; >>>>> + reg = <0x0 0x14000000 0x10000000>; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <1>; >>>>> + ranges; >>>>> + >>>>> + syscon1: syscon@14c02000 { >>>>> + compatible = "aspeed,ast2700-scu1", "syscon", >> "simple-mfd"; >>>>> + reg = <0x0 0x14c02000 0x1000>; >>>>> + ranges = <0x0 0x0 0x0 0x14c02000 0x1000>; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <1>; >>>>> + #clock-cells = <1>; >>>>> + #reset-cells = <1>; >>>>> + }; >>>>> + >>>>> + serial12: serial@14c33b00 { >>>>> + compatible = "ns16550a"; >>>>> + reg = <0x0 0x14c33b00 0x100>; >>>>> + clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>; >>>>> + interrupts-extended = >>>>> + <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | >>>> IRQ_TYPE_LEVEL_HIGH)>; >>>>> + reg-shift = <2>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + }; >>>>> +}; >>>>> + >>>>> +&soc0 { >>>> >>>> This is the base DTSI, there is no existing node to override. Just >>>> define complete SoC node in one place like every other vendor. >>> >>> My original is use this way, but when I do checkpatch, get >>> CHECK: line length of 106 exceeds 100 columns. >>> interrupts = >> IRQ_TYPE_LEVEL_HIGH)>, That the reason modify by this way. >> >> Look how other recent, most developed platforms do it and learn from them >> instead of coming with own, confusing style. > > Thanks, I will refer this to modify. > https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/broadcom/bcm2712.dtsi#L580-L589 >> >>> >>>> >>>> >>>>> + intc0: interrupt-controller@12100000 { >>>>> + compatible = "simple-mfd"; >>>> >>>> NAK, never tested. >>>> >>>> Not allowed, see bindings. And test it next time. >>> >>> Got it, will update by following. >>> Intc0: bus@12100000 { >>> compatible = "simple-bus"; >>> #address-cells = <2>; >>> #size-cells = <1>; >>> reg = <0 0x12100000 0x4000>; >>> ranges = <0x0 0x0 0x0 0x12100000 0x4000>; >>> #address-cells = <2>; >> >> Does not follow DTS coding style and anyway, what sort of bus is this? > > Sorry, for miss-lead. intc0 is like the global base for inte0_11 interrupt-controller. So that's not a bus, thus do not use simple-bus for that. Define bindings for your device. > So, I use simple-mfd. > intc0: interrupt-controller@12100000 { > compatible = "simple-mfd"; > ..... > intc0_11: interrupt-controller@1b00 { > ...... > }; > }; > > But I don't know your previous "NAK, never tested" mean. > I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the fail with > intc0: interrupt-controller@12100000 { > compatible = "simple-mfd"; > > So, could you point me more test instruction for this? See syscon.yaml. And writing bindings or talks on conferences: simple-mfd cannot be alone. Best regards, Krzysztof