[PATCH v6 0/2] arm64: dts: qcom: ipq6018: add sdhci node

[PATCH v6 0/2] arm64: dts: qcom: ipq6018: add sdhci node

[Chukun Pan]

It is difficult to add OPP table for sdhci node due to lack of
datasheet and other data. Limit the maximum clock frequency of
sdcc to avoid overclocking SD/eMMC cards.

Changes in v6:
  Adjust the maximum clock frequency of sdcc to 200 MHz.

Changes in v5:
  Move LDOA2 regulator patch to other series.

Changes in v4:
  Change 'enable' to 'add' of the commit title.

Changes in v3:
  Remove always-on for LDOA2 regulator.
  Remove 1.8v properties of the node added in dtsi.

Changes in v2:
  Add LDOA2 regulator to support SDCC voltage scaling.

Chukun Pan (2):
  clk: qcom: gcc-ipq6018: update sdcc max clock frequency
  arm64: dts: qcom: ipq6018: add sdhci node

 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++
 drivers/clk/qcom/gcc-ipq6018.c        |  2 +-
 2 files changed, 20 insertions(+), 1 deletion(-)

-- 
2.25.1

[PATCH v6 1/2] clk: qcom: gcc-ipq6018: update sdcc max clock frequency

[Chukun Pan]

The mmc controller of the IPQ6018 does not support HS400 mode.
So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
 drivers/clk/qcom/gcc-ipq6018.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index 7e69de34c310..6c764e3e2665 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
 	F(96000000, P_GPLL2, 12, 0, 0),
 	F(177777778, P_GPLL0, 4.5, 0, 0),
 	F(192000000, P_GPLL2, 6, 0, 0),
-	F(384000000, P_GPLL2, 3, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
 	{ }
 };
 
-- 
2.25.1

[PATCH v6 2/2] arm64: dts: qcom: ipq6018: add sdhci node

[Chukun Pan]

Add node to support mmc controller inside of IPQ6018.
This controller supports both eMMC and SD cards.

Tested with:
  eMMC (HS200)
  SD Card (SDR50/SDR104)

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 9694140881c6..b3b98f050cfd 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -457,6 +457,25 @@ dwc_1: usb@7000000 {
 			};
 		};
 
+		sdhc: mmc@7804000 {
+			compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x0 0x07804000 0x0 0x1000>,
+			      <0x0 0x07805000 0x0 0x1000>;
+			reg-names = "hc", "cqhci";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&xo>;
+			clock-names = "iface", "core", "xo";
+			resets = <&gcc GCC_SDCC1_BCR>;
+			max-frequency = <192000000>;
+			status = "disabled";
+		};
+
 		blsp_dma: dma-controller@7884000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x0 0x07884000 0x0 0x2b000>;
-- 
2.25.1

Re: [PATCH v6 1/2] clk: qcom: gcc-ipq6018: update sdcc max clock frequency

[Dmitry Baryshkov]

On Thu, Jun 20, 2024 at 11:01:21PM GMT, Chukun Pan wrote:
> The mmc controller of the IPQ6018 does not support HS400 mode.
> So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).
> 
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>

Fixes?

> ---
>  drivers/clk/qcom/gcc-ipq6018.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> index 7e69de34c310..6c764e3e2665 100644
> --- a/drivers/clk/qcom/gcc-ipq6018.c
> +++ b/drivers/clk/qcom/gcc-ipq6018.c
> @@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
>  	F(96000000, P_GPLL2, 12, 0, 0),
>  	F(177777778, P_GPLL0, 4.5, 0, 0),
>  	F(192000000, P_GPLL2, 6, 0, 0),
> -	F(384000000, P_GPLL2, 3, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),
>  	{ }
>  };
>  
> -- 
> 2.25.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH v6 1/2] clk: qcom: gcc-ipq6018: update sdcc max clock frequency

[Robert Marko]

On 20. 06. 2024. 17:01, Chukun Pan wrote:
> The mmc controller of the IPQ6018 does not support HS400 mode.
> So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).
>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
>   drivers/clk/qcom/gcc-ipq6018.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> index 7e69de34c310..6c764e3e2665 100644
> --- a/drivers/clk/qcom/gcc-ipq6018.c
> +++ b/drivers/clk/qcom/gcc-ipq6018.c
> @@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
>   	F(96000000, P_GPLL2, 12, 0, 0),
>   	F(177777778, P_GPLL0, 4.5, 0, 0),
>   	F(192000000, P_GPLL2, 6, 0, 0),
> -	F(384000000, P_GPLL2, 3, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),

Hi,
Are you sure that 200MHz is even valid of a frequency, cause all IPQ SoC-s
use 192MHz for the HS200 mode instead.

I would just drop the 384MHz frequency as datasheet clearly states that 
HS400
is not supported.

Regards,
Robert

>   	{ }
>   };
>   

Re: [PATCH v6 1/2] clk: qcom: gcc-ipq6018: update sdcc max clock frequency

[Bjorn Andersson]

On Sat, Jun 22, 2024 at 04:36:20PM GMT, Robert Marko wrote:
> 
> On 20. 06. 2024. 17:01, Chukun Pan wrote:
> > The mmc controller of the IPQ6018 does not support HS400 mode.
> > So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).
> > 
> > Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> > ---
> >   drivers/clk/qcom/gcc-ipq6018.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> > index 7e69de34c310..6c764e3e2665 100644
> > --- a/drivers/clk/qcom/gcc-ipq6018.c
> > +++ b/drivers/clk/qcom/gcc-ipq6018.c
> > @@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
> >   	F(96000000, P_GPLL2, 12, 0, 0),
> >   	F(177777778, P_GPLL0, 4.5, 0, 0),
> >   	F(192000000, P_GPLL2, 6, 0, 0),
> > -	F(384000000, P_GPLL2, 3, 0, 0),
> > +	F(200000000, P_GPLL0, 4, 0, 0),
> 
> Hi,
> Are you sure that 200MHz is even valid of a frequency, cause all IPQ SoC-s
> use 192MHz for the HS200 mode instead.
> 

If I'm parsing the docs correctly, 192MHz, 200MHz and 384MHz are a valid
frequencies for the clock output, but the SDCC expects to receive 200MHz.

> I would just drop the 384MHz frequency as datasheet clearly states that
> HS400
> is not supported.
> 

I'll pick this patch as suggested. Please don't hesitate to send a
follow up patch according to this suggestion if it turns out to be a
better choice.

Regards,
Bjorn

> Regards,
> Robert
> 
> >   	{ }
> >   };

Re: (subset) [PATCH v6 0/2] arm64: dts: qcom: ipq6018: add sdhci node

[Bjorn Andersson]

On Thu, 20 Jun 2024 23:01:20 +0800, Chukun Pan wrote:
> It is difficult to add OPP table for sdhci node due to lack of
> datasheet and other data. Limit the maximum clock frequency of
> sdcc to avoid overclocking SD/eMMC cards.
> 
> Changes in v6:
>   Adjust the maximum clock frequency of sdcc to 200 MHz.
> 
> [...]

Applied, thanks!

[2/2] arm64: dts: qcom: ipq6018: add sdhci node
      commit: 5db216f6e1f85394e79dca74ceceb83b2f8566b5

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH v6 1/2] clk: qcom: gcc-ipq6018: update sdcc max clock frequency

[Robert Marko]

On Wed, 26 Jun 2024 at 06:03, Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Sat, Jun 22, 2024 at 04:36:20PM GMT, Robert Marko wrote:
> >
> > On 20. 06. 2024. 17:01, Chukun Pan wrote:
> > > The mmc controller of the IPQ6018 does not support HS400 mode.
> > > So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).
> > >
> > > Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> > > ---
> > >   drivers/clk/qcom/gcc-ipq6018.c | 2 +-
> > >   1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> > > index 7e69de34c310..6c764e3e2665 100644
> > > --- a/drivers/clk/qcom/gcc-ipq6018.c
> > > +++ b/drivers/clk/qcom/gcc-ipq6018.c
> > > @@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
> > >     F(96000000, P_GPLL2, 12, 0, 0),
> > >     F(177777778, P_GPLL0, 4.5, 0, 0),
> > >     F(192000000, P_GPLL2, 6, 0, 0),
> > > -   F(384000000, P_GPLL2, 3, 0, 0),
> > > +   F(200000000, P_GPLL0, 4, 0, 0),
> >
> > Hi,
> > Are you sure that 200MHz is even valid of a frequency, cause all IPQ SoC-s
> > use 192MHz for the HS200 mode instead.
> >
>
> If I'm parsing the docs correctly, 192MHz, 200MHz and 384MHz are a valid
> frequencies for the clock output, but the SDCC expects to receive 200MHz.
>
> > I would just drop the 384MHz frequency as datasheet clearly states that
> > HS400
> > is not supported.
> >
>
> I'll pick this patch as suggested. Please don't hesitate to send a
> follow up patch according to this suggestion if it turns out to be a
> better choice.

Since you have datasheet and 200MHz is a valid option that is fine
by me.

Regards,
Robert
>
> Regards,
> Bjorn
>
> > Regards,
> > Robert
> >
> > >     { }
> > >   };