* [PATCH v3 1/3] dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
2025-07-05 7:39 [PATCH v3 0/3] Add Sophgo EVB V1/V2 Board support Han Gao
@ 2025-07-05 7:39 ` Han Gao
2025-07-08 0:31 ` Chen Wang
2025-07-08 3:20 ` Nutty Liu
2025-07-05 7:39 ` [PATCH v3 2/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree Han Gao
` (2 subsequent siblings)
3 siblings, 2 replies; 11+ messages in thread
From: Han Gao @ 2025-07-05 7:39 UTC (permalink / raw)
To: devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, Thomas Bonnefille, Guo Ren, Chao Wei,
linux-riscv, sophgo, linux-kernel, Conor Dooley
Add DT binding documentation for the Sophgo SG2042_EVB_V1.X/V2.0 board [1].
Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
Documentation/devicetree/bindings/riscv/sophgo.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
index b4c4d7a7d7ad..e21b65938a65 100644
--- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
+++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
@@ -34,6 +34,8 @@ properties:
- items:
- enum:
- milkv,pioneer
+ - sophgo,sg2042-evb-v1
+ - sophgo,sg2042-evb-v2
- const: sophgo,sg2042
- items:
- enum:
--
2.47.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 1/3] dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
2025-07-05 7:39 ` [PATCH v3 1/3] dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings Han Gao
@ 2025-07-08 0:31 ` Chen Wang
2025-07-08 3:20 ` Nutty Liu
1 sibling, 0 replies; 11+ messages in thread
From: Chen Wang @ 2025-07-08 0:31 UTC (permalink / raw)
To: Han Gao, devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Inochi Amaoto,
Thomas Bonnefille, Guo Ren, Chao Wei, linux-riscv, sophgo,
linux-kernel, Conor Dooley
On 2025/7/5 15:39, Han Gao wrote:
> Add DT binding documentation for the Sophgo SG2042_EVB_V1.X/V2.0 board [1].
>
> Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1]
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
> ---
> Documentation/devicetree/bindings/riscv/sophgo.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> index b4c4d7a7d7ad..e21b65938a65 100644
> --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> @@ -34,6 +34,8 @@ properties:
> - items:
> - enum:
> - milkv,pioneer
> + - sophgo,sg2042-evb-v1
> + - sophgo,sg2042-evb-v2
> - const: sophgo,sg2042
> - items:
> - enum:
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
2025-07-05 7:39 ` [PATCH v3 1/3] dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings Han Gao
2025-07-08 0:31 ` Chen Wang
@ 2025-07-08 3:20 ` Nutty Liu
1 sibling, 0 replies; 11+ messages in thread
From: Nutty Liu @ 2025-07-08 3:20 UTC (permalink / raw)
To: Han Gao, devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Thomas Bonnefille, Guo Ren, Chao Wei, linux-riscv,
sophgo, linux-kernel, Conor Dooley
On 7/5/2025 3:39 PM, Han Gao wrote:
> Add DT binding documentation for the Sophgo SG2042_EVB_V1.X/V2.0 board [1].
>
> Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1]
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Thanks,
Nutty
> ---
> Documentation/devicetree/bindings/riscv/sophgo.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> index b4c4d7a7d7ad..e21b65938a65 100644
> --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> @@ -34,6 +34,8 @@ properties:
> - items:
> - enum:
> - milkv,pioneer
> + - sophgo,sg2042-evb-v1
> + - sophgo,sg2042-evb-v2
> - const: sophgo,sg2042
> - items:
> - enum:
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 2/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
2025-07-05 7:39 [PATCH v3 0/3] Add Sophgo EVB V1/V2 Board support Han Gao
2025-07-05 7:39 ` [PATCH v3 1/3] dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings Han Gao
@ 2025-07-05 7:39 ` Han Gao
2025-07-08 0:35 ` Chen Wang
2025-07-08 3:20 ` Nutty Liu
2025-07-05 7:39 ` [PATCH v3 3/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 " Han Gao
2025-07-14 0:47 ` [PATCH v3 0/3] Add Sophgo EVB V1/V2 Board support Inochi Amaoto
3 siblings, 2 replies; 11+ messages in thread
From: Han Gao @ 2025-07-05 7:39 UTC (permalink / raw)
To: devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, Thomas Bonnefille, Guo Ren, Chao Wei,
linux-riscv, sophgo, linux-kernel
Sophgo SG2042_EVB_V1.X [1] is a prototype development board based on SG2042
Currently supports serial port, sdcard/emmc, pwm, fan speed control.
Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1]
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
arch/riscv/boot/dts/sophgo/Makefile | 1 +
arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 245 +++++++++++++++++++
2 files changed, 246 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
index 85966306801e..6c9b29681cad 100644
--- a/arch/riscv/boot/dts/sophgo/Makefile
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
new file mode 100644
index 000000000000..3320bc1dd2c6
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
+ */
+
+#include "sg2042.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Sophgo SG2042 EVB V1.X";
+ compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ gpio-power {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power Key";
+ linux,code = <KEY_POWER>;
+ gpios = <&port0a 22 GPIO_ACTIVE_HIGH>;
+ linux,input-type = <EV_KEY>;
+ debounce-interval = <100>;
+ };
+ };
+
+ pwmfan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <103 128 179 230 255>;
+ pwms = <&pwm 0 40000 0>;
+ #cooling-cells = <2>;
+ };
+
+ thermal-zones {
+ soc-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+ thermal-sensors = <&mcu 0>;
+
+ trips {
+ soc_active1: soc-active1 {
+ temperature = <30000>;
+ hysteresis = <8000>;
+ type = "active";
+ };
+
+ soc_active2: soc-active2 {
+ temperature = <58000>;
+ hysteresis = <12000>;
+ type = "active";
+ };
+
+ soc_active3: soc-active3 {
+ temperature = <70000>;
+ hysteresis = <10000>;
+ type = "active";
+ };
+
+ soc_hot: soc-hot {
+ temperature = <80000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&soc_active1>;
+ cooling-device = <&pwmfan 0 1>;
+ };
+
+ map1 {
+ trip = <&soc_active2>;
+ cooling-device = <&pwmfan 1 2>;
+ };
+
+ map2 {
+ trip = <&soc_active3>;
+ cooling-device = <&pwmfan 2 3>;
+ };
+
+ map3 {
+ trip = <&soc_hot>;
+ cooling-device = <&pwmfan 3 4>;
+ };
+ };
+ };
+
+ board-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+ thermal-sensors = <&mcu 1>;
+
+ trips {
+ board_active: board-active {
+ temperature = <75000>;
+ hysteresis = <8000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map4 {
+ trip = <&board_active>;
+ cooling-device = <&pwmfan 3 4>;
+ };
+ };
+ };
+ };
+};
+
+&cgi_main {
+ clock-frequency = <25000000>;
+};
+
+&cgi_dpll0 {
+ clock-frequency = <25000000>;
+};
+
+&cgi_dpll1 {
+ clock-frequency = <25000000>;
+};
+
+&emmc {
+ pinctrl-0 = <&emmc_cfg>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ wp-inverted;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mcu: syscon@17 {
+ compatible = "sophgo,sg2042-hwmon-mcu";
+ reg = <0x17>;
+ #thermal-sensor-cells = <1>;
+ };
+};
+
+&gmac0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ phy0: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <100000>;
+ reset-deassert-us = <100000>;
+ };
+ };
+};
+
+&pinctrl {
+ emmc_cfg: sdhci-emmc-cfg {
+ sdhci-emmc-wp-pins {
+ pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
+ bias-disable;
+ drive-strength-microamp = <26800>;
+ input-schmitt-disable;
+ };
+
+ sdhci-emmc-cd-pins {
+ pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <26800>;
+ input-schmitt-enable;
+ };
+
+ sdhci-emmc-rst-pwr-pins {
+ pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
+ <PINMUX(PIN_EMMC_PWR_EN, 0)>;
+ bias-disable;
+ drive-strength-microamp = <26800>;
+ input-schmitt-disable;
+ };
+ };
+
+ i2c1_cfg: i2c1-cfg {
+ i2c1-pins {
+ pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
+ <PINMUX(PIN_IIC1_SCL, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <26800>;
+ input-schmitt-enable;
+ };
+ };
+
+ sd_cfg: sdhci-sd-cfg {
+ sdhci-sd-cd-wp-pins {
+ pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
+ <PINMUX(PIN_SDIO_WP, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <26800>;
+ input-schmitt-enable;
+ };
+
+ sdhci-sd-rst-pwr-pins {
+ pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
+ <PINMUX(PIN_SDIO_PWR_EN, 0)>;
+ bias-disable;
+ drive-strength-microamp = <26800>;
+ input-schmitt-disable;
+ };
+ };
+
+ uart0_cfg: uart0-cfg {
+ uart0-rx-pins {
+ pinmux = <PINMUX(PIN_UART0_TX, 0)>,
+ <PINMUX(PIN_UART0_RX, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <26800>;
+ input-schmitt-enable;
+ };
+ };
+};
+
+&sd {
+ pinctrl-0 = <&sd_cfg>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+ wp-inverted;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.47.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 2/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
2025-07-05 7:39 ` [PATCH v3 2/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree Han Gao
@ 2025-07-08 0:35 ` Chen Wang
2025-07-08 3:20 ` Nutty Liu
1 sibling, 0 replies; 11+ messages in thread
From: Chen Wang @ 2025-07-08 0:35 UTC (permalink / raw)
To: Han Gao, devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Inochi Amaoto,
Thomas Bonnefille, Guo Ren, Chao Wei, linux-riscv, sophgo,
linux-kernel
On 2025/7/5 15:39, Han Gao wrote:
> Sophgo SG2042_EVB_V1.X [1] is a prototype development board based on SG2042
>
> Currently supports serial port, sdcard/emmc, pwm, fan speed control.
>
> Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1]
>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Just note that the patch for ethernet support has not yet been upstreamed.
> ---
> arch/riscv/boot/dts/sophgo/Makefile | 1 +
> arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 245 +++++++++++++++++++
> 2 files changed, 246 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
>
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 85966306801e..6c9b29681cad 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
> new file mode 100644
> index 000000000000..3320bc1dd2c6
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
> @@ -0,0 +1,245 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +#include "sg2042.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + model = "Sophgo SG2042 EVB V1.X";
> + compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042";
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + gpio-power {
> + compatible = "gpio-keys";
> +
> + key-power {
> + label = "Power Key";
> + linux,code = <KEY_POWER>;
> + gpios = <&port0a 22 GPIO_ACTIVE_HIGH>;
> + linux,input-type = <EV_KEY>;
> + debounce-interval = <100>;
> + };
> + };
> +
> + pwmfan: pwm-fan {
> + compatible = "pwm-fan";
> + cooling-levels = <103 128 179 230 255>;
> + pwms = <&pwm 0 40000 0>;
> + #cooling-cells = <2>;
> + };
> +
> + thermal-zones {
> + soc-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> + thermal-sensors = <&mcu 0>;
> +
> + trips {
> + soc_active1: soc-active1 {
> + temperature = <30000>;
> + hysteresis = <8000>;
> + type = "active";
> + };
> +
> + soc_active2: soc-active2 {
> + temperature = <58000>;
> + hysteresis = <12000>;
> + type = "active";
> + };
> +
> + soc_active3: soc-active3 {
> + temperature = <70000>;
> + hysteresis = <10000>;
> + type = "active";
> + };
> +
> + soc_hot: soc-hot {
> + temperature = <80000>;
> + hysteresis = <5000>;
> + type = "hot";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&soc_active1>;
> + cooling-device = <&pwmfan 0 1>;
> + };
> +
> + map1 {
> + trip = <&soc_active2>;
> + cooling-device = <&pwmfan 1 2>;
> + };
> +
> + map2 {
> + trip = <&soc_active3>;
> + cooling-device = <&pwmfan 2 3>;
> + };
> +
> + map3 {
> + trip = <&soc_hot>;
> + cooling-device = <&pwmfan 3 4>;
> + };
> + };
> + };
> +
> + board-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> + thermal-sensors = <&mcu 1>;
> +
> + trips {
> + board_active: board-active {
> + temperature = <75000>;
> + hysteresis = <8000>;
> + type = "active";
> + };
> + };
> +
> + cooling-maps {
> + map4 {
> + trip = <&board_active>;
> + cooling-device = <&pwmfan 3 4>;
> + };
> + };
> + };
> + };
> +};
> +
> +&cgi_main {
> + clock-frequency = <25000000>;
> +};
> +
> +&cgi_dpll0 {
> + clock-frequency = <25000000>;
> +};
> +
> +&cgi_dpll1 {
> + clock-frequency = <25000000>;
> +};
> +
> +&emmc {
> + pinctrl-0 = <&emmc_cfg>;
> + pinctrl-names = "default";
> + bus-width = <4>;
> + no-sdio;
> + no-sd;
> + non-removable;
> + wp-inverted;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-0 = <&i2c1_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mcu: syscon@17 {
> + compatible = "sophgo,sg2042-hwmon-mcu";
> + reg = <0x17>;
> + #thermal-sensor-cells = <1>;
> + };
> +};
> +
> +&gmac0 {
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + mdio {
> + phy0: phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <100000>;
> + reset-deassert-us = <100000>;
> + };
> + };
> +};
> +
> +&pinctrl {
> + emmc_cfg: sdhci-emmc-cfg {
> + sdhci-emmc-wp-pins {
> + pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> +
> + sdhci-emmc-cd-pins {
> + pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> +
> + sdhci-emmc-rst-pwr-pins {
> + pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
> + <PINMUX(PIN_EMMC_PWR_EN, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> + };
> +
> + i2c1_cfg: i2c1-cfg {
> + i2c1-pins {
> + pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
> + <PINMUX(PIN_IIC1_SCL, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> + };
> +
> + sd_cfg: sdhci-sd-cfg {
> + sdhci-sd-cd-wp-pins {
> + pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
> + <PINMUX(PIN_SDIO_WP, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> +
> + sdhci-sd-rst-pwr-pins {
> + pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
> + <PINMUX(PIN_SDIO_PWR_EN, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> + };
> +
> + uart0_cfg: uart0-cfg {
> + uart0-rx-pins {
> + pinmux = <PINMUX(PIN_UART0_TX, 0)>,
> + <PINMUX(PIN_UART0_RX, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> + };
> +};
> +
> +&sd {
> + pinctrl-0 = <&sd_cfg>;
> + pinctrl-names = "default";
> + bus-width = <4>;
> + no-sdio;
> + no-mmc;
> + wp-inverted;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 2/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
2025-07-05 7:39 ` [PATCH v3 2/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree Han Gao
2025-07-08 0:35 ` Chen Wang
@ 2025-07-08 3:20 ` Nutty Liu
1 sibling, 0 replies; 11+ messages in thread
From: Nutty Liu @ 2025-07-08 3:20 UTC (permalink / raw)
To: Han Gao, devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Thomas Bonnefille, Guo Ren, Chao Wei, linux-riscv,
sophgo, linux-kernel
On 7/5/2025 3:39 PM, Han Gao wrote:
> Sophgo SG2042_EVB_V1.X [1] is a prototype development board based on SG2042
>
> Currently supports serial port, sdcard/emmc, pwm, fan speed control.
>
> Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1]
>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Thanks,
Nutty
> ---
> arch/riscv/boot/dts/sophgo/Makefile | 1 +
> arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 245 +++++++++++++++++++
> 2 files changed, 246 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
>
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 85966306801e..6c9b29681cad 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
> new file mode 100644
> index 000000000000..3320bc1dd2c6
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
> @@ -0,0 +1,245 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +#include "sg2042.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + model = "Sophgo SG2042 EVB V1.X";
> + compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042";
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + gpio-power {
> + compatible = "gpio-keys";
> +
> + key-power {
> + label = "Power Key";
> + linux,code = <KEY_POWER>;
> + gpios = <&port0a 22 GPIO_ACTIVE_HIGH>;
> + linux,input-type = <EV_KEY>;
> + debounce-interval = <100>;
> + };
> + };
> +
> + pwmfan: pwm-fan {
> + compatible = "pwm-fan";
> + cooling-levels = <103 128 179 230 255>;
> + pwms = <&pwm 0 40000 0>;
> + #cooling-cells = <2>;
> + };
> +
> + thermal-zones {
> + soc-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> + thermal-sensors = <&mcu 0>;
> +
> + trips {
> + soc_active1: soc-active1 {
> + temperature = <30000>;
> + hysteresis = <8000>;
> + type = "active";
> + };
> +
> + soc_active2: soc-active2 {
> + temperature = <58000>;
> + hysteresis = <12000>;
> + type = "active";
> + };
> +
> + soc_active3: soc-active3 {
> + temperature = <70000>;
> + hysteresis = <10000>;
> + type = "active";
> + };
> +
> + soc_hot: soc-hot {
> + temperature = <80000>;
> + hysteresis = <5000>;
> + type = "hot";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&soc_active1>;
> + cooling-device = <&pwmfan 0 1>;
> + };
> +
> + map1 {
> + trip = <&soc_active2>;
> + cooling-device = <&pwmfan 1 2>;
> + };
> +
> + map2 {
> + trip = <&soc_active3>;
> + cooling-device = <&pwmfan 2 3>;
> + };
> +
> + map3 {
> + trip = <&soc_hot>;
> + cooling-device = <&pwmfan 3 4>;
> + };
> + };
> + };
> +
> + board-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> + thermal-sensors = <&mcu 1>;
> +
> + trips {
> + board_active: board-active {
> + temperature = <75000>;
> + hysteresis = <8000>;
> + type = "active";
> + };
> + };
> +
> + cooling-maps {
> + map4 {
> + trip = <&board_active>;
> + cooling-device = <&pwmfan 3 4>;
> + };
> + };
> + };
> + };
> +};
> +
> +&cgi_main {
> + clock-frequency = <25000000>;
> +};
> +
> +&cgi_dpll0 {
> + clock-frequency = <25000000>;
> +};
> +
> +&cgi_dpll1 {
> + clock-frequency = <25000000>;
> +};
> +
> +&emmc {
> + pinctrl-0 = <&emmc_cfg>;
> + pinctrl-names = "default";
> + bus-width = <4>;
> + no-sdio;
> + no-sd;
> + non-removable;
> + wp-inverted;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-0 = <&i2c1_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mcu: syscon@17 {
> + compatible = "sophgo,sg2042-hwmon-mcu";
> + reg = <0x17>;
> + #thermal-sensor-cells = <1>;
> + };
> +};
> +
> +&gmac0 {
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + mdio {
> + phy0: phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <100000>;
> + reset-deassert-us = <100000>;
> + };
> + };
> +};
> +
> +&pinctrl {
> + emmc_cfg: sdhci-emmc-cfg {
> + sdhci-emmc-wp-pins {
> + pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> +
> + sdhci-emmc-cd-pins {
> + pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> +
> + sdhci-emmc-rst-pwr-pins {
> + pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
> + <PINMUX(PIN_EMMC_PWR_EN, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> + };
> +
> + i2c1_cfg: i2c1-cfg {
> + i2c1-pins {
> + pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
> + <PINMUX(PIN_IIC1_SCL, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> + };
> +
> + sd_cfg: sdhci-sd-cfg {
> + sdhci-sd-cd-wp-pins {
> + pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
> + <PINMUX(PIN_SDIO_WP, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> +
> + sdhci-sd-rst-pwr-pins {
> + pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
> + <PINMUX(PIN_SDIO_PWR_EN, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> + };
> +
> + uart0_cfg: uart0-cfg {
> + uart0-rx-pins {
> + pinmux = <PINMUX(PIN_UART0_TX, 0)>,
> + <PINMUX(PIN_UART0_RX, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> + };
> +};
> +
> +&sd {
> + pinctrl-0 = <&sd_cfg>;
> + pinctrl-names = "default";
> + bus-width = <4>;
> + no-sdio;
> + no-mmc;
> + wp-inverted;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 3/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
2025-07-05 7:39 [PATCH v3 0/3] Add Sophgo EVB V1/V2 Board support Han Gao
2025-07-05 7:39 ` [PATCH v3 1/3] dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings Han Gao
2025-07-05 7:39 ` [PATCH v3 2/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree Han Gao
@ 2025-07-05 7:39 ` Han Gao
2025-07-08 0:36 ` Chen Wang
2025-07-08 3:21 ` Nutty Liu
2025-07-14 0:47 ` [PATCH v3 0/3] Add Sophgo EVB V1/V2 Board support Inochi Amaoto
3 siblings, 2 replies; 11+ messages in thread
From: Han Gao @ 2025-07-05 7:39 UTC (permalink / raw)
To: devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, Thomas Bonnefille, Guo Ren, Chao Wei,
linux-riscv, sophgo, linux-kernel
Sophgo SG2042_EVB_V2.0 [1] is a prototype development board based on SG2042
Currently supports serial port, sdcard/emmc, pwm, fan speed control.
Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x4-EVB [1]
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
arch/riscv/boot/dts/sophgo/Makefile | 1 +
arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 233 +++++++++++++++++++
2 files changed, 234 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
index 6c9b29681cad..6f65526d4193 100644
--- a/arch/riscv/boot/dts/sophgo/Makefile
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
new file mode 100644
index 000000000000..46980e41b886
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
+ */
+
+#include "sg2042.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Sophgo SG2042 EVB V2.0";
+ compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ pwmfan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <103 128 179 230 255>;
+ pwms = <&pwm 0 40000 0>;
+ #cooling-cells = <2>;
+ };
+
+ thermal-zones {
+ soc-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+ thermal-sensors = <&mcu 0>;
+
+ trips {
+ soc_active1: soc-active1 {
+ temperature = <30000>;
+ hysteresis = <8000>;
+ type = "active";
+ };
+
+ soc_active2: soc-active2 {
+ temperature = <58000>;
+ hysteresis = <12000>;
+ type = "active";
+ };
+
+ soc_active3: soc-active3 {
+ temperature = <70000>;
+ hysteresis = <10000>;
+ type = "active";
+ };
+
+ soc_hot: soc-hot {
+ temperature = <80000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&soc_active1>;
+ cooling-device = <&pwmfan 0 1>;
+ };
+
+ map1 {
+ trip = <&soc_active2>;
+ cooling-device = <&pwmfan 1 2>;
+ };
+
+ map2 {
+ trip = <&soc_active3>;
+ cooling-device = <&pwmfan 2 3>;
+ };
+
+ map3 {
+ trip = <&soc_hot>;
+ cooling-device = <&pwmfan 3 4>;
+ };
+ };
+ };
+
+ board-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+ thermal-sensors = <&mcu 1>;
+
+ trips {
+ board_active: board-active {
+ temperature = <75000>;
+ hysteresis = <8000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map4 {
+ trip = <&board_active>;
+ cooling-device = <&pwmfan 3 4>;
+ };
+ };
+ };
+ };
+};
+
+&cgi_main {
+ clock-frequency = <25000000>;
+};
+
+&cgi_dpll0 {
+ clock-frequency = <25000000>;
+};
+
+&cgi_dpll1 {
+ clock-frequency = <25000000>;
+};
+
+&emmc {
+ pinctrl-0 = <&emmc_cfg>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ wp-inverted;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mcu: syscon@17 {
+ compatible = "sophgo,sg2042-hwmon-mcu";
+ reg = <0x17>;
+ #thermal-sensor-cells = <1>;
+ };
+};
+
+&gmac0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ phy0: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <100000>;
+ reset-deassert-us = <100000>;
+ };
+ };
+};
+
+&pinctrl {
+ emmc_cfg: sdhci-emmc-cfg {
+ sdhci-emmc-wp-pins {
+ pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
+ bias-disable;
+ drive-strength-microamp = <26800>;
+ input-schmitt-disable;
+ };
+
+ sdhci-emmc-cd-pins {
+ pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <26800>;
+ input-schmitt-enable;
+ };
+
+ sdhci-emmc-rst-pwr-pins {
+ pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
+ <PINMUX(PIN_EMMC_PWR_EN, 0)>;
+ bias-disable;
+ drive-strength-microamp = <26800>;
+ input-schmitt-disable;
+ };
+ };
+
+ i2c1_cfg: i2c1-cfg {
+ i2c1-pins {
+ pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
+ <PINMUX(PIN_IIC1_SCL, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <26800>;
+ input-schmitt-enable;
+ };
+ };
+
+ sd_cfg: sdhci-sd-cfg {
+ sdhci-sd-cd-wp-pins {
+ pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
+ <PINMUX(PIN_SDIO_WP, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <26800>;
+ input-schmitt-enable;
+ };
+
+ sdhci-sd-rst-pwr-pins {
+ pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
+ <PINMUX(PIN_SDIO_PWR_EN, 0)>;
+ bias-disable;
+ drive-strength-microamp = <26800>;
+ input-schmitt-disable;
+ };
+ };
+
+ uart0_cfg: uart0-cfg {
+ uart0-rx-pins {
+ pinmux = <PINMUX(PIN_UART0_TX, 0)>,
+ <PINMUX(PIN_UART0_RX, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <26800>;
+ input-schmitt-enable;
+ };
+ };
+};
+
+&sd {
+ pinctrl-0 = <&sd_cfg>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+ wp-inverted;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.47.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 3/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
2025-07-05 7:39 ` [PATCH v3 3/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 " Han Gao
@ 2025-07-08 0:36 ` Chen Wang
2025-07-08 3:21 ` Nutty Liu
1 sibling, 0 replies; 11+ messages in thread
From: Chen Wang @ 2025-07-08 0:36 UTC (permalink / raw)
To: Han Gao, devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Inochi Amaoto,
Thomas Bonnefille, Guo Ren, Chao Wei, linux-riscv, sophgo,
linux-kernel
On 2025/7/5 15:39, Han Gao wrote:
> Sophgo SG2042_EVB_V2.0 [1] is a prototype development board based on SG2042
>
> Currently supports serial port, sdcard/emmc, pwm, fan speed control.
>
> Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x4-EVB [1]
>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Just note that the patch for ethernet support has not yet been upstreamed.
> ---
> arch/riscv/boot/dts/sophgo/Makefile | 1 +
> arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 233 +++++++++++++++++++
> 2 files changed, 234 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
>
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 6c9b29681cad..6f65526d4193 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
> new file mode 100644
> index 000000000000..46980e41b886
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
> @@ -0,0 +1,233 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +#include "sg2042.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + model = "Sophgo SG2042 EVB V2.0";
> + compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042";
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + pwmfan: pwm-fan {
> + compatible = "pwm-fan";
> + cooling-levels = <103 128 179 230 255>;
> + pwms = <&pwm 0 40000 0>;
> + #cooling-cells = <2>;
> + };
> +
> + thermal-zones {
> + soc-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> + thermal-sensors = <&mcu 0>;
> +
> + trips {
> + soc_active1: soc-active1 {
> + temperature = <30000>;
> + hysteresis = <8000>;
> + type = "active";
> + };
> +
> + soc_active2: soc-active2 {
> + temperature = <58000>;
> + hysteresis = <12000>;
> + type = "active";
> + };
> +
> + soc_active3: soc-active3 {
> + temperature = <70000>;
> + hysteresis = <10000>;
> + type = "active";
> + };
> +
> + soc_hot: soc-hot {
> + temperature = <80000>;
> + hysteresis = <5000>;
> + type = "hot";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&soc_active1>;
> + cooling-device = <&pwmfan 0 1>;
> + };
> +
> + map1 {
> + trip = <&soc_active2>;
> + cooling-device = <&pwmfan 1 2>;
> + };
> +
> + map2 {
> + trip = <&soc_active3>;
> + cooling-device = <&pwmfan 2 3>;
> + };
> +
> + map3 {
> + trip = <&soc_hot>;
> + cooling-device = <&pwmfan 3 4>;
> + };
> + };
> + };
> +
> + board-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> + thermal-sensors = <&mcu 1>;
> +
> + trips {
> + board_active: board-active {
> + temperature = <75000>;
> + hysteresis = <8000>;
> + type = "active";
> + };
> + };
> +
> + cooling-maps {
> + map4 {
> + trip = <&board_active>;
> + cooling-device = <&pwmfan 3 4>;
> + };
> + };
> + };
> + };
> +};
> +
> +&cgi_main {
> + clock-frequency = <25000000>;
> +};
> +
> +&cgi_dpll0 {
> + clock-frequency = <25000000>;
> +};
> +
> +&cgi_dpll1 {
> + clock-frequency = <25000000>;
> +};
> +
> +&emmc {
> + pinctrl-0 = <&emmc_cfg>;
> + pinctrl-names = "default";
> + bus-width = <4>;
> + no-sdio;
> + no-sd;
> + non-removable;
> + wp-inverted;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-0 = <&i2c1_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mcu: syscon@17 {
> + compatible = "sophgo,sg2042-hwmon-mcu";
> + reg = <0x17>;
> + #thermal-sensor-cells = <1>;
> + };
> +};
> +
> +&gmac0 {
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + mdio {
> + phy0: phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <100000>;
> + reset-deassert-us = <100000>;
> + };
> + };
> +};
> +
> +&pinctrl {
> + emmc_cfg: sdhci-emmc-cfg {
> + sdhci-emmc-wp-pins {
> + pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> +
> + sdhci-emmc-cd-pins {
> + pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> +
> + sdhci-emmc-rst-pwr-pins {
> + pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
> + <PINMUX(PIN_EMMC_PWR_EN, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> + };
> +
> + i2c1_cfg: i2c1-cfg {
> + i2c1-pins {
> + pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
> + <PINMUX(PIN_IIC1_SCL, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> + };
> +
> + sd_cfg: sdhci-sd-cfg {
> + sdhci-sd-cd-wp-pins {
> + pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
> + <PINMUX(PIN_SDIO_WP, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> +
> + sdhci-sd-rst-pwr-pins {
> + pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
> + <PINMUX(PIN_SDIO_PWR_EN, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> + };
> +
> + uart0_cfg: uart0-cfg {
> + uart0-rx-pins {
> + pinmux = <PINMUX(PIN_UART0_TX, 0)>,
> + <PINMUX(PIN_UART0_RX, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> + };
> +};
> +
> +&sd {
> + pinctrl-0 = <&sd_cfg>;
> + pinctrl-names = "default";
> + bus-width = <4>;
> + no-sdio;
> + no-mmc;
> + wp-inverted;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 3/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
2025-07-05 7:39 ` [PATCH v3 3/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 " Han Gao
2025-07-08 0:36 ` Chen Wang
@ 2025-07-08 3:21 ` Nutty Liu
1 sibling, 0 replies; 11+ messages in thread
From: Nutty Liu @ 2025-07-08 3:21 UTC (permalink / raw)
To: Han Gao, devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Thomas Bonnefille, Guo Ren, Chao Wei, linux-riscv,
sophgo, linux-kernel
On 7/5/2025 3:39 PM, Han Gao wrote:
> Sophgo SG2042_EVB_V2.0 [1] is a prototype development board based on SG2042
>
> Currently supports serial port, sdcard/emmc, pwm, fan speed control.
>
> Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x4-EVB [1]
>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Thanks,
Nutty
> ---
> arch/riscv/boot/dts/sophgo/Makefile | 1 +
> arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 233 +++++++++++++++++++
> 2 files changed, 234 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
>
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 6c9b29681cad..6f65526d4193 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
> new file mode 100644
> index 000000000000..46980e41b886
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
> @@ -0,0 +1,233 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +#include "sg2042.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + model = "Sophgo SG2042 EVB V2.0";
> + compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042";
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + pwmfan: pwm-fan {
> + compatible = "pwm-fan";
> + cooling-levels = <103 128 179 230 255>;
> + pwms = <&pwm 0 40000 0>;
> + #cooling-cells = <2>;
> + };
> +
> + thermal-zones {
> + soc-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> + thermal-sensors = <&mcu 0>;
> +
> + trips {
> + soc_active1: soc-active1 {
> + temperature = <30000>;
> + hysteresis = <8000>;
> + type = "active";
> + };
> +
> + soc_active2: soc-active2 {
> + temperature = <58000>;
> + hysteresis = <12000>;
> + type = "active";
> + };
> +
> + soc_active3: soc-active3 {
> + temperature = <70000>;
> + hysteresis = <10000>;
> + type = "active";
> + };
> +
> + soc_hot: soc-hot {
> + temperature = <80000>;
> + hysteresis = <5000>;
> + type = "hot";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&soc_active1>;
> + cooling-device = <&pwmfan 0 1>;
> + };
> +
> + map1 {
> + trip = <&soc_active2>;
> + cooling-device = <&pwmfan 1 2>;
> + };
> +
> + map2 {
> + trip = <&soc_active3>;
> + cooling-device = <&pwmfan 2 3>;
> + };
> +
> + map3 {
> + trip = <&soc_hot>;
> + cooling-device = <&pwmfan 3 4>;
> + };
> + };
> + };
> +
> + board-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> + thermal-sensors = <&mcu 1>;
> +
> + trips {
> + board_active: board-active {
> + temperature = <75000>;
> + hysteresis = <8000>;
> + type = "active";
> + };
> + };
> +
> + cooling-maps {
> + map4 {
> + trip = <&board_active>;
> + cooling-device = <&pwmfan 3 4>;
> + };
> + };
> + };
> + };
> +};
> +
> +&cgi_main {
> + clock-frequency = <25000000>;
> +};
> +
> +&cgi_dpll0 {
> + clock-frequency = <25000000>;
> +};
> +
> +&cgi_dpll1 {
> + clock-frequency = <25000000>;
> +};
> +
> +&emmc {
> + pinctrl-0 = <&emmc_cfg>;
> + pinctrl-names = "default";
> + bus-width = <4>;
> + no-sdio;
> + no-sd;
> + non-removable;
> + wp-inverted;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-0 = <&i2c1_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mcu: syscon@17 {
> + compatible = "sophgo,sg2042-hwmon-mcu";
> + reg = <0x17>;
> + #thermal-sensor-cells = <1>;
> + };
> +};
> +
> +&gmac0 {
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + mdio {
> + phy0: phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <100000>;
> + reset-deassert-us = <100000>;
> + };
> + };
> +};
> +
> +&pinctrl {
> + emmc_cfg: sdhci-emmc-cfg {
> + sdhci-emmc-wp-pins {
> + pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> +
> + sdhci-emmc-cd-pins {
> + pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> +
> + sdhci-emmc-rst-pwr-pins {
> + pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
> + <PINMUX(PIN_EMMC_PWR_EN, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> + };
> +
> + i2c1_cfg: i2c1-cfg {
> + i2c1-pins {
> + pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
> + <PINMUX(PIN_IIC1_SCL, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> + };
> +
> + sd_cfg: sdhci-sd-cfg {
> + sdhci-sd-cd-wp-pins {
> + pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
> + <PINMUX(PIN_SDIO_WP, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> +
> + sdhci-sd-rst-pwr-pins {
> + pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
> + <PINMUX(PIN_SDIO_PWR_EN, 0)>;
> + bias-disable;
> + drive-strength-microamp = <26800>;
> + input-schmitt-disable;
> + };
> + };
> +
> + uart0_cfg: uart0-cfg {
> + uart0-rx-pins {
> + pinmux = <PINMUX(PIN_UART0_TX, 0)>,
> + <PINMUX(PIN_UART0_RX, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <26800>;
> + input-schmitt-enable;
> + };
> + };
> +};
> +
> +&sd {
> + pinctrl-0 = <&sd_cfg>;
> + pinctrl-names = "default";
> + bus-width = <4>;
> + no-sdio;
> + no-mmc;
> + wp-inverted;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/3] Add Sophgo EVB V1/V2 Board support
2025-07-05 7:39 [PATCH v3 0/3] Add Sophgo EVB V1/V2 Board support Han Gao
` (2 preceding siblings ...)
2025-07-05 7:39 ` [PATCH v3 3/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 " Han Gao
@ 2025-07-14 0:47 ` Inochi Amaoto
3 siblings, 0 replies; 11+ messages in thread
From: Inochi Amaoto @ 2025-07-14 0:47 UTC (permalink / raw)
To: devicetree, Han Gao
Cc: Inochi Amaoto, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Chen Wang, Thomas Bonnefille, Guo Ren, Chao Wei, linux-riscv,
sophgo, linux-kernel
On Sat, 05 Jul 2025 15:39:53 +0800, Han Gao wrote:
> Sophgo EVB V1/V2 [1][2] is a prototype board based on SOPHON SG2042 [3].
> There are many of these two boards in the hands of developers.
>
> Currently supports serial port, sdcard/emmc, pwm, fan speed control.
>
> Added ethernet support based on [4].
>
> [...]
Applied to for-next, thanks!
[1/3] dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
https://github.com/sophgo/linux/commit/a42a510c1a9119a8413e20fe09ce3c3cd85ea7db
[2/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
https://github.com/sophgo/linux/commit/1bf2708394942e047e08146dc8d2a34c091280de
[3/3] riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
https://github.com/sophgo/linux/commit/6ca1c3d005cdb9bd619a2dec6ed63ef9ba29eb37
Thanks,
Inochi
^ permalink raw reply [flat|nested] 11+ messages in thread