From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_NONE,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by archive.lwn.net (Postfix) with ESMTP id D319A7D910 for ; Wed, 11 Mar 2020 15:48:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730023AbgCKPsL (ORCPT ); Wed, 11 Mar 2020 11:48:11 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:1212 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729977AbgCKPsL (ORCPT ); Wed, 11 Mar 2020 11:48:11 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 11 Mar 2020 08:47:25 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 11 Mar 2020 08:48:10 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 11 Mar 2020 08:48:10 -0700 Received: from [10.25.76.193] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 11 Mar 2020 15:48:05 +0000 Subject: Re: [PATCH V5 0/5] Add support for PCIe endpoint mode in Tegra194 To: Lorenzo Pieralisi , CC: , , , , , , , , , , , , , References: <20200303181052.16134-1-vidyas@nvidia.com> <20200311105141.GA30083@e121166-lin.cambridge.arm.com> X-Nvconfidentiality: public From: Vidya Sagar Message-ID: Date: Wed, 11 Mar 2020 21:18:02 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200311105141.GA30083@e121166-lin.cambridge.arm.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1583941645; bh=ywvixbNO+/N+yt4O8EWdBUGbwryGxLJH9bz6Oivel4E=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=FUr9rm3ZDnaGkISW2fqFeQV6c9pGe4voXCRhfLm6YSBXRi1w8HYJNa8/I8bfNPJZ0 hrvJzdioW7B0VV1xDJZl38c+TJcJV+KIjyRryJyYj+nF9IqXosGb48Ru5Rzl7X9PuQ xeqi9ruu0zODcJlLs68teXh/cON40ntYNfdx1DuZAkFrt9DKr8AE0NVAcbdP9PcPEg y0TF7XWWQpo73L1oNJfHpDQX3qHnrJJ8qYBxYrWerdWJ6trWhksnPj6k/0qaZdNTVF PkPHL/U5VcNEI8kIWQRmXkUai/qB8i/kSr2X+0RJw+0Am0rEg3tMthMIaAg/ooMlGN n1/Ibsjw1TkiQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Archived-At: List-Archive: List-Post: On 3/11/2020 4:22 PM, Lorenzo Pieralisi wrote: > External email: Use caution opening links or attachments > > > On Tue, Mar 03, 2020 at 11:40:47PM +0530, Vidya Sagar wrote: >> Tegra194 has three (C0, C4 & C5) dual mode PCIe controllers that can operate >> either in root port mode or in end point mode but only in one mode at a time. >> Platform P2972-0000 supports enabling endpoint mode for C5 controller. This >> patch series adds support for PCIe endpoint mode in both the driver as well as >> in DT. >> This patch series depends on the changes made for Synopsys DesignWare endpoint >> mode subsystem that are recently accepted. >> @ https://patchwork.kernel.org/project/linux-pci/list/?series=202211 >> which in turn depends on the patch made by Kishon >> @ https://patchwork.kernel.org/patch/10975123/ >> which is also under review. >> >> V5: >> * Rebased patch-2 on top of Lorenzo's pci/endpoint branch >> * Removed unwanted header files inclusion in patch-5 > > Applied patches 1,2,5 to pci/endpoint for v5.7, please let me know > if something is missing. Thanks Lorenzo and Thierry. Thanks, Vidya Sagar > > Thanks, > Lorenzo > >> V4: >> * Started using threaded irqs instead of kthreads >> >> V3: >> * Re-ordered patches in the series to make the driver change as the last patch >> * Took care of Thierry's review comments >> >> V2: >> * Addressed Thierry & Bjorn's review comments >> * Added EP mode specific binding documentation to already existing binding documentation file >> * Removed patch that enables GPIO controller nodes explicitly as they are enabled already >> >> Vidya Sagar (5): >> soc/tegra: bpmp: Update ABI header >> dt-bindings: PCI: tegra: Add DT support for PCIe EP nodes in Tegra194 >> arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194 >> arm64: tegra: Add support for PCIe endpoint mode in P2972-0000 >> platform >> PCI: tegra: Add support for PCIe endpoint mode in Tegra194 >> >> .../bindings/pci/nvidia,tegra194-pcie.txt | 125 +++- >> .../boot/dts/nvidia/tegra194-p2972-0000.dts | 18 + >> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 99 +++ >> drivers/pci/controller/dwc/Kconfig | 30 +- >> drivers/pci/controller/dwc/pcie-tegra194.c | 679 +++++++++++++++++- >> include/soc/tegra/bpmp-abi.h | 10 +- >> 6 files changed, 916 insertions(+), 45 deletions(-) >> >> -- >> 2.17.1 >>