From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 185E9C33CA9 for ; Mon, 13 Jan 2020 18:13:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E082C207FD for ; Mon, 13 Jan 2020 18:13:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="CZeBN5Ix" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728558AbgAMSNE (ORCPT ); Mon, 13 Jan 2020 13:13:04 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:4593 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726878AbgAMSNE (ORCPT ); Mon, 13 Jan 2020 13:13:04 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 13 Jan 2020 10:12:43 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 13 Jan 2020 10:13:03 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 13 Jan 2020 10:13:03 -0800 Received: from [10.24.37.48] (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 13 Jan 2020 18:12:58 +0000 Subject: Re: Re: [PATCH V2 3/5] PCI: tegra: Add support for PCIe endpoint mode in Tegra194 To: Thierry Reding CC: , , , , , , , , , , , , , , References: <20200103124404.20662-1-vidyas@nvidia.com> <20200103124404.20662-4-vidyas@nvidia.com> <20200106131416.GD1955714@ulmo> X-Nvconfidentiality: public From: Vidya Sagar Message-ID: Date: Mon, 13 Jan 2020 23:42:55 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20200106131416.GD1955714@ulmo> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578939163; bh=nVROaRvnp+B2JlV9vIKYl44RY+sBl1DYcWo1xIkZvMU=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=CZeBN5IxJcvyTspS32vk9DBSShHna0nja8hQ3ot8GeuUS7AxUrSC2xuRJ11SDT2p8 e69CEpHSvcxcNcQqaaGfVgbvf8roQTtxPxeDTKoS9pbbpz1hhAu7m801mL8cPLWnhg +zvTWRHw2OufX2C4cmV/pN7jB85RTsSj2ZARQa8Z/MMtO8hA68DBlXqSkPCIM0q2pY 4wgZUBGGbWGKvWQLD8XyIsHzdFfDhe64R0l4xD2JpKcqW2OzG4PWjpJb6D3PJGu6Bp 6vD8No5Fyt1dJOB5nPAJAHVBsDOZh5CJkraIHB8Q+cZmmLKxTjcHZ2uz4P1LpY40B4 +Yno6Ah18fFMw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 1/6/20 6:44 PM, Thierry Reding wrote: > On Fri, Jan 03, 2020 at 06:14:02PM +0530, Vidya Sagar wrote: >> Add support for the endpoint mode of Synopsys DesignWare core based >> dual mode PCIe controllers present in Tegra194 SoC. >> >> Signed-off-by: Vidya Sagar >> --- >> V2: >> * Addressed Bjorn's review comments >> * Made changes as part of addressing review comments for other patches >> >> drivers/pci/controller/dwc/Kconfig | 30 +- >> drivers/pci/controller/dwc/pcie-tegra194.c | 782 ++++++++++++++++++++- >> 2 files changed, 796 insertions(+), 16 deletions(-) >> > [...] >> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c >> index cbe95f0ea0ca..6621ac79efee 100644 >> --- a/drivers/pci/controller/dwc/pcie-tegra194.c >> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > [...] >> @@ -1427,8 +1620,553 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) > [...] >> +static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie, >> + struct platform_device *pdev) >> +{ > [...] >> + ret = devm_request_irq(dev, pcie->pex_rst_irq, >> + tegra_pcie_ep_pex_rst_irq, >> + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, >> + name, (void *)pcie); >> + if (ret < 0) { >> + dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret); >> + return ret; >> + } >> + disable_irq(pcie->pex_rst_irq); > > I just came across this while reviewing another patch: it looks like a > better way to handle "disabled by default" interrupts is to do this: > > irq_set_status_flags(rtc->irq, IRQ_NOAUTOEN); > > before calling devm_request_irq(). See here for an example: > > http://patchwork.ozlabs.org/patch/1217944/ I'll take care of it. Thanks for the review. Vidya Sagar > > Thierry >