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[79.139.233.37]) by smtp.googlemail.com with ESMTPSA id t8sm11062627lfl.51.2019.11.19.11.32.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Nov 2019 11:32:33 -0800 (PST) Subject: Re: [PATCH v1 12/17] arm: tegra: Add clock-cells property to Tegra pmc To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, mperttunen@nvidia.com, gregkh@linuxfoundation.org, sboyd@kernel.org, tglx@linutronix.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: allison@lohutok.net, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mturquette@baylibre.com, horms+renesas@verge.net.au, Jisheng.Zhang@synaptics.com, krzk@kernel.org, arnd@arndb.de, spujar@nvidia.com, josephl@nvidia.com, vidyas@nvidia.com, daniel.lezcano@linaro.org, mmaddireddy@nvidia.com, markz@nvidia.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> <1574146234-3871-13-git-send-email-skomatineni@nvidia.com> From: Dmitry Osipenko Message-ID: Date: Tue, 19 Nov 2019 22:32:32 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <1574146234-3871-13-git-send-email-skomatineni@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 19.11.2019 09:50, Sowjanya Komatineni пишет: > Tegra pmc has 3 clocks clk_out_1, clk_out_2, clk_out_3 with mux and gate > for each of these clocks as part of pmc and Tegra pmc is the clock provider > for these clocks. > > This patch adds #clock-cells property with 1 clock specifier to > the Tegra pmc node. > > Signed-off-by: Sowjanya Komatineni > --- > arch/arm/boot/dts/tegra114.dtsi | 4 +++- > arch/arm/boot/dts/tegra124.dtsi | 4 +++- > arch/arm/boot/dts/tegra30.dtsi | 4 +++- > 3 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi > index 0d7a6327e404..b8f12f24f314 100644 > --- a/arch/arm/boot/dts/tegra114.dtsi > +++ b/arch/arm/boot/dts/tegra114.dtsi > @@ -4,6 +4,7 @@ > #include > #include > #include > +#include > > / { > compatible = "nvidia,tegra114"; > @@ -514,11 +515,12 @@ > status = "disabled"; > }; > > - pmc@7000e400 { > + pmc: pmc@7000e400 { > compatible = "nvidia,tegra114-pmc"; > reg = <0x7000e400 0x400>; > clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; > clock-names = "pclk", "clk32k_in"; > + #clock-cells = <1>; > }; > > fuse@7000f800 { > diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi > index 413bfb981de8..d0802c4ae3bf 100644 > --- a/arch/arm/boot/dts/tegra124.dtsi > +++ b/arch/arm/boot/dts/tegra124.dtsi > @@ -6,6 +6,7 @@ > #include > #include > #include > +#include > > / { > compatible = "nvidia,tegra124"; > @@ -595,11 +596,12 @@ > clocks = <&tegra_car TEGRA124_CLK_RTC>; > }; > > - pmc@7000e400 { > + pmc: pmc@7000e400 { > compatible = "nvidia,tegra124-pmc"; > reg = <0x0 0x7000e400 0x0 0x400>; > clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; > clock-names = "pclk", "clk32k_in"; > + #clock-cells = <1>; > }; > > fuse@7000f800 { > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi > index 55ae050042ce..4d5e9d0001d3 100644 > --- a/arch/arm/boot/dts/tegra30.dtsi > +++ b/arch/arm/boot/dts/tegra30.dtsi > @@ -4,6 +4,7 @@ > #include > #include > #include > +#include > > / { > compatible = "nvidia,tegra30"; > @@ -714,11 +715,12 @@ > status = "disabled"; > }; > > - pmc@7000e400 { > + pmc: pmc@7000e400 { > compatible = "nvidia,tegra30-pmc"; > reg = <0x7000e400 0x400>; > clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; > clock-names = "pclk", "clk32k_in"; > + #clock-cells = <1>; > }; > > mc: memory-controller@7000f000 { > What about Tegra20?