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Wed, 9 Oct 2024 09:27:08 +0800 (AWST) Message-ID: Subject: Re: [PATCH v4 2/2] ARM: dts: aspeed: sbp1: IBM sbp1 BMC board From: Andrew Jeffery To: Naresh Solanki , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph Date: Wed, 09 Oct 2024 11:57:07 +1030 In-Reply-To: <20241008111924.1865857-2-naresh.solanki@9elements.com> References: <20241008111924.1865857-1-naresh.solanki@9elements.com> <20241008111924.1865857-2-naresh.solanki@9elements.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4-2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Naresh, On Tue, 2024-10-08 at 16:49 +0530, Naresh Solanki wrote: > From: Patrick Rudolph >=20 > Add a device tree for IBM sbp1 BMC board which is based on AST2600 SOC. >=20 > sbp1 baseboard has: > - support for up to four Sapphire Rapids sockets having 16 DIMMS each. > - 240 core/480 threads at maximum > - 32x CPU PCIe slots > - 2x M.2 PCH PCIe slots > - Dual 200Gbit/s NIC > - SPI TPM >=20 > Added the following: > - Indication LEDs > - I2C mux & GPIO controller, pin assignments, > - Thermister, > - Voltage regulator > - EEPROM/VPD >=20 > Signed-off-by: Patrick Rudolph > Signed-off-by: Naresh Solanki >=20 > --- > Changes in V4: > - Move reset related entried under mdio to phy. > - Removed reserved gpio range. > Changes in V3: > Drop unused regulator entries which are not used by drivers. > Decouple p12v_a > Update pincfg for U62120 > --- > arch/arm/boot/dts/aspeed/Makefile | 1 + > .../boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts | 6128 +++++++++++++++++ > 2 files changed, 6129 insertions(+) > create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts >=20 > diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed= /Makefile > index c4f064e4b073..577cc6754c45 100644 > --- a/arch/arm/boot/dts/aspeed/Makefile > +++ b/arch/arm/boot/dts/aspeed/Makefile > @@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ > aspeed-bmc-ibm-rainier-1s4u.dtb \ > aspeed-bmc-ibm-rainier-4u.dtb \ > aspeed-bmc-ibm-system1.dtb \ > + aspeed-bmc-ibm-sbp1.dtb \ Please keep this list sorted alphabetically. > aspeed-bmc-intel-s2600wf.dtb \ > aspeed-bmc-inspur-fp5280g2.dtb \ > aspeed-bmc-inspur-nf5280m6.dtb \ > diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts b/arch/arm/= boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts > new file mode 100644 > index 000000000000..6036a9ca3840 > --- /dev/null > +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts >=20 > + > +&i2c1 { > + status =3D "okay"; > + > + bmc_mux_nic: mux@77 { > + compatible =3D "maxim,max7357"; > + reg =3D <0x77>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + reset-gpios =3D <&gpio0 ASPEED_GPIO(R, 3) (GPIO_ACTIVE_LOW | GPIO_OPEN= _DRAIN)>; > + vdd-supply =3D <&p3v3_aux>; > + > + i2c@0 { > + reg =3D <0>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + smb_pex_nic: pinctrl@20 { >=20 ... > + }; > + }; > + > + i2c@1 { > + reg =3D <1>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + i2c@2 { > + reg =3D <2>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + ir38263-pvcore-nic2@40 { > + compatible =3D "infineon,ir38263"; > + reg =3D <0x40>; > + > + regulators { > + pvcore_nic2: vout { > + regulator-name =3D "pvcore_nic2"; > + regulator-enable-ramp-delay =3D <2000>; > + vin-supply =3D <&p12v>; > + }; > + }; > + }; This doesn't match my understanding of the infineon,ir38263 and regulator bindings. Certainly `make CHECK_DTBS=3Dy ...` complains about it. This is untested, but from my understanding, it should rather be something like: pvcore_nic2: regulator@40 { compatible =3D "infineon,ir38263"; reg =3D <0x40>; =20 regulator-name =3D "pvcore_nic2"; regulator-enable-ramp-delay =3D <2000>; vin-supply =3D <&p12v>; }; Note that this is _not_ the same as the maxim,max5978 binding, which _does_ specify the regulators subnode. Please fix all infineon,ir38263 nodes in the dts. ... > + > + i2c-protocol; > + }; > +}; > + > +&i2c5 { > + status =3D "okay"; > + > + i2cmux2: mux@77 { > + compatible =3D "maxim,max7357"; > + reg =3D <0x77>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + reset-gpios =3D <&gpio0 ASPEED_GPIO(Z, 2) (GPIO_ACTIVE_LOW | GPIO_OPEN= _DRAIN)>; > + vdd-supply =3D <&p3v3_aux>; > + > + i2c@1 { > + reg =3D <1>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + r38263-p1v05-pch-aux@40 { > + compatible =3D "infineon,ir38263"; > + reg =3D <0x40>; > + > + interrupt-parent =3D <&smb_pex_vr_ctrl>; > + interrupts =3D <9 IRQ_TYPE_LEVEL_LOW>; Aside from the regulators subnode issue, the infineon,ir38263 binding doensn't specify interrupt properties. Does it need to be updated? Otherwise, we have the following warning: r38263-p1v05-pch-aux@40: Unevaluated properties are not allowed ('interr= upt-parent', 'interrupts', 'regulators' were unexpected) > + > + regulators { > + p1v05_pch_aux: vout { > + regulator-name =3D "p1v05_pch_aux"; > + regulator-enable-ramp-delay =3D <2000>; > + vin-supply =3D <&p12v>; > + }; > + }; > + }; > + }; > + > + i2c@2 { > + reg =3D <2>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + ir38060-p1v8-pch-aux@40 { > + compatible =3D "infineon,ir38060"; > + reg =3D <0x40>; > + > + interrupt-parent =3D <&smb_pex_vr_ctrl>; > + interrupts =3D <32 IRQ_TYPE_LEVEL_LOW>; As above. Andrew