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Thu, 03 Sep 2026 04:59:30 -0700 (PDT) X-Received: by 2002:a05:620a:6492:b0:937:6f83:e80f with SMTP id af79cd13be357-93960cd1505mr798646085a.1.1788436770236; Thu, 03 Sep 2026 04:59:30 -0700 (PDT) Received: from [192.168.202.12] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c25f42307e6sm88905266b.55.2026.09.03.04.59.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Sep 2026 04:59:29 -0700 (PDT) Message-ID: Date: Thu, 3 Sep 2026 13:59:26 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks To: Luo Jie , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com References: <20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com> <20260814-qcom_ipq5210_cmnpll-v3-9-21c3db378611@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260814-qcom_ipq5210_cmnpll-v3-9-21c3db378611@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 5vYKJVJ0JH5TOz9FtlOlbt2bUm21pNvF X-Proofpoint-ORIG-GUID: 5vYKJVJ0JH5TOz9FtlOlbt2bUm21pNvF X-Authority-Analysis: v=2.4 cv=OZyoyBTY c=1 sm=1 tr=0 ts=6a996123 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=lXqaDxtV36Dhfzo6gJMA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAzMDEwNCBTYWx0ZWRfX0CGQPHPDaWYk AXJ+BkKZBIEsikJ1Lqim47vMRjiHPBpRELR3jbpwv15sqj623ZB25ZzfTgw8cXCtk8qMCdPF0rA GrK8hLKE7/MWLR7r2gSV1ApjipHUflU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAzMDEwNCBTYWx0ZWRfX5QxpGGf7pK7n UBAj3Is08BASlmojUUEG6cbWll816ClYkMIX0QvwR74aO17eYJilYEYAYwEzqI2uWMjDgorsyQ/ YeJbCBjFiJZOZ4Db5vnEDRHsFxuyv6CAxI7C5Nyo+1BkkpBwv201euLIFslTjUpSFtm5uU8BOXp MdyOuhtX8RX7K5tHfCskvPaov3WPrPSQenCdxIQwaAPLI/ViGoV1iyHO4NnoRHNS7QRe4VJJYIm F7wLA/Y8APWxlqauf0efp2XUQ5Lj4bgxAcQ08FFEJjRPN3hbF2XZAs1LpksCpNQGKEu3Vtp5a3D UflxkqmdVVCXp5yySuej2jFrUqtA0L7jSKQ1MDvEu1v5K36sE5rdGxyuQPAvpR3mWAcEXoqzoxS dKRf0D06rtq6vJA5+7iNoB0mPKpYWKwlm7B6SVGoY0YPb8cSL1Xx7zoirzcWL80fKxe0NS7zQ67 RvkErs5GMEaFmzXp+JA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-03_03,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 impostorscore=0 clxscore=1015 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609030104 On 8/14/26 2:48 PM, Luo Jie wrote: > Some CMN PLL output clocks require a hardware gate in addition to a > fixed rate. The gate control bits reside in the register > CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered via a > new struct clk_fixed_gate and clk_fixed_gate_ops, combining a fixed > rate with enable/disable/is_enabled gate control through the shared > regmap for CMN_PLL_OUTPUT_RELATED_1. [...] > +static int clk_fixed_gate_enable(struct clk_hw *hw) > +{ > + struct clk_fixed_gate *gate_clk = to_clk_fixed_gate(hw); > + > + return regmap_set_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, > + BIT(gate_clk->enable_bit)); > +} > + > +static void clk_fixed_gate_disable(struct clk_hw *hw) > +{ > + struct clk_fixed_gate *gate_clk = to_clk_fixed_gate(hw); > + > + regmap_clear_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, > + BIT(gate_clk->enable_bit)); > +} > + > +static int clk_fixed_gate_is_enabled(struct clk_hw *hw) > +{ > + struct clk_fixed_gate *gate_clk = to_clk_fixed_gate(hw); > + > + return regmap_test_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1, > + BIT(gate_clk->enable_bit)); > +} This is also all just clk_regmap / clk_branch Konrad