* [PATCH 0/3] pinctrl: samsung: add Exynos9610 pinctrl support
@ 2025-09-14 19:34 Alexandru Chimac
2025-09-14 19:34 ` [PATCH 1/3] dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible Alexandru Chimac
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Alexandru Chimac @ 2025-09-14 19:34 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Alim Akhtar,
Linus Walleij, Rob Herring, Conor Dooley, Tomasz Figa
Cc: linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree,
linux-kernel, Alexandru Chimac
This patchset adds support for the pin controller found on Exynos9610.
Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
Alexandru Chimac (3):
dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible
dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node
pinctrl: samsung: Add Exynos9610 pinctrl configuration
.../pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 +
.../bindings/pinctrl/samsung,pinctrl.yaml | 1 +
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 109 +++++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
5 files changed, 115 insertions(+)
---
base-commit: 48c4c0b684f394721b7db809e1cc282fccdb33da
change-id: 20250914-exynos9610-pinctrl-b44cdfaeeed1
Best regards,
--
Alexandru Chimac <alex@chimac.ro>
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/3] dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible 2025-09-14 19:34 [PATCH 0/3] pinctrl: samsung: add Exynos9610 pinctrl support Alexandru Chimac @ 2025-09-14 19:34 ` Alexandru Chimac 2025-09-22 15:42 ` Rob Herring (Arm) 2025-09-14 19:34 ` [PATCH 2/3] dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node Alexandru Chimac 2025-09-14 19:34 ` [PATCH 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration Alexandru Chimac 2 siblings, 1 reply; 8+ messages in thread From: Alexandru Chimac @ 2025-09-14 19:34 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Alim Akhtar, Linus Walleij, Rob Herring, Conor Dooley, Tomasz Figa Cc: linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree, linux-kernel, Alexandru Chimac Document pin controller support on Exynos9610-series SoCs. Signed-off-by: Alexandru Chimac <alex@chimac.ro> --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index de846085614166087ef9046cf5d154fb9dad8309..2ebe9353d3bff9f708118a249b5e969aa5fc393f 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -56,6 +56,7 @@ properties: - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynos8895-pinctrl + - samsung,exynos9610-pinctrl - samsung,exynos9810-pinctrl - samsung,exynos990-pinctrl - samsung,exynosautov9-pinctrl -- 2.47.3 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible 2025-09-14 19:34 ` [PATCH 1/3] dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible Alexandru Chimac @ 2025-09-22 15:42 ` Rob Herring (Arm) 0 siblings, 0 replies; 8+ messages in thread From: Rob Herring (Arm) @ 2025-09-22 15:42 UTC (permalink / raw) To: Alexandru Chimac Cc: Sylwester Nawrocki, linux-kernel, Tomasz Figa, Conor Dooley, linux-gpio, Linus Walleij, devicetree, Krzysztof Kozlowski, linux-arm-kernel, Alim Akhtar, linux-samsung-soc On Sun, 14 Sep 2025 19:34:26 +0000, Alexandru Chimac wrote: > Document pin controller support on Exynos9610-series SoCs. > > Signed-off-by: Alexandru Chimac <alex@chimac.ro> > --- > Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring (Arm) <robh@kernel.org> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/3] dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node 2025-09-14 19:34 [PATCH 0/3] pinctrl: samsung: add Exynos9610 pinctrl support Alexandru Chimac 2025-09-14 19:34 ` [PATCH 1/3] dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible Alexandru Chimac @ 2025-09-14 19:34 ` Alexandru Chimac 2025-09-22 15:42 ` Rob Herring (Arm) 2025-09-14 19:34 ` [PATCH 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration Alexandru Chimac 2 siblings, 1 reply; 8+ messages in thread From: Alexandru Chimac @ 2025-09-14 19:34 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Alim Akhtar, Linus Walleij, Rob Herring, Conor Dooley, Tomasz Figa Cc: linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree, linux-kernel, Alexandru Chimac Add a dedicated compatible for the exynos9610-wakeup-eint node, which is compatbile with Exynos850's implementation (and the Exynos7 fallback). Signed-off-by: Alexandru Chimac <alex@chimac.ro> --- .../devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 0da6d69f599171b6946992c036f23c5dea17bd0d..fe06c0d2734960d3fe57783c1c528f58fa297c57 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -49,6 +49,7 @@ properties: - enum: - google,gs101-wakeup-eint - samsung,exynos2200-wakeup-eint + - samsung,exynos9610-wakeup-eint - samsung,exynos9810-wakeup-eint - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint @@ -123,6 +124,7 @@ allOf: contains: enum: - samsung,exynos850-wakeup-eint + - samsung,exynos9610-wakeup-eint - samsung,exynosautov920-wakeup-eint then: properties: -- 2.47.3 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node 2025-09-14 19:34 ` [PATCH 2/3] dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node Alexandru Chimac @ 2025-09-22 15:42 ` Rob Herring (Arm) 0 siblings, 0 replies; 8+ messages in thread From: Rob Herring (Arm) @ 2025-09-22 15:42 UTC (permalink / raw) To: Alexandru Chimac Cc: Linus Walleij, Conor Dooley, Alim Akhtar, Sylwester Nawrocki, Tomasz Figa, linux-arm-kernel, Krzysztof Kozlowski, linux-kernel, devicetree, linux-gpio, linux-samsung-soc On Sun, 14 Sep 2025 19:34:37 +0000, Alexandru Chimac wrote: > Add a dedicated compatible for the exynos9610-wakeup-eint node, > which is compatbile with Exynos850's implementation (and the > Exynos7 fallback). > > Signed-off-by: Alexandru Chimac <alex@chimac.ro> > --- > .../devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring (Arm) <robh@kernel.org> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration 2025-09-14 19:34 [PATCH 0/3] pinctrl: samsung: add Exynos9610 pinctrl support Alexandru Chimac 2025-09-14 19:34 ` [PATCH 1/3] dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible Alexandru Chimac 2025-09-14 19:34 ` [PATCH 2/3] dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node Alexandru Chimac @ 2025-09-14 19:34 ` Alexandru Chimac 2025-10-10 12:30 ` Krzysztof Kozlowski 2 siblings, 1 reply; 8+ messages in thread From: Alexandru Chimac @ 2025-09-14 19:34 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Alim Akhtar, Linus Walleij, Rob Herring, Conor Dooley, Tomasz Figa Cc: linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree, linux-kernel, Alexandru Chimac Add pinctrl configuration for Exynos9610. The bank types used are the same as on Exynos850, so we can reuse the macros. Signed-off-by: Alexandru Chimac <alex@chimac.ro> --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 109 +++++++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 112 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 5fe7c4b9f7bd424f396082f1b1b16bfb65f26cdf..a100962c51c28e2422c61a67d20faf03486f4f70 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1604,6 +1604,115 @@ const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { .num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl), }; +/* pin banks of exynos9610 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynos9610_pin_banks0[] = { + EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc0"), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTN(5, 0x080, "gpq0"), +}; + +/* pin banks of exynos9610 pin-controller 1 (CMGP) */ +static struct samsung_pin_bank_data exynos9610_pin_banks1[] = { + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20), + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24), + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28), + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2C), + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30), + EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x34), + EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x38), + EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x3C), + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40), + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44), + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48), + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4C), + EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50), + EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x54), + EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x58), + EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x5C), + EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x60), + EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x64), +}; + +/* pin banks of exynos9610 pin-controller 2 (DISPAUD) */ +static struct samsung_pin_bank_data exynos9610_pin_banks2[] = { + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04), + EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08), +}; + +/* pin banks of exynos9610 pin-controller 3 (FSYS) */ +static struct samsung_pin_bank_data exynos9610_pin_banks3[] = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), + EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf2", 0x08), +}; + +/* pin banks of exynos9610 pin-controller 4 (TOP) */ +static struct samsung_pin_bank_data exynos9610_pin_banks4[] = { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), + EXYNOS850_PIN_BANK_EINTG(5, 0x0A0, "gpc2", 0x14), + EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg0", 0x18), + EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpg1", 0x1C), + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpg2", 0x20), + EXYNOS850_PIN_BANK_EINTG(6, 0x120, "gpg3", 0x24), + EXYNOS850_PIN_BANK_EINTG(3, 0x140, "gpg4", 0x28), +}; + +/* pin banks of exynos9610 pin-controller 5 (SHUB) */ +static struct samsung_pin_bank_data exynos9610_pin_banks5[] = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gph0", 0x00), + EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gph1", 0x04), +}; + +static const struct samsung_pin_ctrl exynos9610_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos9610_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos9610_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks1), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 DISPAUD data */ + .pin_banks = exynos9610_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks2), + }, { + /* pin-controller instance 3 FSYS data */ + .pin_banks = exynos9610_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks3), + }, { + /* pin-controller instance 4 TOP data */ + .pin_banks = exynos9610_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks4), + }, { + /* pin-controller instance 5 SHUB data */ + .pin_banks = exynos9610_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks5), + }, +}; + +const struct samsung_pinctrl_of_match_data exynos9610_of_data __initconst = { + .ctrl = exynos9610_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos9610_pin_ctrl), +}; + /* * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three * gpio/pin-mux/pinconfig controllers. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 24745e1d78cec59c932ed57fdb8ca85410376ff7..2036212bf3d079cc61f1827847a37025c12e0961 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1498,6 +1498,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos850_of_data }, { .compatible = "samsung,exynos8895-pinctrl", .data = &exynos8895_of_data }, + { .compatible = "samsung,exynos9610-pinctrl", + .data = &exynos9610_of_data }, { .compatible = "samsung,exynos9810-pinctrl", .data = &exynos9810_of_data }, { .compatible = "samsung,exynos990-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 1cabcbe1401a614ea33803132db776e97c1d56ee..c711580a8729d05edf5057e0c0a7fed65d692c43 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -395,6 +395,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7870_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; +extern const struct samsung_pinctrl_of_match_data exynos9610_of_data; extern const struct samsung_pinctrl_of_match_data exynos9810_of_data; extern const struct samsung_pinctrl_of_match_data exynos990_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; -- 2.47.3 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration 2025-09-14 19:34 ` [PATCH 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration Alexandru Chimac @ 2025-10-10 12:30 ` Krzysztof Kozlowski 0 siblings, 0 replies; 8+ messages in thread From: Krzysztof Kozlowski @ 2025-10-10 12:30 UTC (permalink / raw) To: Alexandru Chimac, Sylwester Nawrocki, Alim Akhtar, Linus Walleij, Rob Herring, Conor Dooley, Tomasz Figa Cc: linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree, linux-kernel On 14/09/2025 21:34, Alexandru Chimac wrote: > Add pinctrl configuration for Exynos9610. The bank types > used are the same as on Exynos850, so we can reuse the macros. > > Signed-off-by: Alexandru Chimac <alex@chimac.ro> > --- > drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 109 +++++++++++++++++++++++++ > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + > 3 files changed, 112 insertions(+) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > index 5fe7c4b9f7bd424f396082f1b1b16bfb65f26cdf..a100962c51c28e2422c61a67d20faf03486f4f70 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > @@ -1604,6 +1604,115 @@ const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { > .num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl), > }; > > +/* pin banks of exynos9610 pin-controller 0 (ALIVE) */ > +static struct samsung_pin_bank_data exynos9610_pin_banks0[] = { Please use upstream as your starting point, not downstream. Missing const. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 0/3] pinctrl: samsung: add Exynos9610 pinctrl support
@ 2025-09-14 19:31 Alexandru Chimac
2025-09-14 19:32 ` [PATCH 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration Alexandru Chimac
0 siblings, 1 reply; 8+ messages in thread
From: Alexandru Chimac @ 2025-09-14 19:31 UTC (permalink / raw)
Cc: linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree,
linux-kernel, Alexandru Chimac
This patchset adds support for the pin controller found on Exynos9610.
Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
Alexandru Chimac (3):
dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible
dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node
pinctrl: samsung: Add Exynos9610 pinctrl configuration
.../pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 +
.../bindings/pinctrl/samsung,pinctrl.yaml | 1 +
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 109 +++++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
5 files changed, 115 insertions(+)
---
base-commit: 48c4c0b684f394721b7db809e1cc282fccdb33da
change-id: 20250914-exynos9610-pinctrl-b44cdfaeeed1
Best regards,
--
Alexandru Chimac <alex@chimac.ro>
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration 2025-09-14 19:31 [PATCH 0/3] pinctrl: samsung: add Exynos9610 pinctrl support Alexandru Chimac @ 2025-09-14 19:32 ` Alexandru Chimac 0 siblings, 0 replies; 8+ messages in thread From: Alexandru Chimac @ 2025-09-14 19:32 UTC (permalink / raw) Cc: linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree, linux-kernel, Alexandru Chimac Add pinctrl configuration for Exynos9610. The bank types used are the same as on Exynos850, so we can reuse the macros. Signed-off-by: Alexandru Chimac <alex@chimac.ro> --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 109 +++++++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 112 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 5fe7c4b9f7bd424f396082f1b1b16bfb65f26cdf..a100962c51c28e2422c61a67d20faf03486f4f70 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1604,6 +1604,115 @@ const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { .num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl), }; +/* pin banks of exynos9610 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynos9610_pin_banks0[] = { + EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc0"), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTN(5, 0x080, "gpq0"), +}; + +/* pin banks of exynos9610 pin-controller 1 (CMGP) */ +static struct samsung_pin_bank_data exynos9610_pin_banks1[] = { + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20), + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24), + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28), + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2C), + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30), + EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x34), + EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x38), + EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x3C), + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40), + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44), + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48), + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4C), + EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50), + EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x54), + EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x58), + EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x5C), + EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x60), + EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x64), +}; + +/* pin banks of exynos9610 pin-controller 2 (DISPAUD) */ +static struct samsung_pin_bank_data exynos9610_pin_banks2[] = { + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04), + EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08), +}; + +/* pin banks of exynos9610 pin-controller 3 (FSYS) */ +static struct samsung_pin_bank_data exynos9610_pin_banks3[] = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), + EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf2", 0x08), +}; + +/* pin banks of exynos9610 pin-controller 4 (TOP) */ +static struct samsung_pin_bank_data exynos9610_pin_banks4[] = { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), + EXYNOS850_PIN_BANK_EINTG(5, 0x0A0, "gpc2", 0x14), + EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg0", 0x18), + EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpg1", 0x1C), + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpg2", 0x20), + EXYNOS850_PIN_BANK_EINTG(6, 0x120, "gpg3", 0x24), + EXYNOS850_PIN_BANK_EINTG(3, 0x140, "gpg4", 0x28), +}; + +/* pin banks of exynos9610 pin-controller 5 (SHUB) */ +static struct samsung_pin_bank_data exynos9610_pin_banks5[] = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gph0", 0x00), + EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gph1", 0x04), +}; + +static const struct samsung_pin_ctrl exynos9610_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos9610_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos9610_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks1), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 DISPAUD data */ + .pin_banks = exynos9610_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks2), + }, { + /* pin-controller instance 3 FSYS data */ + .pin_banks = exynos9610_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks3), + }, { + /* pin-controller instance 4 TOP data */ + .pin_banks = exynos9610_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks4), + }, { + /* pin-controller instance 5 SHUB data */ + .pin_banks = exynos9610_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks5), + }, +}; + +const struct samsung_pinctrl_of_match_data exynos9610_of_data __initconst = { + .ctrl = exynos9610_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos9610_pin_ctrl), +}; + /* * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three * gpio/pin-mux/pinconfig controllers. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 24745e1d78cec59c932ed57fdb8ca85410376ff7..2036212bf3d079cc61f1827847a37025c12e0961 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1498,6 +1498,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos850_of_data }, { .compatible = "samsung,exynos8895-pinctrl", .data = &exynos8895_of_data }, + { .compatible = "samsung,exynos9610-pinctrl", + .data = &exynos9610_of_data }, { .compatible = "samsung,exynos9810-pinctrl", .data = &exynos9810_of_data }, { .compatible = "samsung,exynos990-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 1cabcbe1401a614ea33803132db776e97c1d56ee..c711580a8729d05edf5057e0c0a7fed65d692c43 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -395,6 +395,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7870_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; +extern const struct samsung_pinctrl_of_match_data exynos9610_of_data; extern const struct samsung_pinctrl_of_match_data exynos9810_of_data; extern const struct samsung_pinctrl_of_match_data exynos990_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; -- 2.47.3 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-10-10 12:30 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-09-14 19:34 [PATCH 0/3] pinctrl: samsung: add Exynos9610 pinctrl support Alexandru Chimac 2025-09-14 19:34 ` [PATCH 1/3] dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible Alexandru Chimac 2025-09-22 15:42 ` Rob Herring (Arm) 2025-09-14 19:34 ` [PATCH 2/3] dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node Alexandru Chimac 2025-09-22 15:42 ` Rob Herring (Arm) 2025-09-14 19:34 ` [PATCH 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration Alexandru Chimac 2025-10-10 12:30 ` Krzysztof Kozlowski -- strict thread matches above, loose matches on Subject: below -- 2025-09-14 19:31 [PATCH 0/3] pinctrl: samsung: add Exynos9610 pinctrl support Alexandru Chimac 2025-09-14 19:32 ` [PATCH 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration Alexandru Chimac
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