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([2a02:810b:f40:4300:55ff:210b:5393:c9d7]) by smtp.gmail.com with ESMTPSA id s7-20020a170906bc4700b00a0f78db91c3sm5416316ejv.95.2023.12.04.07.23.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Dec 2023 07:23:27 -0800 (PST) Message-ID: Date: Mon, 4 Dec 2023 16:23:26 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128 To: =?UTF-8?Q?Heiko_St=C3=BCbner?= , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: Daniel Vetter , David Airlie , Thomas Zimmermann , Maxime Ripard , Maarten Lankhorst , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org References: <20231202125144.66052-1-knaerzche@gmail.com> <4891026.6YUMPnJmAY@diego> <4dec2316-f840-44ab-a07a-3d7f0e5e6d8f@gmail.com> <9588573.jRhZ6ZUK3Y@diego> Content-Language: en-US From: Alex Bee In-Reply-To: <9588573.jRhZ6ZUK3Y@diego> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Heiko, Am 03.12.23 um 17:42 schrieb Heiko Stübner: > Hi Alex, > > Am Sonntag, 3. Dezember 2023, 17:05:47 CET schrieb Alex Bee: >> Am 02.12.23 um 18:46 schrieb Heiko Stübner: >>> Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee: >>>> Am 02.12.23 um 16:51 schrieb Heiko Stübner: >>>>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee: >>>>>> Add power controller and qos nodes for RK3128 in order to use >>>>>> them as powerdomains. >>>>> does the power-domain controller work with the incomplete set of >>>>> pm-domains too? >>>> Yes, it does - the missing domains can request idle only and can't be >>>> powered on/off - if no one requests idle they are just up all the time. >>>> >>>>> What I have in mind is >>>>> - adding the power-controller node with the existing set of power-domains >>>>> - the gpu pm-domain is in there >>>>> - adding the gpu parts >>>> My main concern about adding them later was the change of the ABI after >>>> they've been exposed in the SoC DT. If that's not an issue - sure: I can >>>> add them in a separate series. >>> An ABI change would be _changing_ the domain-ids in the rk3128-power.h >>> I think :-) . >> Well, an addition is still a change. >>> Right now the existing domain ids in the header are already exposed to the >>> world, so someone could already use them, but not the new ones. >> I'm fully aware that nothing would ever hard fail anywhere if the new >> domain ids get added later. >> >> Nevertheless we start using here an ABI which is known to be incomplete. >> For no reason, as the patches (which I am now asked to remove from this >> series) for completion are already there (here). >> >> Anyway, if you prefer it this way: I'm pleased to do so. > I was more thinking of accelerating the gpu-part of the series, as that > really is just waiting for the power-domain node that already has driver > support and domain-ids present. > > It looks like you're feeling more strongly about that though, so I'll > definitly not pressure you ;-) . I'm really not insisting on this - I just didn't understand why you would want this. And honestly I haven't considered merging timeline as an argument. So sure: Let's get the low hanging fruits merged for 6.8. Having the power domains in the DT will also help for my upcoming hdmi / vop series. Alex > > But I guess the split into IDs and driver change should still be > done, especially as the dt-binding-header likely will want an Ack > from the DT maintainers. > > And the power-domain change will go through the new pmdomain > subsystem. > > > Heiko > > >>>>> And a second series with >>>>> - patch1 from here >>>>> - a dts patch adding the additional pm-domains to rk3128.dtsi >>>>> - I guess patch1 also should be split into a patch adding the binding-ids >>>>> and a separate patch for the code addition. >>>> Yeah, I noticed this also :) >>>> >>>> Regards, >>>> >>>> Alex >>>> >>>>> Heiko >>>>> >>>>>> Signed-off-by: Alex Bee >>>>>> --- >>>>>> arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++ >>>>>> 1 file changed, 101 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi >>>>>> index 4e8b38604ecd..b72905db04f7 100644 >>>>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi >>>>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi >>>>>> @@ -8,6 +8,7 @@ >>>>>> #include >>>>>> #include >>>>>> #include >>>>>> +#include >>>>>> >>>>>> / { >>>>>> compatible = "rockchip,rk3128"; >>>>>> @@ -133,6 +134,106 @@ smp-sram@0 { >>>>>> pmu: syscon@100a0000 { >>>>>> compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; >>>>>> reg = <0x100a0000 0x1000>; >>>>>> + >>>>>> + power: power-controller { >>>>>> + compatible = "rockchip,rk3128-power-controller"; >>>>>> + #power-domain-cells = <1>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + >>>>>> + power-domain@RK3128_PD_VIO { >>>>>> + reg = ; >>>>>> + clocks = <&cru ACLK_CIF>, >>>>>> + <&cru HCLK_CIF>, >>>>>> + <&cru DCLK_EBC>, >>>>>> + <&cru HCLK_EBC>, >>>>>> + <&cru ACLK_IEP>, >>>>>> + <&cru HCLK_IEP>, >>>>>> + <&cru ACLK_LCDC0>, >>>>>> + <&cru HCLK_LCDC0>, >>>>>> + <&cru PCLK_MIPI>, >>>>>> + <&cru ACLK_RGA>, >>>>>> + <&cru HCLK_RGA>, >>>>>> + <&cru ACLK_VIO0>, >>>>>> + <&cru ACLK_VIO1>, >>>>>> + <&cru HCLK_VIO>, >>>>>> + <&cru HCLK_VIO_H2P>, >>>>>> + <&cru DCLK_VOP>, >>>>>> + <&cru SCLK_VOP>; >>>>>> + pm_qos = <&qos_ebc>, >>>>>> + <&qos_iep>, >>>>>> + <&qos_lcdc>, >>>>>> + <&qos_rga>, >>>>>> + <&qos_vip>; >>>>>> + #power-domain-cells = <0>; >>>>>> + }; >>>>>> + >>>>>> + power-domain@RK3128_PD_VIDEO { >>>>>> + reg = ; >>>>>> + clocks = <&cru ACLK_VDPU>, >>>>>> + <&cru HCLK_VDPU>, >>>>>> + <&cru ACLK_VEPU>, >>>>>> + <&cru HCLK_VEPU>, >>>>>> + <&cru SCLK_HEVC_CORE>; >>>>>> + pm_qos = <&qos_vpu>; >>>>>> + #power-domain-cells = <0>; >>>>>> + }; >>>>>> + >>>>>> + power-domain@RK3128_PD_GPU { >>>>>> + reg = ; >>>>>> + clocks = <&cru ACLK_GPU>; >>>>>> + pm_qos = <&qos_gpu>; >>>>>> + #power-domain-cells = <0>; >>>>>> + }; >>>>>> + >>>>>> + power-domain@RK3128_PD_CRYPTO { >>>>>> + reg = ; >>>>>> + clocks = <&cru HCLK_CRYPTO>, >>>>>> + <&cru SCLK_CRYPTO>; >>>>>> + pm_qos = <&qos_crypto>; >>>>>> + #power-domain-cells = <0>; >>>>>> + }; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + qos_crypto: qos@10128080 { >>>>>> + compatible = "rockchip,rk3128-qos", "syscon"; >>>>>> + reg = <0x10128080 0x20>; >>>>>> + }; >>>>>> + >>>>>> + qos_gpu: qos@1012d000 { >>>>>> + compatible = "rockchip,rk3128-qos", "syscon"; >>>>>> + reg = <0x1012d000 0x20>; >>>>>> + }; >>>>>> + >>>>>> + qos_vpu: qos@1012e000 { >>>>>> + compatible = "rockchip,rk3128-qos", "syscon"; >>>>>> + reg = <0x1012e000 0x20>; >>>>>> + }; >>>>>> + >>>>>> + qos_rga: qos@1012f000 { >>>>>> + compatible = "rockchip,rk3128-qos", "syscon"; >>>>>> + reg = <0x1012f000 0x20>; >>>>>> + }; >>>>>> + >>>>>> + qos_ebc: qos@1012f080 { >>>>>> + compatible = "rockchip,rk3128-qos", "syscon"; >>>>>> + reg = <0x1012f080 0x20>; >>>>>> + }; >>>>>> + >>>>>> + qos_iep: qos@1012f100 { >>>>>> + compatible = "rockchip,rk3128-qos", "syscon"; >>>>>> + reg = <0x1012f100 0x20>; >>>>>> + }; >>>>>> + >>>>>> + qos_lcdc: qos@1012f180 { >>>>>> + compatible = "rockchip,rk3128-qos", "syscon"; >>>>>> + reg = <0x1012f180 0x20>; >>>>>> + }; >>>>>> + >>>>>> + qos_vip: qos@1012f200 { >>>>>> + compatible = "rockchip,rk3128-qos", "syscon"; >>>>>> + reg = <0x1012f200 0x20>; >>>>>> }; >>>>>> >>>>>> gic: interrupt-controller@10139000 { >>>>>> >>>>> >>> >>> > > >