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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id gz15-20020a170906f2cf00b006f3802a963fsm52298ejb.21.2022.04.23.03.28.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 23 Apr 2022 03:28:34 -0700 (PDT) Message-ID: Date: Sat, 23 Apr 2022 12:28:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit Content-Language: en-US To: Rex-BC Chen , mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: p.zabel@pengutronix.de, angelogioacchino.delregno@collabora.com, chun-jie.chen@mediatek.com, wenst@chromium.org, runyang.chen@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20220422060152.13534-1-rex-bc.chen@mediatek.com> <20220422060152.13534-13-rex-bc.chen@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <20220422060152.13534-13-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 22/04/2022 08:01, Rex-BC Chen wrote: > To support reset of infra_ao, add the bit definition for thermal/PCIe/SVS. > > Signed-off-by: Rex-BC Chen > --- > include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h > index be9a7ca245b9..d5f3433175c1 100644 > --- a/include/dt-bindings/reset/mt8192-resets.h > +++ b/include/dt-bindings/reset/mt8192-resets.h > @@ -27,4 +27,14 @@ > > #define MT8192_TOPRGU_SW_RST_NUM 23 > > +/* INFRA RST0 */ > +#define MT8192_INFRA_RST0_LVTS_AP_RST 0 > +/* INFRA RST2 */ > +#define MT8192_INFRA_RST2_PCIE_PHY_RST 15 > +/* INFRA RST3 */ > +#define MT8192_INFRA_RST3_PTP_RST 5 > +/* INFRA RST4 */ > +#define MT8192_INFRA_RST4_LVTS_MCU 12 > +#define MT8192_INFRA_RST4_PCIE_TOP 1 These should be the IDs of reset, not some register values/offsets. Therefore it is expected to have them incremented by 1. > + > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ Best regards, Krzysztof