From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B23A3081D0; Tue, 28 Oct 2025 11:29:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761650988; cv=pass; b=SBhXhRccidzMz5jSa5GkWHFvJZYp8dU2iYwk3WzAPi+Eznat81JdmzmAC+i/GLlQQTwtqWbUFSwdYuSIXACZlsksKbv0vv9iXNnD8XeraAqKBQcN50OImukRbItbwYX4KGeYjBNInZFjQyu2+5m5b1VSQbLVSkLu9d5ex/hDHQ8= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761650988; c=relaxed/simple; bh=tYbeQ90vGGHXXE7MCg3eqhYlsB9W8v0Z3SOU4Enjgp4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=XaRm6YOtu1nBW8ZNpn/PQ+4xYwUGu5nlubo3T3DaM7CV07aJdGIDi/rq1VG1NuIxMJNyblieY0dnDiewr9I0y2SpuFcNZScVRo/n2jWos5f1TlEMGLg8mzAthNdn/7CTK+DZvX2zpcrE8u+6TmmQashI3+rCbVAIEXUCNdjFbUY= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=njF1zKZ/; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="njF1zKZ/" ARC-Seal: i=1; a=rsa-sha256; t=1761650958; cv=none; d=zohomail.com; s=zohoarc; b=OPE5nDWfuugw1kKa6IcPSetaU8VLCXsoaM0Nn5DkvqFPMPAtCpyRR74CKCvp8fgDrbw03ZqetOY2b58Bha7NWrdpabp+hq08LOC1lmHwhRSWOS6wlcrFbnJds11Xf4yLCMa7oe+aRw2gC1FZtUsCVunrhmyG6A3MWg321jayJrk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761650958; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=htCIUeie1Fllw0gMKXGW6GDJsuGaHCRZYsDOba4fJdw=; b=leSEemltU/maU1r+O9yiGVP2P+FEnVzaaExpVFmnPiimQwOvEUCH4NyS4TKf04DShFVxd3dXUgZLI7YlDzBBSUwJs0eAFMYZZR5znF/caGAnK3TWtzJVzi/FYnFDsgw6XXpTnTPcNwqryZqsg/7AnUp9w8Xd25liHtm9HHUeEPo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1761650958; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=Message-ID:Date:Date:MIME-Version:Subject:Subject:To:To:Cc:Cc:References:From:From:In-Reply-To:Content-Type:Content-Transfer-Encoding:Message-Id:Reply-To; bh=htCIUeie1Fllw0gMKXGW6GDJsuGaHCRZYsDOba4fJdw=; b=njF1zKZ/WbjS+4NeXpMU3JLnnb5YjV33OKRR0aHXNhR7Jcwqy0kdZzM/JEXoeWlU ZXYj5TwdKFdb/ALbBzm3sGGOLbFJDdp6qQsqwvO3yuoa7Mbt1j6PoZgPYh1hF31oXew mEHjaI416JMXgTPtRsi4dT4ijkPqBbzoflyteJ64= Received: by mx.zohomail.com with SMTPS id 1761650955763658.116487530986; Tue, 28 Oct 2025 04:29:15 -0700 (PDT) Message-ID: Date: Tue, 28 Oct 2025 19:29:05 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/6] reset: anlogic: add support for Anlogic DR1V90 resets To: Philipp Zabel , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org References: <20251026-dr1v90-cru-v2-0-43b67acd6ddd@pigmoral.tech> <20251026-dr1v90-cru-v2-4-43b67acd6ddd@pigmoral.tech> <36d28431c41ec9ed86487135d81e50b136ee0fae.camel@pengutronix.de> From: Junhui Liu In-Reply-To: <36d28431c41ec9ed86487135d81e50b136ee0fae.camel@pengutronix.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ZohoMailClient: External Hi Philipp, Thanks for your review. On 10/28/25 4:17 PM, Philipp Zabel wrote: > On So, 2025-10-26 at 22:00 +0800, Junhui Liu wrote: >> Add reset controller support for the Anlogic DR1V90 SoC, which is an >> auxiliary device associated with the Clock and Reset Unit (CRU). All >> resets are active-low. >> >> Signed-off-by: Junhui Liu >> --- >> drivers/reset/Kconfig | 9 +++ >> drivers/reset/Makefile | 1 + >> drivers/reset/reset-dr1v90.c | 135 +++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 145 insertions(+) >> > [...] >> diff --git a/drivers/reset/reset-dr1v90.c b/drivers/reset/reset-dr1v90.c >> new file mode 100644 >> index 0000000000000000000000000000000000000000..eb9064e3ab454fb39adc1ad426f458e39bb6169e >> --- /dev/null >> +++ b/drivers/reset/reset-dr1v90.c >> @@ -0,0 +1,135 @@ > [...] >> +static const struct dr1v90_reset_map dr1v90_resets[] = { >> + [RESET_OCM] = { 0x74, BIT(4)}, > [...] >> + [RESET_NIC_HP0] = { 0x78, BIT(0)}, > [...] >> + [RESET_USB0] = { 0x7C, BIT(0)}, > The registers 0x74, 0x78, and 0x7C are exclusively used for resets? Yes, these three registers only contain bits for resets according to the register list doc. > > [...] >> +}; >> + >> +static int dr1v90_reset_control_update(struct reset_controller_dev *rcdev, >> + unsigned long id, bool assert) >> +{ >> + struct dr1v90_reset_controller *rstc = to_dr1v90_reset_controller(rcdev); >> + u32 offset = dr1v90_resets[id].offset; >> + u32 bit = dr1v90_resets[id].bit; >> + u32 reg; >> + >> + reg = readl(rstc->base + offset); >> + if (assert) >> + reg &= ~bit; >> + else >> + reg |= bit; >> + writel(reg, rstc->base + offset); > There should be a lock around this read-modify-write access. Okay, I will add a lock in the next version. > > regards > Philipp -- Best regards, Junhui Liu