From: Jagadeesh Kona <quic_jkona@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Brian Masney <bmasney@redhat.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
<linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Ajit Pandey <quic_ajipan@quicinc.com>,
"Imran Shaik" <quic_imrashai@quicinc.com>,
Taniya Das <quic_tdas@quicinc.com>,
"Satya Priya Kakitapalli" <quic_skakitap@quicinc.com>,
Shivnandan Kumar <quic_kshivnan@quicinc.com>
Subject: Re: [PATCH 2/3] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
Date: Tue, 3 Dec 2024 20:33:21 +0530 [thread overview]
Message-ID: <e6c17b91-e771-480e-b46d-f11c167a96bf@quicinc.com> (raw)
In-Reply-To: <daqa3krsp6emdha6h7tlcelsggb6qeilnojgtfxjbp5zw4n6ow@xzwdmu55ygjf>
On 11/15/2024 4:18 AM, Dmitry Baryshkov wrote:
> On Mon, Nov 11, 2024 at 06:39:48PM +0530, Jagadeesh Kona wrote:
>>
>>
>> On 10/17/2024 9:12 PM, Brian Masney wrote:
>>> On Thu, Oct 17, 2024 at 02:58:31PM +0530, Jagadeesh Kona wrote:
>>>> + cpu0_opp_table: opp-table-cpu0 {
>>>> + compatible = "operating-points-v2";
>>>> + opp-shared;
>>>> +
>>>> + cpu0_opp_1267mhz: opp-1267200000 {
>>>> + opp-hz = /bits/ 64 <1267200000>;
>>>> + opp-peak-kBps = <6220800 29491200>;
>>>> + };
>>>> +
>>>> + cpu0_opp_1363mhz: opp-1363200000 {
>>>> + opp-hz = /bits/ 64 <1363200000>;
>>>> + opp-peak-kBps = <6220800 29491200>;
>>>> + };
>>>
>>> [snip]
>>>
>>>> + cpu4_opp_table: opp-table-cpu4 {
>>>> + compatible = "operating-points-v2";
>>>> + opp-shared;
>>>> +
>>>> + cpu4_opp_1267mhz: opp-1267200000 {
>>>> + opp-hz = /bits/ 64 <1267200000>;
>>>> + opp-peak-kBps = <6220800 29491200>;
>>>> + };
>>>> +
>>>> + cpu4_opp_1363mhz: opp-1363200000 {
>>>> + opp-hz = /bits/ 64 <1363200000>;
>>>> + opp-peak-kBps = <6220800 29491200>;
>>>> + };
>>>
>>> There's no functional differences in the cpu0 and cpu4 opp tables. Can
>>> a single table be used?
>>>
>>> This aligns with my recollection that this particular SoC only has the
>>> gold cores.
>>>
>>> Brian
>>>
>>
>> Thanks Brian for your review. Sorry for the delayed response.
>>
>> We require separate OPP tables for CPU0 and CPU4 to allow independent
>> scaling of DDR and L3 frequencies for each CPU domain, with the final
>> DDR and L3 frequencies being an aggregate of both.
>>
>> If we use a single OPP table for both CPU domains, then _allocate_opp_table() [1]
>> won't be invoked for CPU4. As a result both CPU devices will end up in sharing
>> the same ICC path handle, which could lead to one CPU device overwriting the bandwidth
>> votes of other.
>
> All of this should be a part of the commit message.
>
Thanks Dmitry for your review. Will include this in commit text while posting the next series.
Thanks,
Jagadeesh
>>
>> [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/opp/core.c#n1588
>>
>> Thanks,
>> Jagadeesh
>>
>
next prev parent reply other threads:[~2024-12-03 15:03 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-17 9:28 [PATCH 0/3] Add support to scale DDR and L3 on SA8775P Jagadeesh Kona
2024-10-17 9:28 ` [PATCH 1/3] arm64: dts: qcom: sa8775p: Add support to scale DDR/L3 Jagadeesh Kona
2024-10-17 22:52 ` Konrad Dybcio
2024-11-11 13:10 ` Jagadeesh Kona
2024-10-17 9:28 ` [PATCH 2/3] arm64: dts: qcom: sa8775p: Add CPU OPP tables " Jagadeesh Kona
2024-10-17 15:42 ` Brian Masney
2024-11-11 13:09 ` Jagadeesh Kona
2024-11-14 22:48 ` Dmitry Baryshkov
2024-11-30 14:32 ` Konrad Dybcio
2024-12-03 15:03 ` Jagadeesh Kona
2024-12-04 3:13 ` Dmitry Baryshkov
2024-12-04 8:45 ` Jagadeesh Kona
2024-12-04 11:00 ` Dmitry Baryshkov
2024-12-03 15:03 ` Jagadeesh Kona [this message]
2024-10-17 9:28 ` [PATCH 3/3] arm64: dts: qcom: sa8775p: Add LMH interrupts support Jagadeesh Kona
2024-10-26 12:27 ` Konrad Dybcio
2024-11-11 13:10 ` Jagadeesh Kona
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