From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F226FC433FE for ; Fri, 15 Oct 2021 19:04:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D962961041 for ; Fri, 15 Oct 2021 19:04:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241555AbhJOTGM (ORCPT ); Fri, 15 Oct 2021 15:06:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238254AbhJOTGM (ORCPT ); Fri, 15 Oct 2021 15:06:12 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEC49C061570 for ; Fri, 15 Oct 2021 12:04:05 -0700 (PDT) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=[IPv6:::1]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mbSUn-0005uk-1l; Fri, 15 Oct 2021 21:03:57 +0200 Message-ID: Subject: Re: [PATCH v3 8/9] arm64: dts: imx8mm-evk: add the pcie support on imx8mm evk board From: Lucas Stach To: Richard Zhu , tharvey@gateworks.com, kishon@ti.com, vkoul@kernel.org, robh@kernel.org, galak@kernel.crashing.org, shawnguo@kernel.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Date: Fri, 15 Oct 2021 21:03:55 +0200 In-Reply-To: <1634028078-2387-9-git-send-email-hongxing.zhu@nxp.com> References: <1634028078-2387-1-git-send-email-hongxing.zhu@nxp.com> <1634028078-2387-9-git-send-email-hongxing.zhu@nxp.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 (3.40.4-1.fc34) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Am Dienstag, dem 12.10.2021 um 16:41 +0800 schrieb Richard Zhu: > Add the PCIe support on i.MX8MM EVK board. > > Signed-off-by: Richard Zhu > --- > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > index 2d0684ac82f6..5ce43daa0c8b 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > @@ -31,6 +31,23 @@ status { > }; > }; > > + pcie0_refclk: pcie0-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + }; This is both the PHY reference and bus clock. I guess you could just squash Patch 4/9 into this one, as they are both required to get PCIe on the EVK board. > + > + reg_pcie0_gpio: regulator-pcie-gpio { Drop the gpio suffix. > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0_reg>; > + regulator-name = "MPCIE_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > reg_usdhc2_vmmc: regulator-usdhc2 { > compatible = "regulator-fixed"; > pinctrl-names = "default"; > @@ -296,6 +313,22 @@ &pcie_phy { > status = "okay"; > }; > > +&pcie0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0>; > + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; > + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, > + <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>; The i.MX8MM PCIe driver should not request the pcie_phy clock. Please add a change in the driver, so we don't need to hook up a useless dummy clock to this node. Regards, Lucas > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; > + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, > + <&clk IMX8MM_CLK_PCIE1_CTRL>; > + assigned-clock-rates = <10000000>, <250000000>; > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, > + <&clk IMX8MM_SYS_PLL2_250M>; > + vpcie-supply = <®_pcie0_gpio>; > + status = "okay"; > +}; > + > &sai3 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_sai3>; > @@ -413,6 +446,19 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 > >; > }; > > + pinctrl_pcie0: pcie0grp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 > + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 > + >; > + }; > + > + pinctrl_pcie0_reg: pcie0reggrp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 > + >; > + }; > + > pinctrl_pmic: pmicirqgrp { > fsl,pins = < > MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141