From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F151C2D0A3 for ; Thu, 12 Nov 2020 15:59:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2B17F22227 for ; Thu, 12 Nov 2020 15:59:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="In6V1hrw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728897AbgKLP6c (ORCPT ); Thu, 12 Nov 2020 10:58:32 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53998 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728883AbgKLP6b (ORCPT ); Thu, 12 Nov 2020 10:58:31 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0ACFwP2p010590; Thu, 12 Nov 2020 09:58:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1605196705; bh=5EME1Y5wxtn8yJOfd69sUQV7FxdOrY9kzzIdVjXXO1M=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=In6V1hrwcRwcNLW/ydQ6LG1p7Cqb58kedqGtYRW7eGhLK+1r2x2fu72dvXyZNVUrb HZVDe8B+d3iuOYQz8UN8BTdgnXmVugk4BwA5OcoXoCiiPQBjUeg7DixnCglgs+Odzg ja4GTOdrpA13ammWra26o+mzedyH9sAzVszVZdq8= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0ACFwP1i072911 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Nov 2020 09:58:25 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 12 Nov 2020 09:58:25 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 12 Nov 2020 09:58:25 -0600 Received: from [10.250.233.179] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0ACFwLbH004118; Thu, 12 Nov 2020 09:58:22 -0600 Subject: Re: [PATCH v2 6/7] arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0 To: Kishon Vijay Abraham I , Tero Kristo , Nishanth Menon , Rob Herring , Roger Quadros , Lee Jones CC: , , , Bjorn Helgaas , References: <20201109170409.4498-1-kishon@ti.com> <20201109170409.4498-7-kishon@ti.com> From: Vignesh Raghavendra Message-ID: Date: Thu, 12 Nov 2020 21:28:21 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201109170409.4498-7-kishon@ti.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11/9/20 10:34 PM, Kishon Vijay Abraham I wrote: > Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected > to PCIe and QSGMII (multi-link SERDES). > > Signed-off-by: Kishon Vijay Abraham I > --- > .../dts/ti/k3-j7200-common-proc-board.dts | 23 +++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > index ef03e7636b66..65a2e5aeb050 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > @@ -8,6 +8,7 @@ > #include "k3-j7200-som-p0.dtsi" > #include > #include > +#include > > / { > chosen { > @@ -213,3 +214,25 @@ > dr_mode = "otg"; > maximum-speed = "high-speed"; > }; > + > +&serdes_refclk { > + clock-frequency = <100000000>; > +}; Since this is a reference clk from the board, should the entire node be here instead of in k3-j7200-main.dtsi? > + > +&serdes0 { > + serdes0_pcie_link: phy@0 { > + reg = <0>; > + cdns,num-lanes = <2>; > + #phy-cells = <0>; > + cdns,phy-type = ; > + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; > + }; > + > + serdes0_qsgmii_link: phy@1 { > + reg = <2>; > + cdns,num-lanes = <1>; > + #phy-cells = <0>; > + cdns,phy-type = ; > + resets = <&serdes_wiz0 3>; > + }; > +}; >