From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10E14C7EE24 for ; Fri, 2 Jun 2023 09:00:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234454AbjFBJA3 (ORCPT ); Fri, 2 Jun 2023 05:00:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234265AbjFBJAW (ORCPT ); Fri, 2 Jun 2023 05:00:22 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8FE78133; Fri, 2 Jun 2023 02:00:20 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B46E1063; Fri, 2 Jun 2023 02:01:05 -0700 (PDT) Received: from [10.57.22.125] (unknown [10.57.22.125]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7BD903F663; Fri, 2 Jun 2023 02:00:17 -0700 (PDT) Message-ID: Date: Fri, 2 Jun 2023 10:00:16 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.11.1 Subject: Re: [PATCH v4 07/11] coresight-tpdm: Add nodes for dsb edge control From: Suzuki K Poulose To: Tao Zhang , Mathieu Poirier , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski Cc: Jinlong Mao , Leo Yan , Greg Kroah-Hartman , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , linux-arm-msm@vger.kernel.org, andersson@kernel.org References: <1682586037-25973-1-git-send-email-quic_taozha@quicinc.com> <1682586037-25973-8-git-send-email-quic_taozha@quicinc.com> <606b8a25-0468-c310-ccff-1477e2b238b2@arm.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 02/06/2023 09:45, Suzuki K Poulose wrote: > On 02/06/2023 09:21, Tao Zhang wrote: >> >> On 6/1/2023 8:14 PM, Suzuki K Poulose wrote: >>> On 27/04/2023 10:00, Tao Zhang wrote: >>>> Add the nodes to set value for DSB edge control and DSB edge >>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR >>>> resgisters to configure edge control. DSB edge detection control >>>> 00: Rising edge detection >>>> 01: Falling edge detection >>>> 10: Rising and falling edge detection (toggle detection) >>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to >>>> configure mask. Eight 32 bit registers providing DSB interface >>>> edge detection mask control. >>>> >>>> Signed-off-by: Tao Zhang >>>> --- >>>>   .../ABI/testing/sysfs-bus-coresight-devices-tpdm   |  32 +++++ >>>>   drivers/hwtracing/coresight/coresight-tpdm.c       | 135 >>>> ++++++++++++++++++++- >>>>   drivers/hwtracing/coresight/coresight-tpdm.h       |  21 ++++ >>>>   3 files changed, 187 insertions(+), 1 deletion(-) >>>> >>>> diff --git >>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> index 348e167..a57f000 100644 >>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> @@ -60,3 +60,35 @@ Description: >>>>           Bit[3] : Set to 0 for low performance mode. >>>>                    Set to 1 for high performance mode. >>>>           Bit[4:8] : Select byte lane for high performance mode. >>>> + >>>> +What: /sys/bus/coresight/devices//dsb_edge_ctrl >>>> +Date:        March 2023 >>>> +KernelVersion    6.3 >>>> +Contact:    Jinlong Mao (QUIC) , Tao >>>> Zhang (QUIC) >>>> +Description: >>>> +        Read/Write a set of the edge control registers of the DSB >>>> +        in TPDM. >>>> + >>>> +        Expected format is the following: >>>> +        >>>> + >>>> +        Where: >>>> +        : Start EDCR register number >>>> +        : End EDCR register number >>>> +        : The value need to be written >>>> + >>>> +What: /sys/bus/coresight/devices//dsb_edge_ctrl_mask >>>> +Date:        March 2023 >>>> +KernelVersion    6.3 >>>> +Contact:    Jinlong Mao (QUIC) , Tao >>>> Zhang (QUIC) >>>> +Description: >>>> +        Read/Write a set of the edge control mask registers of the >>>> +        DSB in TPDM. >>>> + >>>> +        Expected format is the following: >>>> +        >>>> + >>>> +        Where: >>>> +        : Start EDCMR register number >>>> +        : End EDCMR register number >>>> +        : The value need to be written >>>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c >>>> b/drivers/hwtracing/coresight/coresight-tpdm.c >>>> index 1bacaa5..a40e458 100644 >>>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c >>>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c >>>> @@ -80,7 +80,14 @@ static void set_trigger_type(struct tpdm_drvdata >>>> *drvdata, u32 *val) >>>>     static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) >>>>   { >>>> -    u32 val; >>>> +    u32 val, i; >>>> + >>>> +    for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) >>>> +        writel_relaxed(drvdata->dsb->edge_ctrl[i], >>>> +               drvdata->base + TPDM_DSB_EDCR(i)); >>>> +    for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) >>>> +        writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], >>>> +               drvdata->base + TPDM_DSB_EDCMR(i)); >>> >>> Do all TPDM DSBs have MAX_EDCR registers ? Or some have less than that ? >>> If it is latter, do we need special care to avoid writing to inexistent >>> registers ? >>> >> You are right, not all DSB TPDMs have MAX_EDCR registers. In our >> design, the inexistent register addresses >> >> are not occupied and safe for accessing. Does the TRM for the component say so ? Or is it by luck ? If the spec says it is RAZ/WriteIgnore, then we could keep the code as it is, with a comment. Otherwise, we could add a DT property. So please get this clarified with the H/W designers. Suzuki