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([2a02:810d:15c0:828:62f5:eb43:f726:5fee]) by smtp.gmail.com with ESMTPSA id c9-20020a056402100900b0050508605c1dsm7774156edu.37.2023.04.19.00.50.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Apr 2023 00:50:59 -0700 (PDT) Message-ID: Date: Wed, 19 Apr 2023 09:50:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v3 2/5] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Content-Language: en-US To: Jayesh Choudhary , nm@ti.com, vigneshr@ti.com, afd@ti.com Cc: s-vadapalli@ti.com, kristo@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, a-bhatia1@ti.com References: <20230419061710.290068-1-j-choudhary@ti.com> <20230419061710.290068-3-j-choudhary@ti.com> From: Krzysztof Kozlowski In-Reply-To: <20230419061710.290068-3-j-choudhary@ti.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19/04/2023 08:17, Jayesh Choudhary wrote: > From: Siddharth Vadapalli > > J784S4 SoC has a Main CPSW2G instance of the CPSW Ethernet Switch. > > Add the device-tree nodes for the Main CPSW2G instance and enable it. > > Signed-off-by: Siddharth Vadapalli > Signed-off-by: Jayesh Choudhary > --- > arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 48 +++++++++++++++ > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 68 ++++++++++++++++++++++ > 2 files changed, 116 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > index f33815953e77..aef6f53ae8ac 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > @@ -105,6 +105,30 @@ vdd_sd_dv: regulator-TLV71033 { > }; > > &main_pmx0 { > + main_cpsw2g_pins_default: main-cpsw2g-pins-default { > + pinctrl-single,pins = < > + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ > + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ > + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ > + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ > + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ > + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ > + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ > + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ > + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ > + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ > + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ > + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ > + >; > + }; > + > + main_cpsw2g_mdio_pins_default: main-cpsw2g-mdio-pins-default { > + pinctrl-single,pins = < > + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ > + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ > + >; > + }; > + > main_uart8_pins_default: main-uart8-pins-default { > pinctrl-single,pins = < > J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ > @@ -253,3 +277,27 @@ &mcu_cpsw_port1 { > phy-mode = "rgmii-rxid"; > phy-handle = <&mcu_phy0>; > }; > + > +&main_cpsw1 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&main_cpsw2g_pins_default>; > +}; > + > +&main_cpsw1_mdio { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_cpsw2g_mdio_pins_default>; > + > + main_phy0: ethernet-phy@0 { > + reg = <0>; > + ti,rx-internal-delay = ; > + ti,fifo-depth = ; > + ti,min-output-impedance; > + }; > +}; > + > +&main_cpsw1_port1 { > + status = "okay"; > + phy-mode = "rgmii-rxid"; > + phy-handle = <&main_phy0>; > +}; > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index 5fb7edf4f5a0..8bd8aebebe1c 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -36,6 +36,12 @@ scm_conf: syscon@100000 { > #size-cells = <1>; > ranges = <0x00 0x00 0x00100000 0x1c000>; > > + cpsw1_phy_gmii_sel: phy@4034 { > + compatible = "ti,am654-phy-gmii-sel"; > + reg = <0x4034 0x4>; > + #phy-cells = <1>; > + }; > + > serdes_ln_ctrl: mux-controller-4080 { > compatible = "mmio-mux"; > #mux-control-cells = <1>; > @@ -777,6 +783,68 @@ cpts@310d0000 { > }; > }; > > + main_cpsw1: ethernet@c200000 { > + compatible = "ti,j721e-cpsw-nuss"; > + #address-cells = <2>; > + #size-cells = <2>; Fix order of your properties. reg/reg-names/ranges follow comaptible. > + reg = <0x00 0xc200000 0x00 0x200000>; > + reg-names = "cpsw_nuss"; > + ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; > + dma-coherent; > + clocks = <&k3_clks 62 0>; > + clock-names = "fck"; > + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; > + > + dmas = <&main_udmap 0xc640>, > + <&main_udmap 0xc641>, > + <&main_udmap 0xc642>, > + <&main_udmap 0xc643>, > + <&main_udmap 0xc644>, > + <&main_udmap 0xc645>, > + <&main_udmap 0xc646>, > + <&main_udmap 0xc647>, > + <&main_udmap 0x4640>; > + dma-names = "tx0", "tx1", "tx2", "tx3", > + "tx4", "tx5", "tx6", "tx7", > + "rx"; > + > + status = "disabled"; > + > + ethernet-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + main_cpsw1_port1: port@1 { > + reg = <1>; > + label = "port1"; > + phys = <&cpsw1_phy_gmii_sel 1>; > + ti,mac-only; > + status = "disabled"; > + }; > + }; > + > + main_cpsw1_mdio: mdio@f00 { > + compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; > + reg = <0x00 0xf00 0x00 0x100>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&k3_clks 62 0>; > + clock-names = "fck"; > + bus_freq = <1000000>; > + }; > + > + cpts@3d000 { Are you sure dtbs_check does not print any warnings? Best regards, Krzysztof