From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: from michel.telenet-ops.be (michel.telenet-ops.be [IPv6:2a02:1800:110:4::f00:18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAB0210C for ; Tue, 21 Nov 2023 01:59:24 -0800 (PST) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:6bd9:a79:1d00:5285]) by michel.telenet-ops.be with bizsmtp id CxzG2B0060Wid3g06xzGQV; Tue, 21 Nov 2023 10:59:22 +0100 Received: from geert (helo=localhost) by ramsan.of.borg with local-esmtp (Exim 4.95) (envelope-from ) id 1r5NXI-009uxV-4U; Tue, 21 Nov 2023 10:59:16 +0100 Date: Tue, 21 Nov 2023 10:59:16 +0100 (CET) From: Geert Uytterhoeven To: Claudiu cc: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: Re: [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset In-Reply-To: <20231120111820.87398-2-claudiu.beznea.uj@bp.renesas.com> Message-ID: References: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> <20231120111820.87398-2-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Hi Claudiu, On Mon, 20 Nov 2023, Claudiu wrote: > From: Claudiu Beznea > > IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and > its reset. > > Signed-off-by: Claudiu Beznea Thanks for your patch! > --- a/drivers/clk/renesas/r9a08g045-cpg.c > +++ b/drivers/clk/renesas/r9a08g045-cpg.c > @@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { > > static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { > DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0), > + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0), This conflicts with [1], which you sent just before. If that patch goes in first, I guess this new entry should gain ", MSTOP(PERI_CPU, BIT(13))", just like the entry for ia55_clk? > DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), > DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), > DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), Reviewed-by: Geert Uytterhoeven [1] "clk: renesas: rzg2l-cpg: Add support for MSTOP" https://lore.kernel.org/r/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds