From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BDA2730C351; Wed, 10 Sep 2025 09:01:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757494870; cv=none; b=PX9vK0EwJt7Um2g0F/gSFy3WukUT7nKjdjNl87lan2YwMbJmV5MFpqenYzAQ6UQu3VT8taioP3aAVWv5kh1dtwHQuRvoTptXSybec0MPPWaEplYcmIXI5JymfLbArXIEFUESOHrGobxEjDe7wyH9PWVxqF5JU90qUtBSDwzIZzs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757494870; c=relaxed/simple; bh=1ejmRaKPPiRElvXHDKAuk+uu/4bmfOebIKtynk7aOV8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=CtF44i0KY9c5jGCskv/kYL7/P8+aJBnz3J9UCgPDbxP56Wz/FCrWFpuDKvpiMfm6ZLeRCROjrFKsiX/v4Q0AY+NZRn8F7kSu+J1eqjdjZ6qECWFZl5ElXytBcDpMCkOBCM2wUPZ/BRJRjNcfWNg32pfzhMOv+hbZzqNSO2HzrlA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D26316F8; Wed, 10 Sep 2025 02:00:58 -0700 (PDT) Received: from [10.1.196.46] (e134344.arm.com [10.1.196.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8718D3F63F; Wed, 10 Sep 2025 02:01:01 -0700 (PDT) Message-ID: Date: Wed, 10 Sep 2025 10:01:00 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 15/33] arm_mpam: Probe MSCs to find the supported partid/pmg values To: James Morse , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org Cc: shameerali.kolothum.thodi@huawei.com, D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Rex Nie , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich References: <20250822153048.2287-1-james.morse@arm.com> <20250822153048.2287-16-james.morse@arm.com> <507919cd-a6d0-42b7-8721-d35f232edfa5@arm.com> From: Ben Horgan Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi James, On 9/9/25 17:56, James Morse wrote: > Hi Ben, > > On 28/08/2025 14:12, Ben Horgan wrote: >> On 8/22/25 16:29, James Morse wrote: >>> CPUs can generate traffic with a range of PARTID and PMG values, >>> but each MSC may have its own maximum size for these fields. >>> Before MPAM can be used, the driver needs to probe each RIS on >>> each MSC, to find the system-wide smallest value that can be used. >>> >>> While doing this, RIS entries that firmware didn't describe are create >>> under MPAM_CLASS_UNKNOWN. >>> >>> While we're here, implement the mpam_register_requestor() call >>> for the arch code to register the CPU limits. Future callers of this >>> will tell us about the SMMU and ITS. > >>> diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c >>> index 9d6516f98acf..012e09e80300 100644 >>> --- a/drivers/resctrl/mpam_devices.c >>> +++ b/drivers/resctrl/mpam_devices.c >>> @@ -106,6 +116,74 @@ static inline u32 _mpam_read_partsel_reg(struct mpam_msc *msc, u16 reg) > >>> +int mpam_register_requestor(u16 partid_max, u8 pmg_max) >>> +{ >>> + int err = 0; >>> + >>> + lockdep_assert_irqs_enabled(); >>> + >>> + spin_lock(&partid_max_lock); >>> + if (!partid_max_init) { >>> + mpam_partid_max = partid_max; >>> + mpam_pmg_max = pmg_max; >>> + partid_max_init = true; >>> + } else if (!partid_max_published) { >>> + mpam_partid_max = min(mpam_partid_max, partid_max); >>> + mpam_pmg_max = min(mpam_pmg_max, pmg_max); > >> Do we really need to reduce these maximum here? If, say, we add an SMMU >> requester which supports fewer partids than the cpus don't we want to be >> able to carry on using those partids from the cpus. In this case the >> SMMU requestor can, without risk of error interrupts, just use all the >> partids it supports. > > How would it do that? > > We're probably going to expose that SMMU, or the devices behind it, via resctrl. You can > create 10 control groups in resctrl - but can't assign the SMMU/devices to the last two > because it doesn't actually support that many... Ok. If that's how it's going to be exposed to the user then it make sense. > > > Thanks, > > James Thanks, Ben