From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matthias Brugger Subject: Re: [GIT PULL] Mediatek: 32-bit DT update for v4.15 Date: Thu, 2 Nov 2017 12:47:05 +0100 Message-ID: References: <1509423579.10793.10.camel@mtkswgap22> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1509423579.10793.10.camel@mtkswgap22> Content-Language: en-US Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Ryder Lee , Arnd Bergmann Cc: arm-soc , Weiqing Kong , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "moderated list:ARM/Mediatek SoC support" , DTML List-Id: devicetree@vger.kernel.org Hi Arnd, On 10/31/2017 05:19 AM, Ryder Lee wrote: > Hi Arnd, > > We have 3 root ports in MT7623, but this is a bug in this chip where the > HW designers wired the IRQs in a nonstandard way. We've tried to > statically assign the bus portion of the address part in the parent > interrupt-map before, but this approach cannot handle the case - if we > attach the device in random order. > Ryder, please don't top post :) > Thanks. > > On Mon, 2017-10-30 at 13:42 +0100, Arnd Bergmann wrote: >> On Mon, Oct 23, 2017 at 12:06 AM, Matthias Brugger >> wrote: >>> >>> ---------------------------------------------------------------- >>> - mt76233 add PCIe node >> >> Could you clarify what the subnodes in the PCI node are for? It seems odd >> to have "interrupt-map" properties in both the pcie controller and its child >> nodes, and I want to ensure this is following the standard PCIe binding before >> I pull it. >> Arnd, I didn't found the pull request in your next/dt branch. Is there more clarification needed from our side? Regards, Matthias -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html