From: Neil Armstrong <neil.armstrong@linaro.org>
To: Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Vikash Garodia <quic_vgarodia@quicinc.com>,
Dikshita Agarwal <quic_dikshita@quicinc.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/7] media: platform: qcom/iris: split iris_vpu_power_off_controller in multiple steps
Date: Thu, 6 Mar 2025 14:06:58 +0100 [thread overview]
Message-ID: <e90eb78c-0bfe-450f-b7ca-f008fa960b32@linaro.org> (raw)
In-Reply-To: <4cacd96b-8d71-4b0a-954b-8d6f4a769f82@linaro.org>
On 06/03/2025 13:34, Bryan O'Donoghue wrote:
> On 05/03/2025 19:05, Neil Armstrong wrote:
>> In order to support vpu33, the iris_vpu_power_off_controller needs to be
>> reused and extended, but the AON_WRAPPER_MVP_NOC_LPI_CONTROL cannot be
>> set from the power_off_controller sequence like vpu2 and vpu3 so
>> split the power_off_controller into 3 steps:
>> - iris_vpu_power_off_controller_begin
>> - iris_vpu_power_off_controller_end
>> - iris_vpu_power_off_controller_disable
>>
>> And use them in a common iris_vpu_power_off_controller() for
>> vpu2 and vpu3 based platforms.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> drivers/media/platform/qcom/iris/iris_vpu_common.c | 46 ++++++++++++++++------
>> 1 file changed, 33 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
>> index fe9896d66848cdcd8c67bd45bbf3b6ce4a01ab10..d6ce92f3c7544e44dccca26bf6a4c95a720f9229 100644
>> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
>> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
>> @@ -211,33 +211,29 @@ int iris_vpu_prepare_pc(struct iris_core *core)
>> return -EAGAIN;
>> }
>>
>> -static int iris_vpu_power_off_controller(struct iris_core *core)
>> +static void iris_vpu_power_off_controller_begin(struct iris_core *core)
>> {
>> - u32 val = 0;
>> - int ret;
>> -
>> writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
>> +}
>>
>> - writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
>> -
>> - ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,
>> - val, val & BIT(0), 200, 2000);
>> - if (ret)
>> - goto disable_power;
>> +static int iris_vpu_power_off_controller_end(struct iris_core *core)
>> +{
>> + u32 val = 0;
>> + int ret;
>>
>> writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
>>
>> ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
>> val, val & BIT(0), 200, 2000);
>> if (ret)
>> - goto disable_power;
>> + return ret;
>>
>> writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
>>
>> ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
>> val, val == 0, 200, 2000);
>> if (ret)
>> - goto disable_power;
>> + return ret;
>>
>> writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
>> core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
>> @@ -245,10 +241,34 @@ static int iris_vpu_power_off_controller(struct iris_core *core)
>> writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
>> writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
>>
>> -disable_power:
>> + return 0;
>> +}
>> +
>> +static void iris_vpu_power_off_controller_disable(struct iris_core *core)
>> +{
>> iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
>> iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
>> iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
>> +}
>> +
>> +static int iris_vpu_power_off_controller(struct iris_core *core)
>> +{
>> + u32 val = 0;
>> + int ret;
>> +
>> + iris_vpu_power_off_controller_begin(core);
>> +
>> + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
>> +
>> + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,
>> + val, val & BIT(0), 200, 2000);
>> + if (ret)
>> + goto disable_power;
>> +
>> + iris_vpu_power_off_controller_end(core);
>> +
>> +disable_power:
>> + iris_vpu_power_off_controller_disable(core);
>>
>> return 0;
>> }
>>
>> --
>> 2.34.1
>>
>>
>
> Have you checked that rb5/sm8250 still works after this change ?
I'm on it, but it doesn't add any functional changes.
Neil
>
> ---
> bod
next prev parent reply other threads:[~2025-03-06 13:07 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-05 19:05 [PATCH v2 0/7] media: qcom: iris: add support for SM8650 Neil Armstrong
2025-03-05 19:05 ` [PATCH v2 1/7] dt-bindings: media: qcom,sm8550-iris: document SM8650 IRIS accelerator Neil Armstrong
2025-03-18 11:24 ` Bryan O'Donoghue
2025-03-24 7:23 ` Vikash Garodia
2025-03-05 19:05 ` [PATCH v2 2/7] media: platform: qcom/iris: split iris_vpu_power_off_controller in multiple steps Neil Armstrong
2025-03-06 12:34 ` Bryan O'Donoghue
2025-03-06 13:06 ` Neil Armstrong [this message]
2025-03-06 13:06 ` Dikshita Agarwal
2025-03-06 13:09 ` Neil Armstrong
2025-03-06 13:14 ` Dikshita Agarwal
2025-03-05 19:05 ` [PATCH v2 3/7] media: platform: qcom/iris: add power_off_controller to vpu_ops Neil Armstrong
2025-03-06 8:22 ` Neil Armstrong
2025-03-05 19:05 ` [PATCH v2 4/7] media: platform: qcom/iris: introduce optional controller_rst_tbl Neil Armstrong
2025-04-06 13:42 ` Bryan O'Donoghue
2025-03-05 19:05 ` [PATCH v2 5/7] media: platform: qcom/iris: rename iris_vpu3 to iris_vpu3x Neil Armstrong
2025-03-06 13:15 ` Dikshita Agarwal
2025-03-05 19:05 ` [PATCH v2 6/7] media: platform: qcom/iris: add support for vpu33 Neil Armstrong
2025-03-05 19:05 ` [PATCH v2 7/7] media: platform: qcom/iris: add sm8650 support Neil Armstrong
2025-03-06 13:16 ` Dikshita Agarwal
2025-03-07 8:38 ` Dmitry Baryshkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e90eb78c-0bfe-450f-b7ca-f008fa960b32@linaro.org \
--to=neil.armstrong@linaro.org \
--cc=bryan.odonoghue@linaro.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-media@vger.kernel.org \
--cc=mchehab@kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=quic_abhinavk@quicinc.com \
--cc=quic_dikshita@quicinc.com \
--cc=quic_vgarodia@quicinc.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox