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Thu, 06 Mar 2025 05:07:01 -0800 (PST) Message-ID: Date: Thu, 6 Mar 2025 14:06:58 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v2 2/7] media: platform: qcom/iris: split iris_vpu_power_off_controller in multiple steps To: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> <20250305-topic-sm8x50-iris-v10-v2-2-bd65a3fc099e@linaro.org> <4cacd96b-8d71-4b0a-954b-8d6f4a769f82@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <4cacd96b-8d71-4b0a-954b-8d6f4a769f82@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 06/03/2025 13:34, Bryan O'Donoghue wrote: > On 05/03/2025 19:05, Neil Armstrong wrote: >> In order to support vpu33, the iris_vpu_power_off_controller needs to be >> reused and extended, but the AON_WRAPPER_MVP_NOC_LPI_CONTROL cannot be >> set from the power_off_controller sequence like vpu2 and vpu3 so >> split the power_off_controller into 3 steps: >> - iris_vpu_power_off_controller_begin >> - iris_vpu_power_off_controller_end >> - iris_vpu_power_off_controller_disable >> >> And use them in a common iris_vpu_power_off_controller() for >> vpu2 and vpu3 based platforms. >> >> Signed-off-by: Neil Armstrong >> --- >>   drivers/media/platform/qcom/iris/iris_vpu_common.c | 46 ++++++++++++++++------ >>   1 file changed, 33 insertions(+), 13 deletions(-) >> >> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c >> index fe9896d66848cdcd8c67bd45bbf3b6ce4a01ab10..d6ce92f3c7544e44dccca26bf6a4c95a720f9229 100644 >> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c >> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c >> @@ -211,33 +211,29 @@ int iris_vpu_prepare_pc(struct iris_core *core) >>       return -EAGAIN; >>   } >> >> -static int iris_vpu_power_off_controller(struct iris_core *core) >> +static void iris_vpu_power_off_controller_begin(struct iris_core *core) >>   { >> -    u32 val = 0; >> -    int ret; >> - >>       writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH); >> +} >> >> -    writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); >> - >> -    ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, >> -                 val, val & BIT(0), 200, 2000); >> -    if (ret) >> -        goto disable_power; >> +static int iris_vpu_power_off_controller_end(struct iris_core *core) >> +{ >> +    u32 val = 0; >> +    int ret; >> >>       writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); >> >>       ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS, >>                    val, val & BIT(0), 200, 2000); >>       if (ret) >> -        goto disable_power; >> +        return ret; >> >>       writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); >> >>       ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS, >>                    val, val == 0, 200, 2000); >>       if (ret) >> -        goto disable_power; >> +        return ret; >> >>       writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT, >>              core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); >> @@ -245,10 +241,34 @@ static int iris_vpu_power_off_controller(struct iris_core *core) >>       writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); >>       writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); >> >> -disable_power: >> +    return 0; >> +} >> + >> +static void iris_vpu_power_off_controller_disable(struct iris_core *core) >> +{ >>       iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); >>       iris_disable_unprepare_clock(core, IRIS_AXI_CLK); >>       iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); >> +} >> + >> +static int iris_vpu_power_off_controller(struct iris_core *core) >> +{ >> +    u32 val = 0; >> +    int ret; >> + >> +    iris_vpu_power_off_controller_begin(core); >> + >> +    writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); >> + >> +    ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, >> +                 val, val & BIT(0), 200, 2000); >> +    if (ret) >> +        goto disable_power; >> + >> +    iris_vpu_power_off_controller_end(core); >> + >> +disable_power: >> +    iris_vpu_power_off_controller_disable(core); >> >>       return 0; >>   } >> >> -- >> 2.34.1 >> >> > > Have you checked that rb5/sm8250 still works after this change ? I'm on it, but it doesn't add any functional changes. Neil > > --- > bod