From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7307C19F464; Mon, 6 Oct 2025 09:35:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759743333; cv=none; b=JrWVuLRlnpt9+rrGlH8PB8GPRpIuuJLkldFy3NJpwXoyBOR0tZI0zzbQmK2q14S9UiCoEHoXSbJvb85DEzzpf6k72J/kC059CkoRtHJh/PyjT726nqEhKjgjccypCHWX0gPD2vCKsIgkAh5AEWKhF47lftTp1Cijyx2DpOt5PgI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759743333; c=relaxed/simple; bh=Zk8Jo5SPmzAsmHMFK8+ptR1vnmkxF9QjVRBwUXv/GcQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=VCK3iosBcj5TZ+EXx+4MFJaiQNtJC+GDDdkYuQLOAm9Xw0A+amRWt4gb71KDKnljuv1yqV14bpW3AIMJpriV/J6iP5FIOnR+iXeWnUm8Ygr1CK1ckPuNbkbRk1DKgCRNSf64fI7KfLzsY7ZiOmlOwsYqQn1Q0nONnXnLxBPCdIw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=lZVnTSMd; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="lZVnTSMd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1759743329; bh=Zk8Jo5SPmzAsmHMFK8+ptR1vnmkxF9QjVRBwUXv/GcQ=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=lZVnTSMdtFXdu9MAyZ4uke97TZskIr4QYzIH9ZEwEq5Kjo/T1Qwi/eagTJodWRdoU fAAn1tBR7rwBTkz/46bBSXS9W0co3anMfYBIuZBvZZ6Fvn2Y/25g3+dlIHBfFDj90w Xwti81iw1rHNLI8p0QR1GBtVff/pcpBH2y8iN08nE/8d/eos2M0aYGXZRrvx+svaZu zvkoxLSbh+q3i3d5WG+8BMiauD8TGkEO9qdtYNjaFMMDKJTFSrwpncqe+r7CpHrvIU Gd75dNAEMJT8eQA2KttK8aKdxsFk+oeoLznjhQg4qwHsxhgXNUIjcI8ODxTo8hcp0G oBLRNjIuYXN3g== Received: from [192.168.1.100] (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id B079417E0FC2; Mon, 6 Oct 2025 11:35:28 +0200 (CEST) Message-ID: Date: Mon, 6 Oct 2025 11:35:28 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/7] dt-bindings: gpu: mali-valhall-csf: add mediatek,mt8196-mali variant To: Nicolas Frattaroli , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org References: <20251003-mt8196-gpufreq-v6-0-76498ad61d9e@collabora.com> <20251003-mt8196-gpufreq-v6-1-76498ad61d9e@collabora.com> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: <20251003-mt8196-gpufreq-v6-1-76498ad61d9e@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 03/10/25 22:15, Nicolas Frattaroli ha scritto: > The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to > control the power and frequency of the GPU. This is modelled as a power > domain and clock provider. > > It lets us omit the OPP tables from the device tree, as those can now be > enumerated at runtime from the MCU. > > Add the necessary schema logic to handle what this SoC expects in terms > of clocks and power-domains. > > Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno