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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id d11-20020ac2544b000000b004f4e637db2fsm1484450lfn.167.2023.05.29.02.08.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 May 2023 02:08:47 -0700 (PDT) Message-ID: Date: Mon, 29 May 2023 11:08:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 0/5] MDSS reg bus interconnect Content-Language: en-US To: Dmitry Baryshkov Cc: Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> <74a817ff-5850-330d-8cac-f551be6fa35c@linaro.org> <254cd131-4ad1-44c9-2653-862580503c15@linaro.org> From: Konrad Dybcio In-Reply-To: <254cd131-4ad1-44c9-2653-862580503c15@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 29.05.2023 10:47, Dmitry Baryshkov wrote: > On 29/05/2023 10:42, Konrad Dybcio wrote: >> >> >> On 29.05.2023 04:42, Dmitry Baryshkov wrote: >>> On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote: >>>> >>>> Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's >>>> another path that needs to be handled to ensure MDSS functions properly, >>>> namely the "reg bus", a.k.a the CPU-MDSS interconnect. >>>> >>>> Gating that path may have a variety of effects.. from none to otherwise >>>> inexplicable DSI timeouts.. >>>> >>>> This series tries to address the lack of that. >>>> >>>> Example path: >>>> >>>> interconnects = <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_DISPLAY_CFG 0>; >>> >>> If we are going to touch the MDSS interconnects, could you please also >>> add the rotator interconnect to the bindings? >>> We do not need to touch it at this time, but let's not have to change >>> bindings later again. >>> >> Ack > > Also, several points noted from the mdss fbdev driver: > > - All possible clents vote for the low bw setting. This includes DSI, HDMI, MDSS itself and INTF As in, "you need NUM_CLIENTS * MIN_VOTE" or as in "any client necessitates a vote"? > - SMMU also casts such vote, which I do not think should be necessary, unless there is a separate MDSS SMMU? There's one on 8996, pre-845 SoCs often have a MMSS MMU, 845 and later have a MMSS-specific TBU which (theoretically) requires a vote for access to 0x400-0x7ff SIDs > - PINGPONG cacsts high bw setting for the sake of speeding up the LUT tables if required. Hm, I think is would be a separate topic. Konrad >