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From: Krzysztof Kozlowski <krzk@kernel.org>
To: "Jason-JH Lin (林睿祥)" <Jason-JH.Lin@mediatek.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"Singo Chang (張興國)" <Singo.Chang@mediatek.com>,
	"linux-media@vger.kernel.org" <linux-media@vger.kernel.org>,
	"chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"simona@ffwll.ch" <simona@ffwll.ch>,
	"mchehab@kernel.org" <mchehab@kernel.org>,
	"Nancy Lin (林欣螢)" <Nancy.Lin@mediatek.com>,
	"Moudy Ho (何宗原)" <Moudy.Ho@mediatek.com>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"robh@kernel.org" <robh@kernel.org>,
	Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	"airlied@gmail.com" <airlied@gmail.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	"Xavier Chang (張獻文)" <Xavier.Chang@mediatek.com>,
	"jassisinghbrar@gmail.com" <jassisinghbrar@gmail.com>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>
Subject: Re: [PATCH v2 1/8] dt-bindings: mailbox: mediatek: Add GCE header file for MT8196
Date: Thu, 12 Dec 2024 08:20:37 +0100	[thread overview]
Message-ID: <e9caf0fe-a77f-40cb-9fc3-9da3d95f27ca@kernel.org> (raw)
In-Reply-To: <04f7bd2a7d69ab7d02c88cf05bda5ae0c4cb6573.camel@mediatek.com>

On 12/12/2024 04:05, Jason-JH Lin (林睿祥) wrote:
> Hi Krzysztof,
> 
> Thanks for the reviews.
> 
> On Wed, 2024-12-11 at 10:37 +0100, Krzysztof Kozlowski wrote:
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>
>>
>> On Wed, Dec 11, 2024 at 11:22:49AM +0800, Jason-JH.Lin wrote:
>>> Add the Global Command Engine (GCE) header file to define the GCE
>>> thread priority, GCE subsys ID and GCE events for MT8196.
>>
>> This we see from the diff. What we do not see is why priority is a
>> binding. Looking briefly at existing code: it is not a binding, there
>> is
>> no driver user.
>>
> 
> This priority value is used to configure the priority level for each
> GCE hardware thread, so it is a necessary hardware attribute.

I did not say these are not "hardware". I said these are not bindings.
Bring arguments why these are bindings.

> 
> It's hard to find where the priority is used in existing driver code
> because we parsed it from DTS.

So not a binding.

> 
> It is used in all mediaTeks' DTS using the GCE.
> For example, in mt8195.dts:
> 
> vdosys0: syscon@1c01a000 {
>     compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys",
> "syscon";
>     reg = <0 0x1c01a000 0 0x1000>;
>     mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
>     #clock-cells = <1>;
>     mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
> }
> 
> CMDQ driver(mtk-cmdq-mailbox.c) will get the args parsed from mboxes
> property in cmdq_xlate() and then it will store CMDQ_THR_PRIO_4 to the
> specific thread structure. 

So not a binding.

> The user of CMDQ driver will send command to CMDQ driver by 
> cmdq_mbox_send_data(), and this priority setting will be configured to
> GCE hardware thread.

And other things there are the same, we do not talk only about this one
thing. I asked last time to drop which is not a binding.


...

>>> +
>>> +/*
>>> + * GCE General Purpose Register (GPR) support
>>> + * Leave note for scenario usage here
>>> + */
>>> +/* GCE: write mask */
>>
>> That's a definite no-go. Register masks are not bindings.
>>
> 
> I'm sorry to the confusion.
> 
> These defines are the index of GCE General Purpose Register for
> generating instructions, they are not register masks.

Index of register is also sounding like register.

> 
> The comment "/* GCE: write mask */" is briefly describe that the usage
> of GCE_GPR_R0 and GCE_GPR_R01 is used to store the register mask when
> GCE executing the WRITE instruction. And it can also store the register
> mask of POLL and READ instruction.
> 
> I will add more words to make this comment clearer, like this:
> /*GCE: store the mask of instruction */

Not sure, because I feel you just avoid doing what is right and keep
pushing your own narrative. Where is it used in the driver?

I just looked for "GCE_GPR_R00" - no usage at all. So not a binding.

Best regards,
Krzysztof

  reply	other threads:[~2024-12-12  7:20 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-11  3:22 [PATCH v2 0/8] Add GCE support for MT8196 Jason-JH.Lin
2024-12-11  3:22 ` [PATCH v2 1/8] dt-bindings: mailbox: mediatek: Add GCE header file " Jason-JH.Lin
2024-12-11  9:37   ` Krzysztof Kozlowski
2024-12-12  3:05     ` Jason-JH Lin (林睿祥)
2024-12-12  7:20       ` Krzysztof Kozlowski [this message]
2024-12-12 11:24         ` Jason-JH Lin (林睿祥)
2024-12-12 12:23           ` Krzysztof Kozlowski
2024-12-12 18:06             ` Jason-JH Lin (林睿祥)
2024-12-11  3:22 ` [PATCH v2 2/8] dt-bindings: mailbox: mediatek: Add MT8196 support for gce-mailbox Jason-JH.Lin
2024-12-11  9:39   ` Krzysztof Kozlowski
2024-12-12  3:41     ` Jason-JH Lin (林睿祥)
2024-12-12  7:20       ` Krzysztof Kozlowski
2024-12-12 11:25         ` Jason-JH Lin (林睿祥)
2024-12-11  3:22 ` [PATCH v2 3/8] mailbox: mtk-cmdq: Add driver data to support for MT8196 Jason-JH.Lin
2024-12-11  3:22 ` [PATCH v2 4/8] soc: mediatek: mtk-cmdq: Add pa_base parsing for unsupported subsys ID hardware Jason-JH.Lin
2024-12-11  3:22 ` [PATCH v2 5/8] soc: mediatek: mtk-cmdq: Add mminfra_offset compatibility for DRAM address Jason-JH.Lin
2024-12-11  3:22 ` [PATCH v2 6/8] soc: mediatek: Add programming flow for unsupported subsys ID hardware Jason-JH.Lin
2024-12-11 22:17   ` kernel test robot
2024-12-11 22:39   ` kernel test robot
2024-12-11  3:22 ` [PATCH v2 7/8] drm/mediatek: " Jason-JH.Lin
2024-12-11  3:46   ` CK Hu (胡俊光)
2024-12-11  4:04     ` CK Hu (胡俊光)
2024-12-12  3:48       ` Jason-JH Lin (林睿祥)
2024-12-11  3:22 ` [PATCH v2 8/8] media: mediatek: mdp3: " Jason-JH.Lin

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