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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bccfd8ebbsm26141096b3a.102.2025.08.11.00.30.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Aug 2025 00:30:16 -0700 (PDT) Message-ID: Date: Mon, 11 Aug 2025 15:30:08 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 0/2] pci: qcom: Add QCS615 PCIe support To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com References: <20250725112346.614316-1-ziyue.zhang@oss.qualcomm.com> Content-Language: en-US From: Ziyue Zhang In-Reply-To: <20250725112346.614316-1-ziyue.zhang@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=J+Wq7BnS c=1 sm=1 tr=0 ts=68999c0a cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=0rveLjV9VWli9pvRdbwA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: OEqvrSsQ7bM_XvMJQpvRQ5BqLvwJ2H3K X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA5MDAxNSBTYWx0ZWRfX3HxBi+hK+Dyl YN+EWyf8A2vMDWd3RsDLEsq/8MoS095yfbPW9U0E2r9bMHrBYyYSW8xtvs+opi4UGcqBETm5gEN JwL21iBh3GG9GSw8Ts2/RpIEDEhOHwDfTN171p9OM+7NEXX+O1h21rFooyyZgnxunMb9UimiHnw 23oeXk/bxfCExcH1kzlSb0cMkHOCWZms9kB4KcC3JrH/v91SdQAh/AEPwJdJD0tmyBp4u+KsvfD LfAfrD+0DTAaxrf+6lEE8BZD7E7WcAVxewzdpRxQ9DDlvo2P4iIcHfhcgVEowiCgcFORlwE1QAz wDQcHW4Qm4Py3huL5i8JlbNlkjBTZI2SG2Qph4UBRv0ZAq2i0KkgIqFnY0YEg/9E38VArOvZe54 v0HbFUDO X-Proofpoint-GUID: OEqvrSsQ7bM_XvMJQpvRQ5BqLvwJ2H3K X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-11_01,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508090015 On 7/25/2025 7:23 PM, Ziyue Zhang wrote: > This series adds document, phy, configs support for PCIe in QCS615. > > This series depend on the dt-bindings change > https://lore.kernel.org/all/20250521-topic-8150_pcie_drop_clocks-v1-0-3d42e84f6453@oss.qualcomm.com/ > > Signed-off-by: Krishna chaitanya chundru > Signed-off-by: Ziyue Zhang > --- > Have following changes: > - Add a new Document the QCS615 PCIe Controller > - Add configurations in devicetree for PCIe, including registers, clocks, interrupts and phy setting sequence. > - Add configurations in devicetree for PCIe, platform related gpios, PMIC regulators, etc. > > Changes in v9: > - Patch rebased > - Link to v8: https://lore.kernel.org/all/20250703095630.669044-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v8: > - Fix scripts/checkpatch.pl error (Krzystof) > - Link to v7: https://lore.kernel.org/all/20250702103549.712039-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v7: > - Add Fixes tag to phy bindings patch (Johan) > - QCS615 is Gen3 controller but Gen2 phy, so limited max link speed to Gen2. > - Remove eq-presets-8gts and oppopp-8000000 for only support Gen2. > - Link to v6: https://lore.kernel.org/all/t6bwkld55a2dcozxz7rxnvdgpjis6oveqzkh4s7nvxgikws4rl@fn2sd7zlabhe/ > > Changes in v6: > - Change PCIe equalization setting to one lane > - Add reviewed by tags > - Link to v5: https://lore.kernel.org/all/t6bwkld55a2dcozxz7rxnvdgpjis6oveqzkh4s7nvxgikws4rl@fn2sd7zlabhe/ > > Changes in v5: > - Drop qcs615-pcie.yaml and use sm8150, as qcs615 is the downgraded > version of sm8150, which can share the same yaml. > - Drop compatible enrty in driver and use sm8150's enrty (Krzysztof) > - Fix the DT format problem (Konrad) > - Link to v4: https://lore.kernel.org/all/20250507031559.4085159-1-quic_ziyuzhan@quicinc.com/ > > Changes in v4: > - Fixed compile error found by kernel test robot(Krzysztof) > - Update DT format (Konrad & Krzysztof) > - Remove QCS8550 compatible use QCS615 compatible only (Konrad) > - Update phy dt bindings to fix the dtb check errors. > - Link to v3: https://lore.kernel.org/all/20250310065613.151598-1-quic_ziyuzhan@quicinc.com/ > > Changes in v3: > - Update qcs615 dt-bindings to fit the qcom-soc.yaml (Krzysztof & Dmitry) > - Removed the driver patch and using fallback method (Mani) > - Update DT format, keep it same with the x1e801000.dtsi (Konrad) > - Update DT commit message (Bojor) > - Link to v2: https://lore.kernel.org/all/20241122023314.1616353-1-quic_ziyuzhan@quicinc.com/ > > Changes in v2: > - Update commit message for qcs615 phy > - Update qcs615 phy, using lowercase hex > - Removed redundant function > - split the soc dtsi and the platform dts into two changes > - Link to v1: https://lore.kernel.org/all/20241118082619.177201-1-quic_ziyuzhan@quicinc.com/ > > > Krishna chaitanya chundru (2): > arm64: dts: qcom: qcs615: enable pcie > arm64: dts: qcom: qcs615-ride: Enable PCIe interface > > arch/arm64/boot/dts/qcom/qcs615-ride.dts | 42 +++++++ > arch/arm64/boot/dts/qcom/sm6150.dtsi | 138 +++++++++++++++++++++++ > 2 files changed, 180 insertions(+) > > > base-commit: d7af19298454ed155f5cf67201a70f5cf836c842 Hi Maintainers, It seems the patches get reviewed tag for a long time, can you give this series further comment or help me to merge them ? Thanks very much. BRs Ziyue