From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CC15194C78; Wed, 29 Jan 2025 09:47:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738144076; cv=none; b=uTEokbIZ4st4Ku87EDVpG9f3FZc7Ys46Xmhq14zOYhSTxHlvosaPSRvaQOYxo1mAL37ohM4HUO6Yntz50ghHSD515i/tn/nVT+zrEOvzwzoDkKwduI6EJrPqTYN0NwD/b2aTklNCsL3d52AyzNPP1YhX5dkja903o2Cdm2zZRSk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738144076; c=relaxed/simple; bh=gtZgByV3yfC1Ara8kuE21FImn1XoVMsWDvQ8Ijdajk8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=cq1pqOq2B7im1MHxfZv/o9WlMg6kegmBK+OYtTmWWrcpqhQbj5CSxSz9C8DEJVbpNMZUUhimMnMEGy7V+9dQiAN1nncWPqG0rmsIu2V5I1+BmlUNzsix7XKBe4MbsSKDqb5XHixzqy6dWfVYbIw39PgyWuKC7RbY0T2J/CRPI5Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K99pt4KH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K99pt4KH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54DFFC4CED3; Wed, 29 Jan 2025 09:47:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738144075; bh=gtZgByV3yfC1Ara8kuE21FImn1XoVMsWDvQ8Ijdajk8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=K99pt4KHCUegmavMIy4OQXMqzj53B8KSW6lMyB8e0A7r3TtyaDJFoU+Dc8DvS3HRq yexoKG7aiBILOIfT/MqVnnhZnYTdQqxRn90mP/RKFZTig/dPCd/cEua4BYOFmCE274 tt/iFP/6I9BDJ5tw+W1HWOp5f/2BMVqREEHwX8KB4AkvIkrWlj8fya0Wh73ZjRyirp mlhEvlqTe+9lRfKRoQFn/cMkd8VT4PC6q9ilslY5rOWaaBKX+qCuZ+/LwIXVLe/IOA WbwU0W+INPNMeclp7pxCDNYBQdrGe96nN/nZYwC/t6JlSMHmS7W7WZ3DpsfvHhDkb8 jTe6YhVQNlZsA== Message-ID: Date: Wed, 29 Jan 2025 10:47:49 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/5] arm64: dts: agilex: add dtsi for PCIe Root Port To: Matthew Gerlach , lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, joyce.ooi@intel.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: matthew.gerlach@altera.com, peter.colberg@altera.com References: <20250127173550.1222427-1-matthew.gerlach@linux.intel.com> <20250127173550.1222427-4-matthew.gerlach@linux.intel.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 27/01/2025 18:35, Matthew Gerlach wrote: > Add the base device tree for support of the PCIe Root Port > for the Agilex family of chips. > > Signed-off-by: Matthew Gerlach > --- > v3: > - Remove accepted patches from patch set. > > v2: > - Rename node to fix schema check error. > --- > .../intel/socfpga_agilex_pcie_root_port.dtsi | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi > > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi > new file mode 100644 > index 000000000000..50f131f5791b > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi > @@ -0,0 +1,55 @@ > +// SPDX-License-Identifier: GPL-2.0 Odd spaces in SPDX tag. > +/* > + * Copyright (C) 2024, Intel Corporation > + */ > +&soc0 { > + aglx_hps_bridges: fpga-bus@80000000 { > + compatible = "simple-bus"; > + reg = <0x80000000 0x20200000>, > + <0xf9000000 0x00100000>; > + reg-names = "axi_h2f", "axi_h2f_lw"; Where is this binding defined? > + #address-cells = <0x2>; > + #size-cells = <0x1>; These two are not hex. > + ranges = <0x00000000 0x00000000 0x80000000 0x00040000>, > + <0x00000000 0x10000000 0x90100000 0x0ff00000>, > + <0x00000000 0x20000000 0xa0000000 0x00200000>, > + <0x00000001 0x00010000 0xf9010000 0x00008000>, > + <0x00000001 0x00018000 0xf9018000 0x00000080>, > + <0x00000001 0x00018080 0xf9018080 0x00000010>; > + > + pcie_0_pcie_aglx: pcie@200000000 { > + reg = <0x00000000 0x10000000 0x10000000>, > + <0x00000001 0x00010000 0x00008000>, > + <0x00000000 0x20000000 0x00200000>; > + reg-names = "Txs", "Cra", "Hip"; Where is this binding defined? > + interrupt-parent = <&intc>; > + interrupts = ; > + interrupt-controller; > + #interrupt-cells = <0x1>; > + device_type = "pci"; > + bus-range = <0x0000000 0x000000ff>; > + ranges = <0x82000000 0x00000000 0x00100000 0x00000000 0x10000000 0x00000000 0x0ff00000>; > + msi-parent = <&pcie_0_msi_irq>; > + #address-cells = <0x3>; > + #size-cells = <0x2>; Same problem for all cells. > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_0_pcie_aglx 0 0 0 0x1>, > + <0x0 0x0 0x0 0x2 &pcie_0_pcie_aglx 0 0 0 0x2>, > + <0x0 0x0 0x0 0x3 &pcie_0_pcie_aglx 0 0 0 0x3>, > + <0x0 0x0 0x0 0x4 &pcie_0_pcie_aglx 0 0 0 0x4>; > + status = "disabled"; > + }; > + > + pcie_0_msi_irq: msi@10008080 { > + compatible = "altr,msi-1.0"; > + reg = <0x00000001 0x00018080 0x00000010>, > + <0x00000001 0x00018000 0x00000080>; > + reg-names = "csr", "vector_slave"; > + interrupt-parent = <&intc>; > + interrupts = ; > + msi-controller; > + num-vectors = <0x20>; That's decimal. Value is for humans and we count numbers in decimal. Best regards, Krzysztof